User guide

Where: C
0
is the main cursor (boost), C
-1
is the pre-cursor (pre-shoot), and C
+1
is the post-cursor (de-
emphasis).
3. This process is repeated until the downstream component's receiver achieves a BER of < 10
-12
Phase 3 (Optional)
During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2
but operates in the opposite direction.
You cannot perform Phase 3 tuning, when you are using the PHY IP Core for PCI Express (PIPE) as a
Root Port.
After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending EC=2’b00, and the
final coefficients or preset agreed upon in Phase 2. The Endpoint moves to Recovery.RcvrLock using the
final coefficients or preset agreed upon in Phase 3.
Recommendations for Tuning Link
To improve the BER of the receiver, Altera recommends that you turn on CTLE during Phase 2 Equaliza‐
tion for Endpoints or Phase 3 Equalization for Root Ports. You enable CTLE in different modes.
Note:
Refer to the CTLE section of this document for more details.
Related Information
• Continuous Time Linear Equalization (CTLE) on page 5-6
• PCI Express Base Specification
• PIPE Specification
Design Example
The PIPE Design Example, located on the Arria 10 Transceiver PHY Design Examples Wiki page,
demonstrates the connectivity between several IPs that form a complete PCIe design. The example
contains the following components:
• PHY—Native PHY IP Core configured for PIPE Gen1x4, Gen2x8, Gen3x1 or Gen3 x8 mode
• ATX PLL—PLL used for Gen3 data rate
• fPLL—PLL used for Gen1, Gen2 data rates
• Reset controller
• MAC
• Data generator
The design example exercises the PIPE-specific features and blocks. The pseudo-MAC exercises the
control signals and implements part of the LTSSM. The data generator and checker can generate and
verify ordered sets such as TS1, TS2, EIOS, EIEOS, and SKP OS. They can also scramble and descramble
data while operating at Gen3 rates.
The PIPE Design Example User Guide, located in the PIPE Design File on the Wiki page, contains
recommendations about SDC timing constraints.
Note:
The design examples on the Wiki page provide useful guidance for developing your own designs,
but they are not guaranteed by Altera. Use them with caution.
Related Information
PIPE Design Example
UG-01143
2015.05.11
Design Example
2-267
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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