User guide

Receiver Detection
The PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopback
for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state
of the LTSSM. When the pipe_tx_detectrx_loopback signal is asserted in the P1 power state, the PIPE
interface block sends a command signal to the transmitter driver in that channel to initiate a receiver
detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state.
After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the
transmitter buffer. The time constant of the step voltage on the trace increases if an active receiver that
complies with the PCIe input impedance requirements is present at the far end. The receiver detect
circuitry monitors this time constant to determine if a receiver is present.
Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be
used. Also, the AC-coupling capacitor on the serial link and the receiver termination values used in
your system must be compliant with the PCIe Base Specification 2.0.
The PIPE core provides a 1-bit PHY status signal
pipe_phy_status and a 3-bit receiver status signal
pipe_rx_status[2:0] to indicate whether a receiver is detected, as per the PIPE 2.0 specifications.
Gen1 and Gen2 Clock Compensation
In compliance with the PIPE specification, Arria 10 receiver channels have a rate match FIFO to
compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and
the local receiver clocks.
Consider the following guidelines for PIPE clock compensation:
• Insert or delete one SKP symbol in an SKP ordered set.
• Minimum limit is imposed on the number of SKP symbols in SKP ordered set after deletion. An
ordered set may have an empty COM case after deletion.
• Maximum limit is imposed on the number of the SKP symbols in the SKP ordered set after insertion.
An ordered set may have more than five symbols after insertion.
• For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where
insertion or deletion occurs.
• For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.
Note:
When the PIPE interface is on, it translates the value of the flag to the appropriate
pipe_rx_status signal.
• The PIPE mode also has a “0 ppm” configuration option that you can use in synchronous systems. The
Rate Match FIFO Block is not expected to do any clock compensation in this configuration, but latency
will be minimized.
2-232
Receiver Detection
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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