User guide
Address Bit R/W Name Description
0x466 0 RO pma_rx_is_
lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode.
0x467 0 RO pma_rx_is_
lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock.
Speed Change Summary
Table 2-138: Speed Change Summary
Speed Change Speed Change Method Detailed Information
1GbE and 10GBASE-R Interface Signals
• Refer to Dynamic Reconfiguration
Interface.
• Figure 2-61
SGMII (10M, 100M and 1GbE) Avalon-MM bus Table 2-115
1GbE, 10GBASE-R, and 10GBASE-R
with FEC
Avalon-MM bus Table 2-134
Note: You can configure the static speed while generating the IP core using the IP Parameter Editor.
Related Information
Dynamic Reconfiguration Interface on page 2-138
Creating a 1G/10GbE Design
Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
1. Generate the 1G/10GbE PHY with the required parameterization.
The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the Avalon-MM
interface that you can use to read and write to PHY registers. All read and write operations must
adhere to the Avalon specification.
2. Instantiate a reset controller using the Transceiver Reset Controller Megafunction in the IP Catalog.
Connect the power and reset signals between the 1G/10GbE PHY and the reset controller.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate. Connect the high
speed serial clock and PLL lock signals between 1G/10GbE PHY and TX PLLs. You can use any
combination of fPLLs, ATX, or CMU PLLs.
4. Use the tx_pma_divclk from 1G/10GbE PHY or generate a fPLL to create the 156.25 MHz XGMII
clock from the 10G reference clock.
No Memory Initialization Files (.mif) are required for the 1G/10GbE design in Arria 10 devices.
5. Complete the design by creating a top level module to connect all the IP (1G/10GbE PHY IP, PLL IP
and Reset Controller) blocks.
Related Information
• fPLL on page 3-13
• CMU PLL on page 3-21
2-208
Speed Change Summary
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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