User guide

10GBASE-KR PHY Register Definitions
The Avalon-MM slave interface signals provide access to the control and status registers.
The following table specifies the control and status registers that you can access over the Avalon-MM
PHY management interface. A single address space provides access to all registers.
Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
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10GBASE-KR PHY Register Definitions
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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