User guide

Name Direction Clock Domain Description
rx_errdetect[<n>
<w>/<s>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates a code group violation
detected on the received code group. Used along
with rx_disperr signal to differentiate between
code group violation and disparity errors. The
following encodings are defined for rx_errdetect/
rx_disperr:
• 2'b00: no error
• 2'b10: code group violation
• 2'b11: disparity error. rx_errdetect is a part of
rx_parallel_data. For each 128-bit word, rx_
errdetect corresponds to rx_parallel_
data[9].
rx_disperr[<n><w>/
<s>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates a disparity error on the
received code group. rx_disperr is a part of rx_
parallel_data. For each 128-bit word, rx_disperr
corresponds to rx_parallel_data[11].
rx_runningdisp[<n>
<w>/<s>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When high, indicates that rx_parallel_data was
received with negative disparity. When low,
indicates that rx_parallel_data was received with
positive disparity. rx_runningdisp is a part of rx_
parallel_data. For each 128 bit word, rx_
runningdisp corresponds to rx_parallel_
data[15].
rx_patternde-
tect[<n><w>/<s>-
1:0]
Output Asynchronous When asserted, indicates that the programmed word
alignment pattern has been detected in the current
word boundary. rx_patterndetect is a part of rx_
parallel_data. For each 128-bit word, rx_
patterndetect corresponds to rx_parallel_
data[12].
rx_syncstatus[<n>
<w>/<s>-1:0]
Output Asynchronous When asserted, indicates that the conditions
required for synchronization are being met. rx_
syncstatus is a part of rx_parallel_data. For
each 128-bit word, rx_syncstatus corresponds to
rx_parallel_data[10].
Table 2-65: Word Aligner and Bitslip
Name Direction Clock Domain Description
2-72
Standard PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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