User guide

Name Direction Clock Domain Description
rx_std_rmfifo_
empty[<n>-1:0]
Output Asynchronous Rate match FIFO empty flag. When asserted, match
FIFO is empty. You must synchronize this signal.
This port is only used for GigE mode.
rx_rmfifostatus[<n>
-1:0]
Output Asynchronous Indicates FIFO status. The following encodings are
defined:
• 2'b00: Normal operation
• 2'b01: Deletion, rx_std_rmfifo_full = 1
• 2'b10: Insertion, rx_std_rmfifo_empty = 1
• 2'b11: Full. rx_rmfifostatus is a part of rx_
parallel_data. rx_rmfifostatus corresponds
to rx_parallel_data[14:13].
Table 2-64: 8B/10B Encoder and Decoder
Name Direction Clock Domain Description
tx_datak
Input tx_clkout
tx_datak is exposed if 8B/10B enabled and
simplified data interface is set.When 1, indicates that
the 8B/10B encoded word of tx_parallel_data is
control. When 0, indicates that the 8B/10B encoded
word of tx_parallel_data is data. tx_datak is a
part of tx_parallel_data when simplified data
interface is not set.
tx_forcedisp[<n>
(<w>/<s>-1:0]
Input Asynchronous This signal allows you to force the disparity of the
8B/10B encoder. When "1", forces the disparity of
the output data to the value driven on tx_dispval.
When "0", the current running disparity continues.
tx_forcedisp is a part of tx_parallel_data. tx_
forcedisp corresponds to tx_parallel_data[9].
tx_dispval[<n>(<w>
/<s>-1:0]
Input Asynchronous Specifies the disparity of the data. tx_dispval is a
part of tx_parallel_data. tx_dispval
corresponds to tx_dispval[10].
rx_datak[<n><w>/
<s>-1:0]
Output rx_clkout rx_datak is exposed if 8B/10B is enabled and
simplified data interface is set. When 1, indicates
that the 8B/10B decoded word of rx_parallel_data is
control. When 0, indicates that the 8B/10B decoded
word of rx_parallel_data is data. rx_datak is a
part of rx_parallel_data when simplified data
interface is not set.
UG-01143
2015.05.11
Standard PCS Ports
2-71
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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