Datasheet

AS4C32M16D1A-C&I
2 Rev. 1.0 Mar. /2015
Overview
The 512Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM
containing 512 Mbits. It is internally configured as a quad 8M x 16 DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs
occur at both rising edges of CK and
CK
. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of
locations in a programmed sequence. Accesses begin with the registration of a BankActivate
command which is then followed by a Read or Write command. The device provides
programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are easy to use. In addition, 512Mb DDR
features programmable DLL option. By having a programmable mode register and extended
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth, result in a
device particularly well suited to high performance main memory and graphics applications.
Table 1. Ordering Information
Part Number
Clock Frequency
Data Rate
Package
Temperature
Temp Range
AS4C32M16D1A -5TCN
200 MHz
400Mbps/Pin
66 pin TSOP II
Commercial
0~70 ℃
AS4C32M16D1A -5TIN
200 MHz
400Mbps/Pin
66 pin TSOP II
Industrial
-40~85 ℃
T : indicates TSOP II package
C: Commercial I: Industrial
N : indicates Pb free and Halogen free