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EL67I1B16_DDR3-2000X(CL=9)_2GB(128Mx8_Pb free) Rev.0 2009/01/16 Page 2 of 7

General DescriptionΚ

ΚΚ

The ADATA’s EL67I1B16 is a 256Mx64 bits 2GB(2048MB) DDR3-2000(CL9) SDRAM XMP memory module,

The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9-9-9-24 at 1.5V. The module is composed

of sixteen 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on

a 240pin glass–epoxy printed circuit board.

The EL67I1B16 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector

sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are

possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow

the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FeaturesΚ

ΚΚ

• Power supply (Normal): VDD & VDDQ = 1.5V ± 0.075V

• 1.5V (SSTL_15 compatible) I/O

• XMP (Extreme Memory Profile) support

• Timing Reference

- DDR3 1333 CL9-9-9-24 at 1.5V

- DDR3 2000 CL9-9-9-24 at 2.05V (XMP Profile 1)

• Burst Length: 4, 8

• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

• Bi-directional, differential data strobe (DQS and /DQS)

• Differential clock input (CK, /CK) operation

• DLL aligns DQ and DQS transition with CK transition

• Addresses are mirrored for second rank

• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C

• 8-bit pre-fetch.

• On Die Termination using ODT pin

• Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm ± 1%)

• EEPROM VDDSPD=3.3V (Typical)

• PCB Height 30.00mm (1.181”), Double sided component

• Clock Cycle Time (tCK):

- DDR3-1333 tCK=1.5ns

- DDR3-2000 tCK=1.0ns

• Refresh to Active/Refresh Command Time (tRFC): 110ns

• Lead-free products are RoHS compliant

DDR3-2000X(CL9) 240-Pin XMP U-DIMM

2GB (256M x 64-bits)

Summary of content (6 pages)

PAGE 1
EL67I1B16 DDR3-2000X(CL9) 240-Pin XMP U-DIMM 2GB (256M x 64-bits) General DescriptionΚ Κ The ADATA’s EL67I1B16 is a 256Mx64 bits 2GB(2048MB) DDR3-2000(CL9) SDRAM XMP memory module, The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9-9-9-24 at 1.5V. The module is composed of sixteen 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass–epoxy printed circuit board.
PAGE 2
Pin AssignmentΚ Κ Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREFDQ 41 VSS 81 DQ32 121 VSS 161 NC,DM8 201 DQ37 2 VSS 42 NC 82 DQ33 122 DQ4 162 NC 202 VSS 3 DQ0 43 NC 83 VSS 123 DQ5 163 VSS 203 DM4 4 DQ1 44 VSS 84 /DQS4 124 VSS 164 NC,CB6 204 NC 5 VSS 45 NC,CB2 85 DQS4 125 DM0 165 NC,CB7 205 VSS 6 /DQS0 46 NC,CB3 86 VSS 126 NC 166 VSS 206 DQ38 7 DQS0 47 VSS 87 DQ34 127 VSS 167 NC 207 DQ39 8 VSS 4
PAGE 3
Pin DescriptionΚ Κ PIN NAME FUNCTION CK0~CK1, System Clock Active on the positive and negative edge to sample all inputs. /CK0~/CK1 Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at CKE0, CKE1 Clock Enable least on cycle prior new command. Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK, CKE and /S0,/S1 Chip Select L(U)DQM Row / Column address are multiplexed on the same pins.
PAGE 4
Block DiagramΚ Κ EL67I1B16_DDR3-2000X(CL=9)_2GB(128Mx8_Pb free) Rev.
PAGE 5
Absolute Maximum RatingsΚ Κ Parameter Voltage on VDD supply relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage temperature Symbol Value Unit VDD -0.4 ~ 2.15 V VDDQ -0.4 ~ 2.15 V VIN, Vout -0.4 ~ 2.
PAGE 6
Package DimensionsΚ Κ EL67I1B16_DDR3-2000X(CL=9)_2GB(128Mx8_Pb free) Rev.