Dual-Core Intel® Xeon® Processor 3000Δ Series Datasheet on 65 nm Process in the 775-land LGA Package November 2007 Document Number: 314915-002
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Contents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 11 1.1.1 Processor Terminology ............................................................................ 12 1.2 References .......................................................................................................
5.3 5.2.1 Thermal Monitor .....................................................................................80 5.2.2 Thermal Monitor 2 ..................................................................................81 5.2.3 On-Demand Mode ...................................................................................82 5.2.4 PROCHOT# Signal ..................................................................................83 5.2.5 THERMTRIP# Signal ..................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 7 8 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache.......................... 22 VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache.......................... 23 VCC Overshoot Example Waveform .......................................................................... 24 Differential Clock Waveform...................................
Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 20 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 7 8 6-1 7-1 7-2 6 Voltage Identification Definition ...............................................................................17 Market Segment Selection Truth Table for MSID[1:0]1, 2, 3, 4 .......................................18 Absolute Maximum and Minimum Ratings..................................................................
Revision History Revision Number Description Date -001 • Initial release September 2006 -002 • • • • • • • • • • Updated Features Page Updated Table 2-4, 2-15 Added Section 2.8, “PECI DC Specifications” Updated Figure 3-5, 3-6, 3-7 Updated Section 5.
Dual-Core Intel® Xeon® Processor 3000 Series Features • Available at 2.66 GHz, 2.40 GHz, 2.13 GHz, and 1.86 GHz (Dual-Core Intel® Xeon® processors 3070, 3060, 3050, and 3040 only) • Available at 3.00 GHz, 2.66 GHz, 2.40 GHz, and 2.
Introduction 1 Introduction The Dual-Core Intel® Xeon® processor 3000 series combines the performance of previous generation products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software.
Introduction 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: • Dual-Core Intel® Xeon® Processor 3085, 3075, 3070, 3065, and 3060 — Dual core processor in the FC-LGA package with a 4 MB L2 cache. • Dual-Core Intel® Xeon® Processor 3050 and 3040 — Dual core processor in the FC-LGA package with a 2 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Dual-Core Intel® Xeon® processor 3000 series.
Introduction • Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/64bitextensions/.
Introduction Document Location Notes Conroe Processor Enabled Components Drawings 1, 2, 4 Conroe Processor I/O Buffer Models 1, 2, 5 Conroe Processor Overshoot Checker 1, 2, 5 Debug Port Design Guide for Family Chipset Systems Intel® 975X, 3000, 3010, Bearlake and Bigby 1 Notes: 1. Contact your Intel representative for the latest revision and order number of this document. 2. This document may not be released as of the publication of this document. 3.
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC and AC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2-1. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VID (V) VID6 VID5 VID4 VID3 VID2 VID1 VID (V) 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.
Electrical Specifications 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 2-2 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Table 2-2.
Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
Electrical Specifications Table 2-3. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC Core voltage with respect to VSS –0.3 1.55 V - VTT FSB termination voltage with respect to VSS –0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature –40 85 °C 3, 4, 5 Notes: 1.
Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered.
Electrical Specifications Figure 2-1. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache Icc [A] 0 10 20 30 40 50 60 70 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 Vcc [V] VID - 0.063 VID - 0.075 Vcc Typical VID - 0.088 VID - 0.100 Vcc Minimum VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 Notes: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2.
Electrical Specifications Table 2-6. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache (Sheet 2 of 2) Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.40 mΩ Typical Voltage 1.53 mΩ Minimum Voltage 1.65 mΩ 65 -0.091 -0.118 -0.145 70 -0.098 -0.126 -0.154 75 -0.105 -0.133 -0.162 Notes: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2.
Electrical Specifications 2.6.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.7 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary.
Electrical Specifications Table 2-8.
Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.7.
Electrical Specifications Table 2-13. CMOS Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 VTT * 0.30 V 2, 3 3, 4, 5 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 3, 6, 5 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 2.7.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-9 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 2-15 lists the GTLREF specifications.
Electrical Specifications Table 2-16. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (266 MHz BCLK/1066 MHz FSB) Core Frequency (333 MHz BCLK/1333 MHz FSB) Notes1, 2 1/6 1.60 GHz 2.00 GHz - 1/7 1.87 GHz 2.33 GHz - 1/8 2.13 GHz 2.66 GHz - 1/9 2.40 GHz 3.00 GHz - 1/10 2.66 GHz na - 1/11 2.93 GHz na - Notes: 1. Individual processors operate only at or below the rated frequency. 2.
Electrical Specifications 2.7.8 BCLK[1:0] Specifications (CK505 based Platforms) Table 2-18. Front Side Bus Differential BCLK Specifications Symbol Parameter VL Input Low Voltage VH Input High Voltage Min Typ Max Unit Figure Notes1 -0.30 N/A N/A V 2-4 2 N/A N/A 1.15 V 2-4 2 0.300 N/A 0.550 V 2-4, 2-5 3, 4, 5 Range of Crossing Points N/A N/A 0.140 V 2-4, 2-5 4 VOS Overshoot N/A N/A 1.4 V 2-4 6 VUS Undershoot -0.
Electrical Specifications Figure 2-5. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.5 (VHavg - 700) 350 300 250 300 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 2-6. Differential Measurements Slew_rise Slew _fall +150 mV +150mV 0.0V V_swing 0.0V -150 mV -150mV Diff 2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) Table 2-19.
Electrical Specifications Notes: 1. 2. 3. 4. 5. 6. 7. 8. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. The crossing point must meet the absolute and relative crossing point specifications simultaneously. VHavg is the statistical average of the VH measured by the oscilloscope.
Electrical Specifications Table 20. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Ileak- High impedance leakage to GND N/A 10 µA 3 Cbus Bus capacitance per node N/A 10 pF 4 Vnoise Signal noise immunity above 300 MHz 0.1 * VTT — Vp-p Notes: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 2-3 for VTT specifications. 2.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 3.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • Package reference with tolerances (total height, length, width, etc.) • IHS parallelism and tilt • Land dimensions • Top-side and back-side component keep-out dimensions • Reference datums • All drawing dimensions are in mm [in].
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.1.1 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones.
Package Mechanical Specifications 3.1.5 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.1.6 Processor Materials Table 3-3 lists some of the package components and associated materials. Table 3-3. Processor Materials Component 3.
Package Mechanical Specifications Figure 3-6. Processor Top-Side Markings Example for the Dual-Core Intel® Xeon® Processor 3000 Series with 4 MB L2 Cache with 1066 MHz FSB 2.40GHZ/4M/1066/06 INTEL® XEON® 3060 SLxxx [COO] i M ©'05 [FPO] e4 ATPO S/N Figure 3-7. Processor Top-Side Markings Example for the Dual-Core Intel® Xeon® Processor 3000 Series with 4 MB L2 Cache with 1333 MHz FSB INTEL M ©'05 3065 INTEL® XEON® SLxxx [COO] 2.
Package Mechanical Specifications 3.2.1 Processor Land Coordinates Figure 3-8 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-8.
Package Mechanical Specifications 44 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 3 of 20) Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 50 Alphabetical Land Assignments (Sheet 5 of 20) Land Name Land # Signal Buffer Type FC37 AB3 FC38 FC38 Direction Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 7 of 20) Land Name Land # Signal Buffer Type VCC AC25 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 52 Alphabetical Land Assignments (Sheet 9 of 20) Land Name Land # Signal Buffer Type VCC AK11 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 11 of 20) Land Name Land # Signal Buffer Type VCC K28 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 54 Alphabetical Land Assignments (Sheet 13 of 20) Land Name Land # Signal Buffer Type VSS A2 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 15 of 20) Land Name Land # Signal Buffer Type VSS AJ10 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 56 Alphabetical Land Assignments (Sheet 17 of 20) Land Name Land # Signal Buffer Type VSS D3 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 19 of 20) Land Name Land # Signal Buffer Type VSS R28 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 3 of 20) Land # Land Name Signal Buffer Type C22 VSS C23 C24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 5 of 20) Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 7 of 20) Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 9 of 20) Land # Land Name Signal Buffer Type N8 VCC N23 N24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 11 of 20) Land # Land Name Signal Buffer Type V8 VCC V23 V24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 13 of 20) Land # Land Name Signal Buffer Type AC8 VCC AC23 AC24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 15 of 20) Land # Land Name Signal Buffer Type AF26 VSS AF27 AF28 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 17 of 20) Land # Land Name Signal Buffer Type AJ16 VSS Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 19 of 20) Land # Land Name Signal Buffer Type AM6 FC40 Power/Other AM7 VID7 Power/Other AM8 VCC Power/Other AM9 VCC Power/Other AM10 VSS AM11 Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 7) Name Type Description Input/Output A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 7) Name Type Description Input/Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. BSEL[2:0] Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 7) Name Type Description DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 7) Type Description IGNNE# Name Input IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 7) Name REQ[4:0]# RESET# Type Input/Output Input RESERVED Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 7) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 7) Name VTT VTT_OUT_LEFT Type Input Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. Output The VTT_SEL signal is used to select the correct VTT voltage level for the processor. This land is connected internally in the package to VTT. VTT_OUT_RIGHT VTT_SEL Description Miscellaneous voltage supply.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 5-2. Figure 5-1. Thermal Profile (Dual-Core Intel® Xeon® Processor 3000 Series with 4 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 44.7 24 54.8 48 64.9 2 45.5 26 55.6 50 65.7 4 46.4 28 56.5 52 66.5 6 47.2 30 57.3 54 67.4 8 48.1 32 58.1 56 68.2 10 48.9 34 59.0 58 69.1 12 49.7 36 59.8 60 69.9 14 50.6 38 60.7 62 70.7 16 51.4 40 61.5 64 71.6 18 52.
Thermal Specifications and Design Considerations Table 5-3. Figure 5-2. Thermal Profile (Dual-Core Intel® Xeon® 3070/3060 Processor with 4 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 43.2 24 49.4 48 55.7 2 43.7 26 50.0 50 56.2 4 44.2 28 50.5 52 56.7 6 44.8 30 51.0 54 57.2 8 45.3 32 51.5 56 57.8 10 45.8 34 52.0 58 58.3 12 46.3 36 52.6 60 58.8 14 46.8 38 53.1 62 59.3 16 47.4 40 53.6 64 59.8 18 47.
Thermal Specifications and Design Considerations Table 5-4. Figure 5-3. hermal Profile (Dual-Core Intel® Xeon® Processor 3000 Series with 2 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 43.2 24 49.9 48 56.6 2 43.8 26 50.5 50 57.2 4 44.3 28 51.0 52 57.8 6 44.9 30 51.6 54 58.3 8 45.4 32 52.2 56 58.9 10 46.0 34 52.7 58 59.4 12 46.6 36 53.3 60 60.0 14 47.1 38 53.8 62 60.6 16 47.7 40 54.4 64 61.1 18 48.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-4 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Dual-Core Intel® Xeon® Processor 3000 Series Thermal and Mechanical Design Guidelines.
Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.
Thermal Specifications and Design Considerations voltage transition back to the normal system operating point. Transition of the VID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-5 for an illustration of this ordering. Figure 5-5.
Thermal Specifications and Design Considerations however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
Thermal Specifications and Design Considerations the "diode" parameter and interface specifications. Two different sets of "diode" parameters are listed in Table 5-5 and Table 5-6. The Diode Model parameters (Table 5-5) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 5-6) have been added to support thermal sensors that use the transistor equation method.
Thermal Specifications and Design Considerations Table 5-6. Thermal “Diode” Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes µA 1, 2 - 3, 4, 5 Ω 3, 6 IFW Forward Bias Current 5 — 200 IE Emitter Current 5 — 200 nQ Transistor Ideality 0.997 1.001 1.005 0.391 — 0.760 2.79 4.52 6.24 Beta RT Series Resistance 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 5-5. 3.
Thermal Specifications and Design Considerations Processor PECI Topology PECI Host Controller 5.4.1.1 Land G5 30h Figure 5-6. Domain 0 Key Difference with Legacy Diode-Based Thermal Management Fan speed control solutions based on PECI uses a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative.
Thermal Specifications and Design Considerations Figure 8.
Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for socket 0 is 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.4.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the IA-32 Intel® Architecture Software Developer's Manual Volume 3: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT powerdown state, the processor will process bus snoops. 6.
Features A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop. 6.2.3.
Features 6.3 Enhanced Intel® SpeedStep® Technology The processor supports Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled. Note: Not all processors are capable of supporting Enhanced Intel SpeedStep® Technology.
Features The following are key features of Enhanced Intel SpeedStep® Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSRs (Model Specific Registers), thus eliminating chipset dependency. — If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.
Boxed Processor Specifications 7 Boxed Processor Specifications The processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-4. Space Requirements for the Boxed Processor (Overall View) Boxed Proc OverallView 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the Dual-Core Intel® Xeon® Processor 3000 Series Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 7-6 shows the location of the fan power connector relative to the processor socket.
Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C Boxed Proc PwrHeaderPlacement 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View) Figure 7-8.
Boxed Processor Specifications 7.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 7-2. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X ≤30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 35 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 104 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
