User Manual

Power Amplifier Serial I/F Spec.

11 Version 1.62

0Figure 3-2

The Power Amplifier must be able to support a SPIC cycle of between 0kHz and 800kHz. The

design of the interface should not assume that the time intervals between edges of signals during

a transfer will necessarily be regular, i.e. there may be some jitter and delay during clocking,

although all maximum and minimum timings given above will be adhered to.

Minimum time interval between SPI transfers to an individual PA is 500uS.

Whenever the SPI address does not match a device’s SPI ID, the SPIO line must go high-

impedance (<20uA output current).

3.7.1 Power Amplifier DeviceID 0 transfer protocol

DeviceID 0 is a 5 byte transfer with the following order:

Byte 1: Temperature

Byte 2: Forward Power

Byte 3: Reflected Power

Byte 4: DC Supply Voltage

Byte 5: DC Supply Current

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Power Amplifier Serial I/F Spec. 0Figure 3-2 The Power Amplifier must be able to support a SPIC cycle of between 0kHz and 800kHz. The design of the interface should not assume that the time intervals between edges of signals during a transfer will necessarily be regular, i.e. there may be some jitter and delay during clocking, although all maximum and minimum timings given above will be adhered to. Minimum time interval between SPI transfers to an individual PA is 500uS.
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Power Amplifier Serial I/F Spec. During the 5 byte transfer, A5-A0 will not normally change. If prior to the completion of the 5 byte transfer, the SPI address A5..A0 changes, for example due to a host reset or error, the transfer will be halted by the PA. The next time the device ID on the addressed PA is active, the transfer begins again starting with byte 1. The timing diagram is shown in Figure 3-3: 0Figure 3-3 3.7.2 Power Amplifier DeviceID 1 transfer protocol DeviceID 1 is a 1 byte transfer.
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Power Amplifier Serial I/F Spec. Byte 5: byte 3 Byte 6: byte 4 The timing diagram for this transfer is approximately shown in Figure 3-3, with the addition of a byte. 3.7.5.2 Write A write to DeviceID 4 is an 8 byte transfer with the following order: Byte 1: 0x06 (this is the WRITE ENABLE instruction byte for the EEPROM) Byte 2: 0x02 (this is the WRITE instruction byte for the EEPROM) Byte 3: target EEPROM page number (0-63) shifted left two bits (e.