Power Amplifier Serial I/F Spec. Power Amplifier Serial Interface Version 1.62 Requirements Specification Sonik Technologies Corporation Sonik Technologies Corporation 2310 Cousteau Court Vista, CA 92083 Ph: 760-536-1000 Fax: 760-536-1025 1 Version 1.
Power Amplifier Serial I/F Spec. Table of Contents 1. Introduction..................................................................................................................3 1.1 Version Control........................................................................................................3 1.2 Scope........................................................................................................................3 1.3 Overview............................................................
Power Amplifier Serial I/F Spec. 1. Introduction 1.1 Version Control Date Author Revision Comment 12/20/00 Welte 1.00 Initial Revision 12/21/00 Welte 1.10 Added more clarity to section 2.4 and changed Figure 2-1 to specify host as Master and size of transaction. 1/4/01 Welte 1.20 Redefined chip select, device ID mechanism. Made some changes to timing diagrams. 1/9/01 Welte 1.
Power Amplifier Serial I/F Spec. DC supply voltage DC supply current fan status internal self- test result amplifier model number 2. Power Amplifier 2.1 Status & Control The Power Amplifier has status & control information as defined in Table 2.1: 4 Version 1.
Power Amplifier Serial I/F Spec. Description No.
Power Amplifier Serial I/F Spec. Relative Offset Page Address Description 0 1 2 3 4 5 . . . . 216 . . . 247 248 249 250 251 252 253 254 255 0 940 MHz Attenuation Value 940 MHz Phase Value Unused Unused 930 MHz Attenuation Value 930 MHz Phase Value Unused Unused Unused Unused Serial Number (32 bytes starting at 0xD8) “ “ “ Serial Number Model Number Version Number Unused Unused Unused Unused Unused Checksum 1 2 0x36 0x3E 0x3F 0Table 2-2 3.
Power Amplifier Serial I/F Spec. System Devices ID (A5, A4, A3) Reserved 000 Power Amplifier #1 001 Power Amplifier #2 010 Power Amplifier #3 011 Power Amplifier #4 100 Power Supply #1 101 Power Supply #2 110 Reserved 111 0Table 3-1 3.2 Serial Communication Description The Power Amplifier and host will communicate synchronously via a Serial Peripheral Interface (SPI) Bus with the master located on the host and the Power Amplifier functioning as one of up to 8 slave devices. 3.
Power Amplifier Serial I/F Spec. 0Table 3-2 Note: Pins 11 and 12 will indicate to the amplifier its slot location in the rack. Pin 11 Ground Ground Open Open Pin 12 Ground Open Ground Open Amplifier 1 2 3 4 Pins 13, 14, and 15 should be left open in the Sonik rack. These pins will be used by the manufacturer for test purposes. SPI bits A5-A3 are used to select the Power Amplifier module on the SPI BUS. SPI bits A2-A0 are used to select the register/device within the selected Power Amplifier module. 3.
Power Amplifier Serial I/F Spec. Fan Fail Flag Clear Amp Online Amplifier Reset Flag Clear Reverse Power Shutdown Flag Clear 6 Reserved 7 Factory Communication Amplifier Overdrive Alarm Flag Clear Thermal Alarm Flag Clear Amplifier Overdrive Shutdown Flag Clear Thermal Shutdown Flag Clear 0Table 3-3 3.5 SPI Electrical Considerations All signals are CMOS levels with 30%/70% thresholds.
Power Amplifier Serial I/F Spec. Figure 3-1 Note that the Host is the Master Device and therefore is the only device on the SPI bus to drive the CLK signal. The host changes its MOSI output on the falling edge of the SPI clock while the SPISB (chip selected) is driven active low. The Power Amplifier is expected to sample data (SPII) on the rising edge of the clock signal. The host samples the MISO input on the rising edge of the SPI clock while the SPISB (chip selected) is driven active low.
Power Amplifier Serial I/F Spec. 0Figure 3-2 The Power Amplifier must be able to support a SPIC cycle of between 0kHz and 800kHz. The design of the interface should not assume that the time intervals between edges of signals during a transfer will necessarily be regular, i.e. there may be some jitter and delay during clocking, although all maximum and minimum timings given above will be adhered to. Minimum time interval between SPI transfers to an individual PA is 500uS.
Power Amplifier Serial I/F Spec. During the 5 byte transfer, A5-A0 will not normally change. If prior to the completion of the 5 byte transfer, the SPI address A5..A0 changes, for example due to a host reset or error, the transfer will be halted by the PA. The next time the device ID on the addressed PA is active, the transfer begins again starting with byte 1. The timing diagram is shown in Figure 3-3: 0Figure 3-3 3.7.2 Power Amplifier DeviceID 1 transfer protocol DeviceID 1 is a 1 byte transfer.
Power Amplifier Serial I/F Spec. Byte 5: byte 3 Byte 6: byte 4 The timing diagram for this transfer is approximately shown in Figure 3-3, with the addition of a byte. 3.7.5.2 Write A write to DeviceID 4 is an 8 byte transfer with the following order: Byte 1: 0x06 (this is the WRITE ENABLE instruction byte for the EEPROM) Byte 2: 0x02 (this is the WRITE instruction byte for the EEPROM) Byte 3: target EEPROM page number (0-63) shifted left two bits (e.
