Video and Image Processing Suite User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-VIPSUITE-12.
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Contents Chapter 1. About This MegaCore Function Suite Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv Contents Use of Control Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Structure of a Control Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 User-Defined and Altera-Reserved Packets . . . . .
Contents v Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Packet Visualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi Contents Chapter 11. Clocked Video Output MegaCore Function Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1 Video Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents vii Using the Control Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1 Avalon-ST Video Protocol Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3 Stall Behavior and Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Error Recovery . . . . . . . . . . . . . . . . . . . . . . .
viii Contents Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1 Locked Frame Rate Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–2 Interlaced Video Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents ix Chapter 22. Scaler II MegaCore Function Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22–1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22–1 Edge-Adaptive Scaling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x Contents tb_test.sv—Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tb_test.sv—Section 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Field Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constrained Random Test . . . . . . . . . . . . . . . . . .
1. About This MegaCore Function Suite This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores in a wide variety of image processing and display applications.
1–2 Chapter 1: About This MegaCore Function Suite Release Information Release Information Table 1–1 provides information about this release of the Altera Video and Image Processing Suite MegaCore functions. Table 1–1. Video and Image Processing Suite Release Information Item Description Version 12.
Chapter 1: About This MegaCore Function Suite Features 1–3 Table 1–3. Device Family Support (Part 2 of 2) Device Family Arria V Support Refer to the What’s New in Altera IP page of the Altera website. Cyclone® II Final Cyclone III Final Cyclone III LS Final Cyclone IV E Final Cyclone IV GX Final Cyclone V Refer to the What’s New in Altera IP page of the Altera website.
1–4 Chapter 1: About This MegaCore Function Suite Design Example During control packet processing, the MegaCore functions might stall frequently and read/write less than once per clock cycle. During data processing, the MegaCore functions generally process one input/output per clock cycle. There are, however, some stalling cycles. Typically, these are for internal calculations between rows of image data and between frames/fields.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–5 Performance and Resource Utilization This section shows typical expected performance for the Video and Image Processing Suite MegaCore functions with the Quartus® II software targeting Cyclone IV GX and Stratix V devices. 1 Cyclone IV GX devices use combinational look-up tables (LUTs) and logic registers; Stratix V devices use combinational adaptive look-up tables (ALUTs) and logic registers.
1–6 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Table 1–5. 2D Median Filter Performance (Part 2 of 2) Device Family Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 984 1,154 3,072 — 2 — — 364.7 V (2) Median filtering 352×288 pixel two color frames using a 5×5 kernel of pixels. Cyclone IV GX (1) 5,402 5,667 28,160 8 — — — 235.07 Stratix V (2) 2,698 3,832 28,160 — 4 — — 274.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–7 Avalon-ST Video Monitor Table 1–7 lists the performance figures for the Avalon-ST Video Monitor. Table 1–7. Avalon-ST Video Monitor Performance Device Family Cyclone IV Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 885 870 5,856 11 — — — 237.87 468 880 5,536 — 9 — — 363.50 GX (1) V (2) Notes to Table 1–7: (1) EP4CGX15BF14C6 devices.
1–8 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Clipper Table 1–9 lists the performance figures for the Clipper. Table 1–9. Clipper Performance Device Family Combinational LUTs/ALUTs Logic Registers Memory Bits M9K DSP Blocks M20K (9x9) (18x18) fMAX (MHz) A 1080p60-compatible clipper with a clipping window that has fixed offsets from the size of the input frames. Cyclone IV GX (1) Stratix V (2) 596 664 — 0 — — — 191.28 452 453 — — 0 — — 313.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–9 Table 1–10. Clocked Video Input Performance (Part 2 of 2) Device Family Stratix Memory Combinational LUTs/ALUTs Logic Registers Bits M9K M20K MLAB Bits fMAX (MHz) 310 426 43,008 — 3 40 198.61 V (2) Notes to Table 1–10: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices. Clocked Video Output Table 1–11 lists the performance figures for the Clocked Video Output. Table 1–11.
1–10 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Table 1–12. Color Plane Sequencer Performance (Part 2 of 2) Device Family Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 272 313 — — 0 — — 385.21 V (2) Splitting a 4:2:2 stream from 2 channels in parallel to a single channel luminance output stream and a channels in sequence horizontally half-subsampled chrominance output stream. 8 bit data.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–11 Control Synchronizer Table 1–14 lists the performance figures for the Control Synchronizer. Table 1–14.
1–12 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Table 1–15. Deinterlacer Performance (Part 2 of 2) Device Family Cyclone IV Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 2,790 3,313 2,566 14 — — — 176.03 2,144 2,299 2,566 — 14 — — 283.61 GX (1) V (2) Notes to Table 1–15: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–13 Table 1–17. Frame Buffer Performance (Part 2 of 2) Device Family Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 1,285 3,291 11,168 — 4 — — 301.11 V (2) Triple-buffering 720×576 8-bit RGB with sequential data interface and run-time control interface. Cyclone IV GX (1) 1,286 1,684 8,192 5 — — — 179.
1–14 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Table 1–19. Interlacer Performance (Part 2 of 2) Device Family Stratix Memory DSP Blocks Combinational LUTs/ALUTs Logic Registers Bits M9K M20K (9×9) (18×18) fMAX (MHz) 310 428 — — 0 — — 368.46 V (2) Interlacing 720p 10-bit video, 2 channels over a sequential interface. Cyclone IV GX (1) 431 501 — 0 — — — 246.67 Stratix V (2) 280 347 — — 0 — — 330.
Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization 1–15 Scaler II Table 1–21 lists the performance figures for the Scaler II. Table 1–21. Scaler II Performance Device Family Combinational LUTs/ALUTs Logic Registers Memory Bits M9K DSP Blocks M20K (9×9) (18×18) fMAX (MHz) Scaling 640×480, 8-bit, three color data up to 1,024×768 with linear interpolation.
1–16 Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization Test Pattern Generator Table 1–23 lists the performance figures for the Test Pattern Generator. Table 1–23. Test Pattern Generator Performance Combinational LUTs/ALUTs Device Family Logic Registers Memory Bits M9K DSP Blocks M20K (9×9) (18×18) fMAX (MHz) Producing a 400×x200, 8-bit 4:2:0 Y'Cb'Cr' stream with a parallel data interface. Cyclone IV GX (1) 159 168 192 2 — — — 315.
2. Getting Started with Altera IP Cores This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications.
2–2 Chapter 2: Getting Started with Altera IP Cores Design Flows Design Flows You can use the following flow(s) to parameterize Altera IP cores: ■ MegaWizard Plug-In Manager Flow Figure 2–2.
Chapter 2: Getting Started with Altera IP Cores MegaWizard Plug-In Manager Flow 2–3 1. Create a Quartus II project using the New Project Wizard available from the File menu. 2. In the Quartus II software, launch the MegaWizard Plug-in Manager from the Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation. 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4.
2–4 Chapter 2: Getting Started with Altera IP Cores Generated Files 1 The Finish button may be unavailable until all parameterization errors listed in the messages window are corrected. 8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. You can now integrate your custom IP core instance in your design, simulate, and compile.
Chapter 2: Getting Started with Altera IP Cores Generated Files 1 2–5 For a description of the signals that the MegaCore function variation supports, refer to the “Signals” section of the respective MegaCore Function chapter in this user guide. Table 2–1. Generated Files File Name (1) Description .bsf Quartus II block symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. .
2–6 Video and Image Processing Suite User Guide Chapter 2: Getting Started with Altera IP Cores Generated Files January 2013 Altera Corporation
3. Interfaces Interface Types The MegaCore functions in the Video and Image Processing Suite use standard interfaces for data input and output, control input, and access to external memory. These standard interfaces ensure that video systems can be quickly and easily assembled by connecting MegaCore functions together. The functions use the following types of interfaces: ■ Avalon-ST interface—a streaming interface that supports backpressure.
3–2 Chapter 3: Interfaces Avalon-ST Video Protocol 1 For information about the supported clocked video interfaces, refer to the “Functional Description” sections of “Clocked Video Input MegaCore Function” on page 10–1 and “Clocked Video Output MegaCore Function” on page 11–1. Avalon-ST Video Protocol The MegaCore functions in the Video and Image Processing Suite use the Avalon-ST Video protocol.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–3 Table 3–1 lists the packet types and Figure 3–2 shows the structure of a packet. Table 3–1. Avalon-ST Video Packet Types Type Identifier Description 0 Video data packet 1–8 User packet types 9–12 Reserved for future Altera use 13 Ancillary data packet 14 Reserved for future Altera use 15 Control data packet Figure 3–2.
3–4 Chapter 3: Interfaces Avalon-ST Video Protocol Static Parameters of Video Data Packets The following two static parameters specify the Avalon-ST interface that video systems use: Bits Per Pixel Per Color Plane The maximum number of bits that represent each color plane value within each pixel. For example R’G’B’ data of eight bits per sample (24 bits per pixel) would use eight bits per pixel per color plane.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–5 A color pattern can represent more than one pixel. This is the case when consecutive pixels contain samples from different color planes—There must always be at least one common color plane between all pixels in the same color pattern. Color patterns representing more than one pixel are identifiable by a repeated color plane name. The number of times a color plane name is repeated is the number of pixels represented.
3–6 Chapter 3: Interfaces Avalon-ST Video Protocol Table 3–3 lists the recommended color patterns for common combinations of color spaces and color planes in parallel and sequence. Table 3–3.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–7 Structure of Video Data Packets Figure 3–6 shows the structure of a video data packet using a set parallel color pattern and bits per pixel per color plane. Figure 3–6.
3–8 Chapter 3: Interfaces Avalon-ST Video Protocol When a video data packet uses a subsampled color pattern, the individual color planes of the video data packet have different dimensions. For example, 4:2:2 has one full width, full height plane and two half width, full height planes. For 4:2:0 there are one full width, full height plane and two half width, half height planes.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–9 Table 3–4. Examples of Control Data Packet Parameters Parameters Type Width Height Description Interlacing 15 1920 540 1011 The fields that follow are 1920 pixels wide and 540 pixels high. The next field is F0 (even lines) and you must handle the stream as genuine interlaced video material where the fields are all temporally disjoint. 15 1920 540 1010 The fields that follow are 1920 pixels wide and 540 pixels high.
3–10 Chapter 3: Interfaces Avalon-ST Video Protocol Figure 3–8 to Figure 3–10 show examples of control data packets, and how they are split into symbols. Figure 3–8. Three Symbols in Parallel Control data, reference numbers to Table 4-5 Start End X 3 6 9 Symbols in most significant bits X 2 5 8 Symbols in middle significant bits 15 1 4 7 Symbols in least significant bits Control data packet type identifier (4 bits in least significant symbol, X’s for unused symbols) Figure 3–9.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–11 MegaCore functions are not required to understand or process ancillary data packets, but must forward them on, as is done with user-defined and Altera-reserved packets. Figure 3–11 shows an example of an Avalon-ST Video Ancillary Data Packet containing two ancillary packets. Figure 3–11.
3–12 Chapter 3: Interfaces Avalon-ST Video Protocol ■ MegaCore functions that can change the color pattern of a video data packets may also pad non-video data packets with extra data. When defining a packet type where the length is variable and meaningful, it is recommended to send the length at the start of the packet. Transmission of Avalon-ST Video Over Avalon-ST Interfaces Avalon-ST Video is a protocol transmitted over Avalon-ST interfaces.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–13 In this case, both the input and output video data packets have a parallel color pattern and eight bits per pixel per color plane as listed in Table 3–8. Table 3–8. Parameters for Example of Data Transferred in Parallel Parameter Value Bits per Pixel per Color Plane 8 R Color Pattern G B Figure 3–12 shows how the first few pixels of a frame are processed. Figure 3–12. Timing Diagram Showing R’G’B’ Transferred in Parallel 1. 2. 3. 4. 5. 6. n.
3–14 Chapter 3: Interfaces Avalon-ST Video Protocol There are five signals types (ready, valid, data, startofpacket, and endofpacket) associated with each port. The din_ready signal is an output from the MegaCore function and indicates when the input port is ready to receive data. The din_valid and din_data signals are both inputs. The source connected to the input port sets din_valid to logic '1' when din_data has useful information that must be sampled.
Chapter 3: Interfaces Avalon-ST Video Protocol 3–15 Example 2 (Data Transferred in Sequence) This example shows how a number of pixels from the middle of a frame could be processed by another MegaCore function. This time handling a color pattern that has planes B'G'R' in sequence. This example does not show the start of packet and end of packet signals because these are always low during the middle of a packet. The bits per pixel per color plane and color pattern are listed in Table 3–9. Table 3–9.
3–16 Chapter 3: Interfaces Avalon-ST Video Protocol 5. The MegaCore function sets dout_valid to logic '0' and stops putting data on the dout_data port because the sink is not ready for data. The MegaCore function also sets din_ready to logic '0' because there is no way to output data and the MegaCore function must stop the source from sending more data before it uses all internal buffer space.
Chapter 3: Interfaces Avalon-MM Slave Interfaces 3–17 Avalon-MM Slave Interfaces The Video and Image Processing Suite MegaCore functions that permit run-time control of some aspects of their behavior, use a common type of Avalon-MM slave interface for this purpose. Each slave interface provides access to a set of control registers which must be set by external hardware. You must assume that these registers power up in an undefined state.
3–18 Chapter 3: Interfaces Avalon-MM Slave Interfaces Most Video and Image Processing Suite MegaCore functions with a slave interface read and propagate non-image data packets from the input stream until the image data header (0) of an image data packet has been received. The status bit is then set to 0 and the MegaCore function waits until the Go bit is set to 1 if it is not already.
Chapter 3: Interfaces Avalon-MM Slave Interfaces 3–19 Specification of the Type of Avalon-MM Slave Interfaces The Avalon Interface Specifications define many signal types, many of which are optional. Table 3–10 lists the signals that the Avalon-MM slave interfaces use in the Video and Image Processing Suite. Table 3–10 does not list unused signals. Table 3–10.
3–20 Chapter 3: Interfaces Avalon-MM Master Interfaces Avalon-MM Master Interfaces The Video and Image Processing Suite MegaCore functions use a common type of Avalon-MM master interface for access to external memory. Connect these master interfaces to external memory resources through arbitration logic such as that provided by the system interconnect fabric. Specification of the Type of Avalon-MM Master Interfaces The Avalon Interface Specifications define many signal types, many of which are optional.
Chapter 3: Interfaces Buffering of Non-Image Data Packets in Memory 3–21 Buffering of Non-Image Data Packets in Memory The Frame Buffer and the Deinterlacer (when buffering is enabled) route the video stream through an external memory. Non-image data packets must be buffered and delayed along with the frame or field they relate to and extra memory space has to be allocated. You must specify the maximum number of packets per field and the maximum size of each packet to cover this requirement.
3–22 Video and Image Processing Suite User Guide Chapter 3: Interfaces Buffering of Non-Image Data Packets in Memory January 2013 Altera Corporation
4. 2D FIR Filter MegaCore Function Core Overview The 2D FIR Filter MegaCore function performs 2D convolution using matrices of 3×3, 5×5, or 7×7 coefficients. The 2D FIR Filter retains full precision throughout the calculation while making efficient use of FPGA resources. With suitable coefficients, the 2D FIR Filter can perform operations such as sharpening, smoothing, and edge detection. You can configure the 2D FIR Filter to change coefficient values at run time with an Avalon-MM slave interface.
4–2 Chapter 4: 2D FIR Filter MegaCore Function Functional Description The conversion is performed in four stages, in the following order: 1. Result Scaling. You can choose to scale up the results, increasing their range. This is useful to quickly increase the color depth of the output. The available options are a shift of the binary point right –16 to +16 places. This is implemented as a simple shift operation so it does not require multipliers. 2. Removal of Fractional Bits.
Chapter 4: 2D FIR Filter MegaCore Function Functional Description 4–3 Error Recovery The 2D FIR Filter MegaCore function resolution is not configurable at run time. This MegaCore function does not read the control packets passed through it. An error condition occurs if an endofpacket signal is received too early or too late for the compile time configured frame size. In either case, the 2D FIR Filter always creates output video packets of the configured size.
4–4 Chapter 4: 2D FIR Filter MegaCore Function Parameter Settings Parameter Settings Table 4–3 and Table 4–4 list the 2D FIR Filter MegaCore function parameters. Table 4–3. 2D FIR Filter Parameter Settings Tab, General Page Parameter Value Description Maximum image width 32–2600, Default = 640 Choose the maximum image width in pixels. Number of color planes in sequence 1–3 The number of color planes that are sent in sequence over one data connection.
Chapter 4: 2D FIR Filter MegaCore Function Signals 4–5 Table 4–4. 2D FIR Filter Parameter Settings Tab, Coefficients Page Parameter Value Description Filter size (1) 3x3, 5x5, 7x7 Choose the size in pixels of the convolution kernel used in the filtering. Run-time controlled On or Off Turn on to enable run-time control of the coefficient values.
4–6 Chapter 4: 2D FIR Filter MegaCore Function Control Register Map Table 4–5. 2D FIR Filter Signals (Part 2 of 2) Signal Direction Description din_ready Out din port Avalon-ST ready signal. This signal indicates when the MegaCore function is ready to receive data. din_startofpacket In din port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. din_valid In din port Avalon-ST valid signal. This signal identifies the cycles when the port must input data.
5. 2D Median Filter MegaCore Function Core Overview The 2D Median Filter MegaCore function applies 3×3 or 5×5 pixel median filters to video images. Median filtering removes speckle noise and salt-and-pepper noise while preserving the sharpness of edges in video images. Functional Description The 2D Median Filter MegaCore function provides a means to perform 2D median filtering operations using matrices of 3×3 or 5×5 kernels.
5–2 Chapter 5: 2D Median Filter MegaCore Function Parameter Settings Error Recovery The 2D Median Filter MegaCore function resolution is not configurable at run time. This MegaCore function does not read the control packets passed through it. An error condition occurs if an endofpacket signal is received too early or too late for the compile-time-configured frame size. In either case, the 2D FIR Filter always creates output video packets of the configured size.
Chapter 5: 2D Median Filter MegaCore Function Signals 5–3 Table 5–3. 2D Median Filter Filter Parameter Settings (Part 2 of 2) Parameter Bits per pixel per color plane Value 4–20, Default = 8 Description Choose the number of bits per pixel (per color plane). Number of color 1–3 planes in sequence The number of color planes that are sent in sequence over one data connection. For example, a value of 3 for R'G'B' R'G'B' R'G'B'. Filter size Choose the size of kernel in pixels to take the median from.
5–4 Video and Image Processing Suite User Guide Chapter 5: 2D Median Filter MegaCore Function Signals January 2013 Altera Corporation
6. Alpha Blending MegaCore Function Core Overview The Alpha Blending Mixer MegaCore function mixes together up to 12 image layers. The Alpha Blending Mixer supports both picture-in-picture mixing and image blending. Each foreground layer can be independently activated and moved at run time using an Avalon-MM slave interface. Functional Description The Alpha Blending Mixer MegaCore function provides an efficient means to mix together up to 12 image layers.
6–2 Chapter 6: Alpha Blending MegaCore Function Functional Description This behavior is illustrated by the following pseudo-code: go = 0; while (true) { status = 0; read_non_image_data_packet_from background_layer(); read_control_first_pass(); // Check layer status (disable/displayed/consumed) for_each_layer layer_id { // process non-image data packets for displayed or consumed layers if (layer_id is not disabled) { handle_non_image_packet_from_foreground_layer(layer_id); } } while (go != 1) wait; status
Chapter 6: Alpha Blending MegaCore Function Functional Description 6–3 The value of an output pixel ON, where N is the maximum number of layers, is deduced from the following recursive formula: ON = (1 – aN)pN + aNON – 1 O 0 = p0 where pN is the input pixel for layer N and aN is the alpha pixel for layer N. Consumed and disabled layers are skipped.
6–4 Chapter 6: Alpha Blending MegaCore Function Functional Description During the mixing of a frame, the Alpha Blending Mixer reads from the background input for each non-stalled cycle. The Alpha Blending Mixer also reads from the input ports associated with layers that currently cover the background image. Because of pipelining, the foreground pixel of layer N is read approximately N active cycles after the corresponding background pixel has been read.
Chapter 6: Alpha Blending MegaCore Function Parameter Settings 6–5 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 6–2. Alpha Blending Mixer Latency Mode Latency O (cycles) (1) All modes Note to Table 6–2: (1) O refers to a small number of clock cycles, and is not of zero value.
6–6 Chapter 6: Alpha Blending MegaCore Function Signals Signals Table 6–4 lists the input and output signals for the Alpha Blending Mixer MegaCore function. Table 6–4. Alpha Blending Mixer Signals (Part 1 of 2) Signal Direction Description clock In The main system clock. The MegaCore function operates on the rising edge of the clock signal. reset In The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal.
Chapter 6: Alpha Blending MegaCore Function Control Register Maps 6–7 Table 6–4. Alpha Blending Mixer Signals (Part 2 of 2) Signal Direction Description dout_startofpacket Out dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. dout_valid Out dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data. Note to Table 6–4: (1) These ports are present only if you turn on Alpha blending.
6–8 Video and Image Processing Suite User Guide Chapter 6: Alpha Blending MegaCore Function Control Register Maps January 2013 Altera Corporation
7. Avalon-ST Video Monitor MegaCore Function Core Overview The Avalon-ST Video Monitor MegaCore function is a debugging and monitoring component. The monitor together with the associated software in the System Console allows you to capture and visualize the flow of video data in a system. You can inspect the video data flow at multiple levels of abstraction from the Avalon-ST video protocol level down to raw packet data level.
7–2 Chapter 7: Avalon-ST Video Monitor MegaCore Function Functional Description 1 The System Console uses the sopcinfo file written by Qsys to discover the connections between the trace system and the monitors. If you instantiate and manually connect the trace system and the monitors using HDL, the System Console will not detect them. f For more information on the Trace System, refer to Chapter 25, Trace System MegaCore Function.
Chapter 7: Avalon-ST Video Monitor MegaCore Function Parameter Settings 7–3 Table 7–1. Statistics Statistic Backpressure Description [(Not ready and valid cycles + Inter packet valid cycles) / (Data transfer cycles + Not ready and valid cycles + Ready and not valid cycles + Not ready and not valid cycles + Inter packet valid cycles)] × 100 Inter packet ready cycles are not included in the packet duration. A packet begins when a source is ready to send data.
7–4 Chapter 7: Avalon-ST Video Monitor MegaCore Function Signals Signals Table 7–3 lists the input and output signals for the Avalon-ST Video Monitor MegaCore function. Table 7–3. Avalon-ST Video Monitor Signals (Part 1 of 2) Signal Direction Description All signals on the monitor are synchronous to this clock. Drive this signal from the clock which drives the video components that are being monitored. clock_clk In reset_reset In This signal only resets the debugging parts of the monitor.
Chapter 7: Avalon-ST Video Monitor MegaCore Function Control Register Map 7–5 Table 7–3. Avalon-ST Video Monitor Signals (Part 2 of 2) Signal Direction Description control_writedata In control slave port Avalon-MM writedata bus. control_waitrequest Out control slave port Avalon-MM waitrequest signal. Control Register Map Table 7–4 describes the Avalon-ST Video Monitor MegaCore function control register map. Table 7–4.
7–6 Video and Image Processing Suite User Guide Chapter 7: Avalon-ST Video Monitor MegaCore Function Control Register Map January 2013 Altera Corporation
8. Chroma Resampler MegaCore Function Chroma Resampler The Chroma Resampler MegaCore function resamples video data to and from common sampling formats. The human eye is more sensitive to brightness than tone. Taking advantage of this characteristic, video transmitted in the Y’CbCr color space often subsamples the color components (Cb and Cr) to save on data bandwidth.
8–2 Chapter 8: Chroma Resampler MegaCore Function Functional Description The Chroma Resampler MegaCore Function only supports the cosited form of horizontal resampling—the form for 4:2:2 data in ITU Recommendation BT.601, MPEG2, and other standards. f For more information about the ITU standard, refer to Recommendation ITU-R BT.601, Encoding Parameters of Digital Television for Studios, 1992, International Telecommunications Union, Geneva.
Chapter 8: Chroma Resampler MegaCore Function Functional Description 8–3 Figure 8–2 shows 4:2:2 data at an edge transition. Without taking any account of the luma, the interpolation to produce chroma values for sample 4 would weight samples 3 and 5 equally. From the luma, you can see that sample 4 falls on an the low side of an edge, so sample 5 is more significant than sample 3. The luma-adaptive mode looks for such situations and chooses how to adjust the interpolation filter.
8–4 Chapter 8: Chroma Resampler MegaCore Function Functional Description 1 All input data samples must be in unsigned format. If the number of bits per pixel per color plane is N, this means that each sample consists of N bits of data which are interpreted as an unsigned binary number in the range [0, 2N – 1]. All output data samples are also in the same unsigned format. 1 For more information about how non-video packets are transferred, refer to “Packet Propagation” on page 3–11.
Chapter 8: Chroma Resampler MegaCore Function Parameter Settings 8–5 Error Recovery On receiving an early endofpacket signal, the Chroma Resampler stalls its input but continues writing data until it has sent an entire frame. If it does not receive an endofpacket signal at the end of a frame, the Chroma Resampler discards data until the end-of-packet is found. 1 For more information about the stall behavior and error recovery, refer to “Stall Behavior and Error Recovery” on page 1–3.
8–6 Chapter 8: Chroma Resampler MegaCore Function Signals Table 8–3. Chroma Resampler Parameter Settings (Part 2 of 2) Parameter Value Description Color plane configuration Sequence, Parallel There must always be three color planes for this function but you can choose whether the three color planes are transmitted in sequence or in parallel. Input Format (1) 4:4:4, 4:2:2, 4:2:0 Choose the format/sampling rate format for the input frames. Note that the input and output formats must be different.
9. Clipper MegaCore Function Core Overview The Clipper MegaCore function clips video streams. You can configure the Clipper at compile time or optionally at run time using an Avalon-MM slave interface. Functional Description The Clipper MegaCore function provides a means to select an active area from a video stream and discard the remainder.
9–2 Chapter 9: Clipper MegaCore Function Parameter Settings Error Recovery On receiving an early endofpacket signal, the Clipper stalls its input but continues writing data until it has sent an entire frame. If it does not receive an endofpacket signal at the end of a frame, the Clipper discards data until the end-of-packet is found. 1 For more information about the stall behavior and error recovery, refer to “Stall Behavior and Error Recovery” on page 1–3.
Chapter 9: Clipper MegaCore Function Signals 9–3 Table 9–3. Clipper Parameter Settings (Part 2 of 2) Parameter Number of color planes in parallel Value Description 1–3 Choose the number of color planes in parallel. Include Avalon-MM On or Off interface Turn on if you want to specify clipping offsets using the Avalon-MM interface. Clipping method Offsets, Rectangle Choose whether to specify the clipping area as offsets from the edge of the input area or as a fixed rectangle.
9–4 Chapter 9: Clipper MegaCore Function Control Register Maps Table 9–4. Clipper Signals (Part 2 of 2) Signal Direction Description din_ready Out din port Avalon-ST ready signal. This signal indicates when the MegaCore function is ready to receive data. din_startofpacket In din port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. din_valid In din port Avalon-ST valid signal. This signal identifies the cycles when the port must input data.
10. Clocked Video Input MegaCore Function Core Overview The Clocked Video Input MegaCore function converts clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video. You can configure the Clocked Video Input at run time using an Avalon-MM slave interface. Functional Description The Clocked Video Input converts clocked video to the flow controlled Avalon-ST Video protocol.
10–2 Chapter 10: Clocked Video Input MegaCore Function Functional Description The Clocked Video Input MegaCore function supports both 8 and 10-bit TRS and XYZ words. When in 10-bit mode the bottom 2 bits of the TRS and XYZ words are ignored to allow easy transition from an 8-bit system. The XYZ word contains the synchronization information and the relevant bits of it's format are listed in Table 10–1. Table 10–1.
Chapter 10: Clocked Video Input MegaCore Function Functional Description 10–3 Table 10–2 lists the signals and Figure 10–3 shows the timing. Table 10–2. Clocked Video Input Signals for Separate Synchronization Format Video Signal Name Description vid_datavalid When asserted the video is in an active picture period (not horizontal or vertical blanking). vid_h_sync When 1, the video is in a horizontal synchronization period. vid_v_sync When 1, the video is in a vertical synchronization period.
10–4 Chapter 10: Clocked Video Input MegaCore Function Functional Description 2. Read Status register bit 0. When this is a 1, the MegaCore function outputs data. This occurs on the next start of frame or field that matches the setting of the Field order in the parameter editor. The sequence for stopping the output of the MegaCore function is as follows: 1. Write a 0 to Control register bit 0. 2. Read Status register bit 0. When this is a 0, the MegaCore function has stopped data output.
Chapter 10: Clocked Video Input MegaCore Function Functional Description 10–5 If the MegaCore function has not yet determined the format of the incoming video, it uses the values specified under the Avalon-ST Video Initial/Default Control Packet section in the parameter editor. After determining an aspect of the incoming videos format, the MegaCore function enters the value in the respective register, sets the registers valid bit in the Status register, and triggers the respective interrupts.
10–6 Chapter 10: Clocked Video Input MegaCore Function Functional Description The Clocked Video Input MegaCore function provides some functions to facilitate Genlock. The MegaCore function can be configured to output, via the refclk_div signal, a divided down version of its vid_clk (refclk) aligned to the start of frame (SOF).
Chapter 10: Clocked Video Input MegaCore Function Functional Description 10–7 A Clocked Video Output MegaCore function can take in the locked PLL clock and the SOF signal and align the output video to these signals. This produces an output video frame that is synchronized to the incoming video frame. For more information, refer to “Clocked Video Output MegaCore Function” on page 11–1.
10–8 Chapter 10: Clocked Video Input MegaCore Function Functional Description f Refer to the SMPTE 2016-1-2007 standard for a more detailed description of the AFD codes. Table 10–6 lists the AFD Extractor register map. Table 10–6. AFD Extractor Register Map Address Register Description When bit 0 is 0, the core discards all packets. 0 Control 1 When bit 0 is 1, the core passes through all nonancillary packets. Reserved.
Chapter 10: Clocked Video Input MegaCore Function Parameter Settings 10–9 Latency Table 10–7 lists the approximate latency from the video data input to the video data output for typical usage modes of the Clocked Video Input MegaCore function. You can use this table to predict the approximate latency between the input and the output of your video processing pipeline.
10–10 Chapter 10: Clocked Video Input MegaCore Function Signals Table 10–8. Clocked Video Input Parameter Settings (Part 2 of 2) Parameter Value Description Interlaced or progressive Progressive, Interlaced Choose the format to be used when no format can be automatically detected. Width 32–65,536, Default = 1920 Choose the image width to be used when no format can be automatically detected.
Chapter 10: Clocked Video Input MegaCore Function Signals 10–11 Table 10–9. Clocked Video Input Signals (Part 2 of 3) Signal Direction Description av_writedata In control slave port Avalon-MM write data bus. These input lines are used for write transfers. (1) is_clk In Clock signal for Avalon-ST ports dout and control. The MegaCore function operates on the rising edge of the is_clk signal. is_data Out dout port Avalon-ST data bus.
10–12 Chapter 10: Clocked Video Input MegaCore Function Control Register Maps Table 10–9. Clocked Video Input Signals (Part 3 of 3) Signal Direction In vid_v_sync Description (Separate Synchronization Mode Only.) Clocked video vertical synchronization signal. Assert this signal during the vertical synchronization period of the video stream. Note to Table 10–9: (1) These ports are present only if you turn on Use control port.
Chapter 10: Clocked Video Input MegaCore Function Control Register Maps 10–13 Table 10–10. Clocked Video Input Control Register Map (Part 2 of 2) Address Register Description Bits 2 and 1 are the interrupt status bits: 2 Interrupt ■ When bit 1 is asserted, the status update interrupt has triggered. ■ When bit 2 is asserted, the stable video interrupt has triggered. ■ The interrupts stay asserted until a write of 1 is performed to these bits.
10–14 Video and Image Processing Suite User Guide Chapter 10: Clocked Video Input MegaCore Function Control Register Maps January 2013 Altera Corporation
11. Clocked Video Output MegaCore Function Core Overview The Clocked Video Output MegaCore function converts Avalon-ST Video to clocked video formats (such as BT656, BT1120, and DVI). You can configure the Clocked Video Output at run time using an Avalon-MM slave interface.
11–2 Chapter 11: Clocked Video Output MegaCore Function Functional Description The format of the video frame is shown in Figure 11–1 for progressive and Figure 11–2 for interlaced. Figure 11–1.
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–3 Figure 11–2.
11–4 Chapter 11: Clocked Video Output MegaCore Function Functional Description The Clocked Video Input MegaCore function extracts any ancillary packets from the Y channel during the vertical blanking. Ancillary packets are not extracted from the horizontal blanking. The extracted packets are output via the Clocked Video Input’s Avalon-ST output with a packet type of 13 (0xD).
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–5 The MegaCore function can be configured to support between 1 to 14 different modes and each mode has a bank of registers that describe the output frame. When the MegaCore function receives a new control packet on the Avalon-ST Video input, it searches the mode registers for a mode that is valid and has a field width and height that matches the width and height in the control packet.
11–6 Chapter 11: Clocked Video Output MegaCore Function Functional Description Table 11–2 lists how Figure 11–3 relates to the register map. Table 11–2. Progressive Frame Parameter Descriptions Register Name Parameter Description The zeroth bit of this register is the Interlaced bit: ModeN Control ■ Set to 0 for progressive. Bit 1 of this register is the sequential output control bit (only if the Allow output of color planes in sequence compiletime parameter is enabled).
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–7 Figure 11–4 shows how the register values map to the interlaced frame format described in “Video Formats” on page 11–1. Figure 11–4.
11–8 Chapter 11: Clocked Video Output MegaCore Function Functional Description Table 11–3 lists how Figure 11–4 relates to the register map. Table 11–3. Interlaced Frame Parameter Descriptions Register Name Parameter Description The zeroth bit of this register is the Interlaced bit: ModeN Control ■ Set to 0 for interlaced. ■ Bit 1 of this register is the sequential output control bit (only if the Allow output of color planes in sequence compile-time parameter is enabled).
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–9 The mode registers can only be written to if a mode is marked as invalid. For example, the following steps reconfigure mode 1: 1. Write 0 to the Mode1 Valid register. 2. Write to the mode 1 configuration registers. 3. Write 1 to the Mode1 Valid register. The mode is now valid and can be selected. A currently-selected mode can be configured in this way without affecting the video output of the MegaCore function.
11–10 Chapter 11: Clocked Video Output MegaCore Function Functional Description The Clocked Video Output MegaCore function can take in the SOF signal from a Clocked Video Input MegaCore function and align its own SOF to this signal. The Clocked Video Output SOF signal can be set to any position within the outgoing video frame. The registers used to configure the SOF signal are measured from the rising edge of the F0 vertical sync. A start of frame is indicated by a rising edge on the SOF signal (0 to 1).
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–11 Figure 11–6 shows an example of how to connect the Clocked Video Input and Clocked Video Output MegaCore functions to a video PLL. Figure 11–6.
11–12 Chapter 11: Clocked Video Output MegaCore Function Functional Description Timing Constraints To constrain the Clocked Video Output MegaCore function correctly, add the following file to your Quartus II project: \ip\clocked_video_output\lib\alt_vip_cvo.sdc. When you apply the SDC file, you may see some warning messages in a format as follows: ■ Warning: At least one of the filters had some problems and could not be matched. ■ Warning: * could not be matched with a keeper.
Chapter 11: Clocked Video Output MegaCore Function Functional Description 11–13 Stall Behavior and Error Recovery Once its input FIFO is full, the stall behavior of the Clocked Video Output MegaCore function is dictated by the outgoing video. During horizontal and vertical blanking periods it stalls and does not take in any more video data.
11–14 Chapter 11: Clocked Video Output MegaCore Function Parameter Settings Parameter Settings Table 11–6 lists the Clocked Video Output MegaCore function parameters. Table 11–6. Clocked Video Output Parameter Settings (Part 1 of 2) Parameter Value Description Select preset to load DVI 1080p60, SDI 1080p60, SDI 1080i60, PAL, NTSC You can choose from a list of preset conversions or use the other fields in the dialog box to set up custom parameter values.
Chapter 11: Clocked Video Output MegaCore Function Parameter Settings 11–15 Table 11–6. Clocked Video Output Parameter Settings (Part 2 of 2) Parameter Value Description Frame / Field 1: Vertical front porch 0–65,536, Default = 4 Choose the number of lines in the vertical front porch period for Frame/Field 1. Frame / Field 1: Vertical back porch 0–65,536, Default = 36 Choose the number of lines in the vertical back porch period for Frame/Field 1.
11–16 Chapter 11: Clocked Video Output MegaCore Function Signals Signals Table 11–7 lists the input and output signals for the Clocked Video Output MegaCore function. Table 11–7. Clocked Video Output Signals (Part 1 of 2) Signal Direction Description rst In The MegaCore function asynchronously resets when you assert rst. You must deassert rst synchronously to the rising edge of the is_clk signal.
Chapter 11: Clocked Video Output MegaCore Function Signals 11–17 Table 11–7. Clocked Video Output Signals (Part 2 of 2) Signal Direction Description vcoclk_div Out A divided down version of vid_clk (vcoclk). Setting the Vcoclk Divider register to be the number of samples in a line produces a horizontal reference on this signal that a PLL can use to synchronize its output clock. vid_data Out Clocked video data bus. This bus transfers video data into the MegaCore function.
11–18 Chapter 11: Clocked Video Output MegaCore Function Control Register Maps Control Register Maps Table 11–8 lists the Clocked Video Output MegaCore function control register map. The width of each register is 16 bits. Table 11–8. Clocked Video Output Control Register Map (Part 1 of 2) Address Register Description Bit 0 of this register is the Go bit: ■ Setting this bit to 1 causes the Clocked Video Output MegaCore function to start video data output.
Chapter 11: Clocked Video Output MegaCore Function Control Register Maps 11–19 Table 11–8. Clocked Video Output Control Register Map (Part 2 of 2) Address Register Description 9 Mode1 Horizontal Front Porch Video mode 1 horizontal front porch. Specifies the length of the horizontal front porch in samples. 10 Mode1 Horizontal Sync Length Video mode 1 horizontal synchronization length. Specifies the length of the horizontal synchronization length in samples.
11–20 Video and Image Processing Suite User Guide Chapter 11: Clocked Video Output MegaCore Function Control Register Maps January 2013 Altera Corporation
12. Color Plane Sequencer MegaCore Function Core Overview The Color Plane Sequencer MegaCore function changes how color plane samples are transmitted across the Avalon-ST interface. You can configure the channel order in sequence or in parallel. In addition to reordering color plane samples, the Color Plane Sequencer splits and joins video streams, giving control over the routing of color plane samples.
12–2 Chapter 12: Color Plane Sequencer MegaCore Function Functional Description Combining Color Patterns The Color Plane Sequencer also allows the combination of two Avalon-ST Video streams into a single stream. In this mode of operation, two input color patterns (one for each input stream) are combined and arranged to the output stream color pattern in a user defined way, so long as it contains a valid combination of channels in sequence and parallel.
Chapter 12: Color Plane Sequencer MegaCore Function Functional Description 12–3 Avalon-ST Video packets other than video data packets are duplicated to both outputs. Figure 12–3 shows an example of partially splitting and duplicating an input color pattern. Figure 12–3.
12–4 Chapter 12: Color Plane Sequencer MegaCore Function Functional Description Avalon-ST Video Protocol Parameters The only stream requirement imposed is that when two streams are being combined, the video data packets must contain the same total number of pixels, and to make a valid image, the packets must have the same dimensions. The Color Plane Sequencer can process streams of pixel data of the types listed in Table 12–1. Table 12–1.
Chapter 12: Color Plane Sequencer MegaCore Function Parameter Settings 12–5 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 12–2. Color Plane Sequencer Latency Mode Latency O (cycles) (1) All modes Note to Table 12–2: (1) O refers to a small number of clock cycles, and is not of zero value.
12–6 Chapter 12: Color Plane Sequencer MegaCore Function Signals Table 12–3. Color Plane Sequencer Parameter Settings (Part 2 of 2) Parameter Value Color planes in sequence (dout1) 1–4 Description Choose the number of color planes in sequence for output port dout1. Notes to Table 12–3: (1) Turn on when treating Cb and Cr separately because two pixels worth of data is required. Alternatively, you can turn this parameter off and use channel names C, Y instead of Cb, Y, Cr, Y.
13. Color Space Converter MegaCore Function Core Overview The Color Space Converter MegaCore function transforms video data between color spaces. The color spaces allow you to specify colors using three coordinate values. The Color Space Converter supports a number of predefined conversions between standard color spaces, and allows the entry of custom coefficients to translate between any two three-valued color spaces.
13–2 Chapter 13: Color Space Converter MegaCore Function Functional Description Given a set of nine coefficients [A0, A1, A2, B0, B1, B2, C0, C1, C2] and a set of three summands [S0, S1, S2], the output values on channels 0, 1, and 2 (denoted dout_0, dout_1, and dout_2) are calculated as follows: dout_0 = (A0 × din_0) + (B0 × din_1) + (C0 × din_2) + S0 dout_1 = (A1 × din_0) + (B1 × din_1) + (C1 × din_2) + S1 dout_2 = (A2 × din_0) + (B2 × din_1) + (C2 × din_2) + S2 where din_0, din_1, and din_2 are inputs
Chapter 13: Color Space Converter MegaCore Function Functional Description 13–3 Constant Precision The Color Space Converter MegaCore function requires fixed point types to be defined for the constant coefficients and constant summands. The user entered constants (in the white cells of the matrix in the parameter editor) are rounded to fit in the chosen fixed point type (these are shown in the purple cells of the matrix).
13–4 Chapter 13: Color Space Converter MegaCore Function Functional Description Avalon-ST Video Protocol Parameters The Color Space Converter MegaCore function can process streams of pixel data of the types listed inTable 13–1. Table 13–1. Color Space Converter Avalon-ST Video Protocol Parameters Parameter Value Frame Width Read from control packets at run time. Frame Height Read from control packets at run time. Interlaced / Progressive Either.
Chapter 13: Color Space Converter MegaCore Function Parameter Settings 13–5 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 13–2. Color Space Converter Latency Mode Latency O (cycles) (1) All modes Note to Table 13–2: (1) O refers to a small number of clock cycles, and is not of zero value.
13–6 Chapter 13: Color Space Converter MegaCore Function Parameter Settings Table 13–3. Color Space Converter Parameter Settings Tab, General Page (Part 2 of 2) Parameter Value Description Convert from signed Saturating to minimum value at stage 4, to unsigned by Replacing negative with absolute value Choose the method of signed to unsigned conversion for the results.
Chapter 13: Color Space Converter MegaCore Function Signals 13–7 Table 13–4. Color Space Converter Parameter Settings Tab, Operands Page (Part 2 of 2) Parameter Value Description Coefficient and 0–34, Default = 8 summand fraction bits (2) Specifies the number of fraction bits for the fixed point type used to store the coefficients and summands. Notes to Table 13–4: (1) Editing the coefficient values automatically changes the Color model conversion value to Custom.
13–8 Chapter 13: Color Space Converter MegaCore Function Control Register Maps Control Register Maps Table 13–6 describes the control register map for the Color Space Converter MegaCore function. The width of each register in the Color Space Converter control register map is 32 bits. The coefficient and summand registers use integer, signed 2’s complement numbers. To convert from fractional values, simply move the binary point right by the number of fractional bits specified in the user interface.
14. Control Synchronizer MegaCore Function Core Overview The Control Synchronizer MegaCore function synchronizes the configuration change of MegaCores with an event in a video stream. For example, the MegaCore function could synchronize the changing of a position of a video layer with the changing of the size of the layer.
14–2 Chapter 14: Control Synchronizer MegaCore Function Functional Description scaling ratio of 1:1 (no scaling). The Frame Buffer is configured to drop and repeat; this makes it impossible to calculate when packets streamed into the Frame Buffer are streamed out to the Scaler, which means that the Scaler cannot be configured in advance of a certain video data packet. The Control Synchronizer solves this problem, as described in the following scenario. 1.
Chapter 14: Control Synchronizer MegaCore Function Functional Description 14–3 3. The Video Data Packet and Control Data Packet pair with changed width of 320 have propagated through the Frame Buffer. The Control Synchronizer has detected the change and triggered a write to the Scaler. The Control Synchronizer has stalled the video processing pipeline while it performs the write, as shown in Figure 14–3. Figure 14–3.
14–4 Chapter 14: Control Synchronizer MegaCore Function Functional Description Table 14–1. Control Synchronizer Avalon-ST Video Protocol Parameters (Part 2 of 2) Parameter Value Interlaced / Progressive Run-time controlled. Any valid value supported. Bits per Color Sample Number of bits per color sample selected in the parameter editor. Color Pattern Up to four color planes in parallel, with any number of color planes in sequence.
Chapter 14: Control Synchronizer MegaCore Function Parameter Settings 1 14–5 The latency associated with the initial buffering phase, when a MegaCore function first receives video data, is not included. Parameter Settings Table 14–3 lists the Control Synchronizer MegaCore function parameters. Table 14–3. Control Synchronizer Parameter Settings Parameter Value Description Bits per pixel per color plane 4–16, Default = 8 The number of bits used per pixel, per color plane.
14–6 Chapter 14: Control Synchronizer MegaCore Function Signals Table 14–4. Control Synchronizer Signals (Part 2 of 2) Signal Direction Description din_valid In din port Avalon-ST valid signal. This signal identifies the cycles when the port must input data. dout_data Out dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the MegaCore function. dout_endofpacket Out dout port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet.
Chapter 14: Control Synchronizer MegaCore Function Control Register Maps 14–7 Control Register Maps The width of each register of the frame reader is 32 bits. The control data is read once at the start of each frame. The registers may be safely updated during the processing of a frame. Table 14–5 describes the Control Synchronizer MegaCore function control register map. Table 14–5.
14–8 Video and Image Processing Suite User Guide Chapter 14: Control Synchronizer MegaCore Function Control Register Maps January 2013 Altera Corporation
15. Deinterlacer MegaCore Function Core Overview The Deinterlacer MegaCore function converts interlaced video to progressive video using a bob, weave, or simple motion-adaptive algorithm. Interlaced video is commonly used in television standards such as phase alternation line (PAL) and national television system committee (NTSC), but progressive video is required by LCD displays and is often more useful for subsequent image processing functions.
15–2 Chapter 15: Deinterlacer MegaCore Function Functional Description Figure 15–1 shows a simple block diagram of the Deinterlacer MegaCore function with frame buffering. Figure 15–1.
Chapter 15: Deinterlacer MegaCore Function Functional Description 15–3 Output frames are produced by filling in the missing lines from the current field with the linear interpolation of the lines above and below them. At the top of an F1 field or the bottom of an F0 field there is only one line available so it is just duplicated. The function only uses the current field, therefore if the output frame rate is the same as the input frame rate, the function discards half of the input fields.
15–4 Chapter 15: Deinterlacer MegaCore Function Functional Description The motion-adaptive algorithm fills in the rows that are missing in the current field by calculating a function of other pixels in the current field and the three preceding fields as shown in the following sequence: 1. Pixels are collected from the current field and the three preceding it (the X denotes the location of the desired output pixel) (Figure 15–2). Figure 15–2.
Chapter 15: Deinterlacer MegaCore Function Functional Description 15–5 Output Pixel = M . Upper Pixel + Lower Pixel 2 + (1 - M) . Still Pixel The motion-adaptive algorithm requires the buffering of two frames of data before it can produce any output. The Deinterlacer always consumes the three first fields it receives at start up and after a change of resolution without producing any output.
15–6 Chapter 15: Deinterlacer MegaCore Function Functional Description When triple-buffering is in use, external RAM usually uses three frame buffers. The function uses four frame buffers when you select the motion-adaptive algorithm. At any time, one buffer is in use by the input and one (two for the motion adaptive case) is (are) in use by the output in the same way as the double-buffering case. The last frame buffer is spare. This configuration allows the input and output sides to swap asynchronously.
Chapter 15: Deinterlacer MegaCore Function Functional Description 15–7 By using a double-buffer and controlling the dropping/repeating behavior, the input and output can be kept synchronized. For example, if the input has 60 interlaced fields per second, but the output requires 50 progressive frames per second (fps), setting the input frame rate to 30 fps and the output frame rate at 50 fps guarantees that exactly one frame in six is dropped.
15–8 Chapter 15: Deinterlacer MegaCore Function Functional Description Handling of Avalon-ST Video Control Packets When buffering is used, the Deinterlacer MegaCore function stores non-image data packets in memory as described in “Buffering of Non-Image Data Packets in Memory” on page 3–21. Control packets and user packets are never repeated and they are not dropped or truncated as long as memory space is sufficient.
Chapter 15: Deinterlacer MegaCore Function Functional Description 15–9 When you select the weave algorithm, the MegaCore function may stall for longer than the usual periods between each output row of the image. Stalls of up to 45 clock cycles are possible due to the time taken for internal processing in between lines. When you select the motion-adaptive algorithm, the Deinterlacer may stall up to 90 clock cycles.
15–10 Chapter 15: Deinterlacer MegaCore Function Parameter Settings The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 15–2.
Chapter 15: Deinterlacer MegaCore Function Parameter Settings 15–11 Table 15–3. Deinterlacer Parameter Settings (Part 2 of 3) Parameter Value Description Frame buffering mode (1), (3), (4), (5) No buffering, Double buffering, Triple buffering with rate conversion Specifies whether external frame buffers are used. In no buffering mode, data is piped directly from input to output without using external memory. This is possible only with the bob method.
15–12 Chapter 15: Deinterlacer MegaCore Function Signals Table 15–3. Deinterlacer Parameter Settings (Part 3 of 3) Parameter Value Description Read-only master(s) interface FIFO depth 16–1024, Default = 64 Choose the FIFO depth of the read-only Avalon-MM interface. Read-only master(s) interface burst target 2–256, Default = 32 Choose the burst target for the read-only Avalon-MM interface.
Chapter 15: Deinterlacer MegaCore Function Signals 15–13 Table 15–4. Deinterlacer Signals (Part 2 of 4) Signal Direction Description din_valid In din port Avalon-ST valid signal. This signal identifies the cycles when the port must input data. dout_data Out dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the MegaCore function. dout_endofpacket Out dout port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet.
15–14 Chapter 15: Deinterlacer MegaCore Function Signals Table 15–4. Deinterlacer Signals (Part 3 of 4) Signal Direction Description read_master_N_av_address Out read_master_N port Avalon-MM address bus. This bus specifies a byte address in the Avalon-MM address space. (1), (2), (3) read_master_N_av_burstcount Out read_master_N port Avalon-MM burstcount signal. This signal specifies the number of transfers in each burst. (1), (2), (3) read_master_N_av_clock In read_master_N port clock signal.
Chapter 15: Deinterlacer MegaCore Function Control Register Maps 15–15 Table 15–4. Deinterlacer Signals (Part 4 of 4) Signal Direction Out write_master_av_writedata Description write_master port Avalon-MM writedata bus. These output lines carry data for write transfers. (1), (3) Notes to Table 15–4: (1) The signals associated with the write_master and read_master ports are present only when buffering is used. (2) When you select Motion Adaptive algorithm, two read master interfaces are used.
15–16 Chapter 15: Deinterlacer MegaCore Function Control Register Maps Table 15–5 describes the control register map that synchronizes the input and output frame rates. The control data is read and registered when receiving the image data header that signals new frame. It can be safely updated during the processing of a frame. Table 15–6.
16. Deinterlacer II MegaCore Function Core Overview The Deinterlacer II MegaCore function provides you the option of using high quality motion-adaptive deinterlacing algorithms that significantly enhances edge-adaptive reconstruction and improves image quality streams. The Deinterlacer II does not support lower quality bob and weave deinterlacing.
16–2 Chapter 16: Deinterlacer II MegaCore Function Functional Description Functional Description The features and functionality of the Deinterlacer II MegaCore function are largely similar to those of the Deinterlacer MegaCore Function. The Deinterlacer II does not support bob and weave methods but it can convert interlaced video to progressive video using two high quality motion-adaptive methods.
Chapter 16: Deinterlacer II MegaCore Function Functional Description 1 16–3 You may face throughput issues when you swap the Deinterlacer with the Deinterlacer II in your designs. You can easily fix the throughput issues by instantiating the Frame Buffer MegaCore Function into the designs. ■ The Deinterlacer II only allows one output frame for one input field. The Deinterlacer II uses each interlaced field to construct a deinterlaced frame, which effectively doubles the frame rate.
16–4 Chapter 16: Deinterlacer II MegaCore Function Parameter Settings 1 For more information about the stall behavior and error recovery, refer to “Stall Behavior and Error Recovery” on page 1–3. Latency Table 16–1 lists the approximate latency from the video data input to the video data output for typical usage modes of the Deinterlacer II MegaCore function. You can use this table to predict the approximate latency between the input and the output of your video processing pipeline.
Chapter 16: Deinterlacer II MegaCore Function Parameter Settings 16–5 Table 16–2. Deinterlacer II Parameter Settings (Part 2 of 2) Parameter Value Description Behavior Deinterlace algorithm Motion Adaptive High Quality or Motion Adaptive Choose the deinterlacing algorithm. For high quality progressive video sequence, choose the Motion Adaptive High Quality option. Run-time control On or Off Turn on to enable run-time control for the cadence detection and reverse pulldown.
16–6 Chapter 16: Deinterlacer II MegaCore Function Signals Signals Table 16–3 lists the input and output signals for the Deinterlacer II MegaCore function. Table 16–3. Deinterlacer II Signals (Part 1 of 4) Signal Direction Description In The main system clock. The MegaCore function operates on the rising edge of the av_st_clock signal. av_st_reset In The MegaCore function asynchronously resets when you assert av_st_reset.
Chapter 16: Deinterlacer II MegaCore Function Signals 16–7 Table 16–3. Deinterlacer II Signals (Part 2 of 4) Signal Direction Description control_readdata Out control slave port Avalon-MM readdata bus. These output lines are used for read transfers. (4) control_readdatavalid Out control slave port Avalon-MM readdatavalid bus. The MegaCore function asserts this signal when the readdata bus contains valid data in response to the read signal.
16–8 Chapter 16: Deinterlacer II MegaCore Function Signals Table 16–3. Deinterlacer II Signals (Part 3 of 4) Signal Direction Description ma_read_master_waitrequest In ma_read_master port Avalon-MM waitrequest signal. The system interconnect fabric asserts this signal to cause the master port to wait. (1) motion_read_master_address Out motion_read_master port Avalon-MM address bus. This bus specifies a byte address in the Avalon-MM address space.
Chapter 16: Deinterlacer II MegaCore Function Control Map Registers 16–9 Table 16–3. Deinterlacer II Signals (Part 4 of 4) Signal Direction motion_write_master_waitrequest In Description motion_write_master port Avalon-MM waitrequest signal.The system interconnect fabric asserts this signal to cause the master port to wait. (2) Notes to Table 16–3: (1) Two read master interfaces are used: edi_read_master and ma_read_master.
16–10 Video and Image Processing Suite User Guide Chapter 16: Deinterlacer II MegaCore Function Control Map Registers January 2013 Altera Corporation
17. Frame Reader MegaCore Function Core Overview The Frame Reader MegaCore function reads video frames stored in external memory and outputs them as a video stream. You can configure the MegaCore function to read multiple video frames using an Avalon-MM slave interface. Functional Description The Frame Reader reads video frames stored in external memory and outputs them using the Avalon-ST Video protocol. The Frame Reader has an Avalon-MM read master port that reads data from an external memory.
17–2 Chapter 17: Frame Reader MegaCore Function Functional Description The raw data that comprises a video frame in external memory is stored as a set of single-cycle color patterns. In memory, the single-cycle color patterns must be organized into word-sized sections. Each of these word-sized sections must contain as many whole samples as possible, with no partial single-cycle color patterns. Unused bits are in the most significant portion of the word-sized sections.
Chapter 17: Frame Reader MegaCore Function Parameter Settings 17–3 Avalon-ST Video Protocol Parameters The Avalon-ST Video parameters for the Frame Reader MegaCore function are listed in Table 17–1. Table 17–1. Frame Reader Avalon-ST Video Parameters Parameter Value Frame Width Set via the Avalon-MM slave control port. Maximum value specified in parameter editor. Frame Height Set via the Avalon-MM slave control port. Maximum value specified in parameter editor.
17–4 Chapter 17: Frame Reader MegaCore Function Signals Table 17–2. Frame Reader Parameter Settings (Part 2 of 2) Parameter Value Description Read master FIFO burst target 2–256, Default = 32 The target burst size of the read master Use separate clock for the AvalonMM master interface On or Off Use separate clock for the Avalon-MM master interface Signals Table 17–3 lists the input and output signals for the Frame Reader MegaCore function. Table 17–3.
Chapter 17: Frame Reader MegaCore Function Control Register Maps 17–5 Table 17–3. Frame Reader Signals (Part 2 of 2) Signal Direction Description master_av_read Out master port Avalon-MM read signal. Asserted to indicate read requests from the master to the system interconnect fabric. master_av_readdata In master port Avalon-MM readdata bus. These input lines carry data for read transfers. master_av_readdatavalid In master port Avalon-MM readdatavalid signal.
17–6 Chapter 17: Frame Reader MegaCore Function Control Register Maps Table 17–4. Frame Reader Register Map for Run-Time Control (Part 2 of 2) Address Register Description 11 Frame 1 Base Address The 32-bit base address of the frame. 12 Frame 1 Words The number of words (reads from the master port) to read from memory for the frame. 13 Frame 1 Single Cycle Color Patterns The number of single-cycle color patterns to read for the frame. 14 Frame 1 Reserved Reserved for future use.
18. Frame Buffer MegaCore Function Core Overview The Frame Buffer MegaCore function buffers video frames into external RAM. The Frame Buffer supports double or triple buffering with a range of options for frame dropping and repeating. Functional Description The Frame Buffer MegaCore function buffers progressive or interlaced video fields in external RAM.
18–2 Chapter 18: Frame Buffer MegaCore Function Functional Description A double-buffer is typically used when the frame rate is the same both at the input and at the output sides but the pixel rate is highly irregular at one or both sides. A double-buffer is often used when a frame has to be received or sent in a short period of time compared with the overall frame rate. For example, after the Clipper MegaCore function or before one of the foreground layers of the Alpha Blending Mixer MegaCore function.
Chapter 18: Frame Buffer MegaCore Function Functional Description 18–3 Table 18–5 on page 18–8 lists the control register maps for the Frame Buffer writer component. Interlaced Video Streams In its default configuration the Frame Buffer MegaCore function does not differentiate between interlaced and progressive fields. When interlaced fields are received, the MegaCore function buffers, drops, or repeats fields independently.
18–4 Chapter 18: Frame Buffer MegaCore Function Functional Description Avalon-ST Video Protocol Parameters The Frame Buffer MegaCore function can process streams of pixel data of the type listed in Table 18–1. Table 18–1. Frame Buffer Avalon-ST Video Protocol Parameters Parameter Value Frame Width Run time controlled. Maximum value selected in the parameter editor. Frame Height Run time controlled. Maximum value selected in the parameter editor.
Chapter 18: Frame Buffer MegaCore Function Parameter Settings 18–5 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 18–2. Latency Mode Latency 1 frame +O lines (1) All modes Note to Table 18–2: (1) O refers to a small number of clock cycles, and is not of zero value.
18–6 Chapter 18: Frame Buffer MegaCore Function Signals Table 18–3. Frame Buffer Parameter Settings (Part 2 of 2) Parameter Value Description 10–1024 Specify the maximum packet length as a number of symbols. The minimum value is 10 because this is the size of an Avalon-ST control packet (header included). Extra samples are discarded if packets are larger than allowed.
Chapter 18: Frame Buffer MegaCore Function Signals 18–7 Table 18–4. Frame Buffer Signals (Part 2 of 3) Signal Direction Description din_startofpacket In din port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. din_valid In din port Avalon-ST valid signal. This signal identifies the cycles when the port must input data. dout_data Out dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the MegaCore function.
18–8 Chapter 18: Frame Buffer MegaCore Function Control Register Maps Table 18–4. Frame Buffer Signals (Part 3 of 3) Signal Direction Description write_master_av_burstcount Out write_master port Avalon-MM burstcount signal. Specifies the number of transfers in each burst. write_master_av_clock In write_master port clock signal. The interface operates on the rising edge of the clock signal. (1) write_master_av_reset In write_master port reset signal.
Chapter 18: Frame Buffer MegaCore Function Control Register Maps 18–9 Table 18–5. Frame Buffer Control Register Map for the Writer Component (Part 2 of 2) Address Register(s) Description 2 Frame Counter Read-only register updated at the end of each frame processed by the writer. The counter is incremented if the frame is not dropped and passed to the reader component. 3 Drop Counter Read-only register updated at the end of each frame processed by the writer.
18–10 Video and Image Processing Suite User Guide Chapter 18: Frame Buffer MegaCore Function Control Register Maps January 2013 Altera Corporation
19. Gamma Corrector MegaCore Function Core Overview The Gamma Corrector MegaCore function corrects video streams for the physical properties of display devices. For example, the brightness displayed by a cathode-ray tube monitor has a nonlinear response to the voltage of a video signal. You can configure the Gamma Corrector with a look-up table that models the nonlinear function to compensate for the non linearity. The look-up table can then transform the video data and give the best image on the display.
19–2 Chapter 19: Gamma Corrector MegaCore Function Parameter Settings Error Recovery The Gamma Corrector MegaCore function processes video packets until an endofpacket signal is received. Non-image packets are propagated but the content of control packets is ignored. For this MegaCore function there is no such condition as an early or late endofpacket. Any mismatch of the endofpacket signal and the frame size is propagated unchanged to the next MegaCore function.
Chapter 19: Gamma Corrector MegaCore Function Signals 1 19–3 You program the actual gamma corrected intensity values at run time using the Avalon-MM slave interface. Signals Table 19–4 lists the input and output signals for the Gamma Corrector MegaCore function. Table 19–4. Gamma Corrector Signals Signal Direction Description clock In The main system clock. The MegaCore function operates on the rising edge of the clock signal.
19–4 Chapter 19: Gamma Corrector MegaCore Function Control Register Maps Control Register Maps The Gamma Corrector can have up to three Avalon-MM slave interfaces. There is a separate slave interface for each channel in parallel. Table 19–5 to Table 19–7 describe the control register maps for these interfaces.
Chapter 19: Gamma Corrector MegaCore Function Control Register Maps 19–5 Table 19–7. Gamma Corrector Control Register Map: Interface 2 Address Register Name Description 0 Unused This register is not used 1 Unused This register is not used 2 to 2N +1 where N Gamma Lookis the number of Up Table bits per color plane. January 2013 Altera Corporation These registers contain a look-up table that is used to apply gamma correction to video data.
19–6 Video and Image Processing Suite User Guide Chapter 19: Gamma Corrector MegaCore Function Control Register Maps January 2013 Altera Corporation
20. Interlacer MegaCore Function Core Overview The Interlacer MegaCore function converts progressive video to interlaced video by dropping half the lines of incoming progressive frames. You can configure the MegaCore function to discard or propagate already-interlaced input. You can also disable the interlacer at run time to propagate progressive frames unchanged.
20–2 Chapter 20: Interlacer MegaCore Function Functional Description Avalon-ST Video Protocol Parameters The Interlacer MegaCore function can process streams of pixel data of the types listed in Table 20–1. The Interlacer does not support vertically subsampled video streams. For example, 4:2:2 is supported but 4:2:0 is not. Table 20–1. Interlacer Avalon-ST Video Protocol Parameters Parameter Value Frame Width Run time controlled. (Maximum value specified in the parameter editor.
Chapter 20: Interlacer MegaCore Function Parameter Settings 20–3 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 20–2. Interlacer Latency Mode Latency O (cycles) (1) All modes Note to Table 20–2: (1) O refers to a small number of clock cycles, and is not of zero value.
20–4 Chapter 20: Interlacer MegaCore Function Signals Signals Table 20–4 shows the input and output signals for the Interlacer MegaCore function. Table 20–4. Interlacer Signals Signal Direction Description clock In The main system clock. The MegaCore function operates on the rising edge of the clock signal. reset In The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal.
Chapter 20: Interlacer MegaCore Function Control Register Maps 20–5 Control Register Maps Table 20–5 describes the control register map for the Interlacer. The control interface is 8 bits wide but the Interlacer only uses bit 0 of each addressable register. Table 20–5. Interlacer Control Register Map Address Register Description 0 Control Bit 0 of this register is the Go bit. All other bits are unused.
20–6 Video and Image Processing Suite User Guide Chapter 20: Interlacer MegaCore Function Control Register Maps January 2013 Altera Corporation
21. Scaler MegaCore Function Core Overview The Scaler MegaCore function resizes video streams. The Scaler supports nearestneighbor, bilinear, bicubic, and polyphase scaling algorithms. You can configure the Scaler to change resolutions or filter coefficients, or both, at run time using an AvalonMM slave interface. Functional Description The Scaler MegaCore function provides a means to resize video streams. It supports nearest neighbor, bilinear, bicubic, and polyphase scaling algorithms.
21–2 Chapter 21: Scaler MegaCore Function Functional Description This equation gives an answer relative to the mid-point of the input pixel. You must subtract 0.5 to translate from pixel positions to grid positions. However, this 0.5 would then be added again so that later truncation performs rounding to the nearest integer. Therefore no change is required.
Chapter 21: Scaler MegaCore Function Functional Description 21–3 The sum is then weighted proportionally to these errors. Note that because the values are measured from the top-left pixel, the weights for this pixel are one minus the error.
21–4 Chapter 21: Scaler MegaCore Function Functional Description Figure 21–1 shows the flow of data through an instance of the scaler in polyphase mode.this. Figure 21–1. Polyphase Mode Scaler Block Diagram Line Buffer Delay Line Buffer Delay Cv 0 Cv 1 Cv Nv ě Bit Narrowing Register Delay Ch 0 Ch 1 Register Delay Ch Nh ě Bit Narrowing Data from multiple lines of the input image are assembled into line buffers–one for each vertical tap.
Chapter 21: Scaler MegaCore Function Functional Description 21–5 Bv is the bit width of the vertical coefficients and is derived from the user parameters for the vertical coefficients. It is equal to the sum of integer bits and fraction bits for the vertical coefficients, plus one if coefficients are signed. Bh is defined similarly for horizontal coefficients. Pv and Ph are the user-defined number of vertical and horizontal phases for each coefficient set.
21–6 Chapter 21: Scaler MegaCore Function Functional Description Algorithmic Description This section describes how the algorithmic operations of the polyphase scaler can be modelled using a frame-based method. This description shows how the filter kernel is applied and how coefficients are loaded, but is not intended to indicate how the hardware of the scaler is designed. The filtering part of the polyphase scaler works by passing a windowed sinc function over the input data.
Chapter 21: Scaler MegaCore Function Functional Description 1 21–7 The two lobes refer to the number of times the function changes direction on each side of the central maxima, including the maxima itself. The class of Lanczos N functions is defined as: 1 sin x sin x N LanczosN x = -------------------- ---------------------------x x N 0 x = 0 x0 x N x N As can be seen in the figure, phase 0 centers the function over tap 1 on the x-axis.
21–8 Chapter 21: Scaler MegaCore Function Functional Description In summary, you can generate a set of coefficients for an N-tap, P-phase instance of the Scaler as follows: 1. Define a function, f(x) over the domain [0, N – 1] under the assumption that (N – 1)/2 is the mid-point of the filter. 2. For each tap t Î {0, 1, . . . ,N – 1} and for each phase p {0, 1/P, . . . , (P – 1/P)}, sample f(t – p). 3. Quantize each sample. Ideally, the sum of the quantized values for all phases must be equal. 4.
Chapter 21: Scaler MegaCore Function Functional Description 21–9 Table 21–1 summarizes some recommended values for parameters when using the Scaler in polyphase mode. Table 21–1.
21–10 Chapter 21: Scaler MegaCore Function Functional Description ■ In bilinear mode, a complete line of input is read into a buffer before any output is produced. At the end of a frame there are no reads as this buffer is drained. Exactly how many writes are possible during this time depends on the scaling ratio. ■ In bicubic mode, three lines of input are read into line buffers before any output is ready.
Chapter 21: Scaler MegaCore Function Parameter Settings 21–11 The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 21–3. Scaler Latency Mode Latency Scaling algorithm: Polyphase (N–1) lines +O (cycles) (1) Number of vertical taps: N Note to Table 21–3: (1) O refers to a small number of clock cycles, and is not of zero value.
21–12 Chapter 21: Scaler MegaCore Function Parameter Settings Table 21–5. Scaler Parameter Settings Tab, Algorithm and Precision Page (Part 2 of 2) Parameter Value Description Number of horizontal phases 2, 4, 8, 16, 32, 64, 128, 256 Specify the number of horizontal phases. Vertical Coefficient Precision: Signed On or Off Turn on if you want the fixed-point type that stores the vertical coefficients to have a sign bit.
Chapter 21: Scaler MegaCore Function Parameter Settings 21–13 Table 21–6. Scaler Parameter Settings Tab, Coefficients Page (Part 2 of 2) Parameter Value Description Horizontal Coefficient Data: User specified Custom coefficient file When a custom function is selected, you can browse for a comma-separated value file containing custom coefficients. Key in the path for the file that contains these custom coefficients.
21–14 Chapter 21: Scaler MegaCore Function Signals Signals Table 21–7 lists the input and output signals for the Scaler MegaCore function. Table 21–7. Scaler Signals Signal Direction Description clock In The main system clock. The MegaCore function operates on the rising edge of the clock signal. reset In The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal.
Chapter 21: Scaler MegaCore Function Control Register Maps 21–15 Control Register Maps Table 21–8 describes the Scaler MegaCore function control register map. The Scaler reads the control data once at the start of each frame and buffers the data inside the MegaCore function. The registers may be safely updated during the processing of a frame, unless the frame is a coefficient bank. The coefficient bank that is being read by the Scaler must not be written to unless the core is in a stopped state.
21–16 Chapter 21: Scaler MegaCore Function Control Register Maps Table 21–8. Scaler Control Register Map (Part 2 of 2) Address 9+Nh to 8+Nh+Nh+N Register Description Vertical Tap Data Specifies values for the vertical coefficients at a particular phase. Write these values first, then the Vertical Phase to commit the write. (2) Vertical Phase Specifies which phase the Vertical Tap Data applies to. Writing to this location, commits the writing of tap data.
22. Scaler II MegaCore Function Core Overview The Scaler II MegaCore function resizes video streams and offers improved functionality compared to the Scaler MegaCore Function. The Scaler II supports nearest neighbor, bilinear, bicubic and polyphase scaling algorithms, but extends beyond the functionality of the Scaler by supporting a simple edge-adaptive scaling algorithm and 4:2:2 sampled video data.
22–2 Chapter 22: Scaler II MegaCore Function Functional Description Edge-Adaptive Scaling Algorithm In the edge-adaptive mode, each bank of scaling coefficients inside the Scaler II consists of the following two full coefficient sets: ■ A set for pixels that do not lie on the edge—allows you to select a coefficient set with a softer frequency response for the non-edge pixels ■ A set for pixels that lie on the edges—allows you to select a coefficient set with a harsher frequency response for the edge pi
Chapter 22: Scaler II MegaCore Function Functional Description ■ 22–3 In polyphase mode with Nv vertical taps, Nv – 1 lines of input are read into line buffers before any output is ready. As with bilinear mode, there is a scaling ratio dependent time at the end of a frame where no reads are required as the buffers are drained.
22–4 Chapter 22: Scaler II MegaCore Function Parameter Settings The latency is measured with the assumption that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). Table 22–1. Scaler II Latency Mode Latency Scaling algorithm: Polyphase (N–1) lines + O (cycles) (1) Number of vertical taps: N Note to Table 22–1: (1) O refers to a small number of clock cycles, and is not of zero value.
Chapter 22: Scaler II MegaCore Function Parameter Settings 22–5 Table 22–2. Scaler II Parameter Settings Tab Parameter Value Description Algorithm Settings Scaling algorithm Nearest Neighbor, Bilinear, Bicubic, Polyphase, or Edge Adaptive Choose the scaling algorithm. For more information about these options, refer to , “Nearest Neighbor Algorithm” on page 21–1, “Bilinear Algorithm” on page 21–2, “Polyphase and Bicubic Algorithms” on page 21–3, and “Edge-Adaptive Scaling Algorithm” on page 22–2.
22–6 Chapter 22: Scaler II MegaCore Function Parameter Settings Table 22–2. Scaler II Parameter Settings Tab Parameter Value Description Horizontal coefficient integer bits 0–32, Default = 1 Choose the number of integer bits for each horizontal coefficient. Horizontal coefficient fraction bits 1–32, Default = 7 Choose the number of fraction bits for each horizontal coefficient. Default = 0 Choose the number of fractional bits you want to preserve between the horizontal and vertical filtering.
Chapter 22: Scaler II MegaCore Function Signals 22–7 Signals Table 22–3 lists the input and output signals for the Scaler II MegaCore function. Table 22–3. Scaler II Signals (Part 1 of 2) Signal Direction Description main_clock In The main system clock. The MegaCore function operates on the rising edge of the main_clock signal. main_reset In The MegaCore function asynchronously resets when you assert main_reset.
22–8 Chapter 22: Scaler II MegaCore Function Control Register Maps Table 22–3. Scaler II Signals (Part 2 of 2) Signal Direction Description dout_startofpacket Out dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. dout_valid Out dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data.
Chapter 22: Scaler II MegaCore Function Control Register Maps 22–9 Table 22–4. Scaler II Control Register Map (Part 2 of 2) Address 4 Register Description Output Height The height of the output frames in pixels. Edge Threshold Specifies the minimum difference between neighboring pixels beyond which the edge-adaptive algorithm switches to using the edge coefficient set. To get the threshold used internally, this value is multiplied by the number of color planes per pixel.
22–10 Video and Image Processing Suite User Guide Chapter 22: Scaler II MegaCore Function Control Register Maps January 2013 Altera Corporation
23. Switch MegaCore Function Core Overview The Switch MegaCore function allows the connection of up to twelve input video streams to twelve output video streams and the run-time reconfiguration of those connections via a control input. Functional Description The Switch MegaCore function allows the connection of up to twelve input video streams to twelve output video streams. For example, 1 to 2, 4 to 1, 6 to 6, and so on. The connections can be reconfigured at run time via a control input.
23–2 Chapter 23: Switch MegaCore Function Functional Description Figure 23–1 shows the system configuration used to achieve this. Figure 23–1.
Chapter 23: Switch MegaCore Function Parameter Settings 23–3 Latency Table 23–1 lists the approximate latency from the video data input to the video data output for typical usage modes of the Switch MegaCore function. You can use this table to predict the approximate latency between the input and the output of your video processing pipeline.
23–4 Chapter 23: Switch MegaCore Function Signals Signals Table 23–3 lists the input and output signals for the Switch MegaCore function. Table 23–3. Switch Signals (Part 1 of 2) Signal Direction Description clock In The main system clock. The MegaCore function operates on the rising edge of the clock signal. reset In The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal.
Chapter 23: Switch MegaCore Function Control Register Map 23–5 Table 23–3. Switch Signals (Part 2 of 2) Signal Direction Description dout_N_startofpacket Out dout_N port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. dout_N_valid Out dout_N port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data. Note to Table 23–3: (1) These ports are present only when Alpha Enabled is turned on in the parameter editor.
23–6 Video and Image Processing Suite User Guide Chapter 23: Switch MegaCore Function Control Register Map January 2013 Altera Corporation
24. Test Pattern Generator MegaCore Function Core Overview The Test Pattern Generator MegaCore function generates a video stream that displays either still color bars for use as a test pattern or a constant color for use as a uniform background. You can use this MegaCore function during the design cycle to validate a video system without the possible throughput issues associated with a real video input.
24–2 Chapter 24: Test Pattern Generator MegaCore Function Functional Description The actual numerical values are given in Table 24–1 (assuming 8 bits per color samples). If the output is requested in a different number of bits per color sample these values are converted by truncation or promotion. Table 24–1.
Chapter 24: Test Pattern Generator MegaCore Function Functional Description 24–3 do once for progressive output or twice for interlaced output { send_control_packet(); send_image_data_header(); output_test_pattern (); } } Avalon-ST Video Protocol Parameters The Test Pattern Generator MegaCore function supports a wide range of resolutions and color spaces with either a sequential or parallel data interface.
24–4 Chapter 24: Test Pattern Generator MegaCore Function Parameter Settings Table 24–2.
Chapter 24: Test Pattern Generator MegaCore Function Signals 24–5 Table 24–3. Test Pattern Generator Parameter Settings (Part 2 of 2) Parameter Value Description Bits per pixel per color plane 4–20, Default = 8 Choose the number of bits per pixel (per color plane). Color space RGB or YCbCr Choose whether to use an R’G’B’ or Y’CbCr color space. Output format 4:4:4, 4:2:2, 4:2:0 Choose the format/sampling rate format for the output frames.
24–6 Chapter 24: Test Pattern Generator MegaCore Function Control Register Map Table 24–4. Test Pattern Generator Signals (Part 2 of 2) Signal Direction Out dout_valid Description dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data. Note to Table 24–4: (1) These ports are present only if you turn on Run-time control of image size. Control Register Map The width of each register in the Test Pattern Generator control register map is 16 bits.
25. Trace System MegaCore Function Core Overview The Trace System MegaCore function is a debugging and monitoring component. The trace system collects data from various monitors, such as the Avalon-ST monitor, and passes it to the System Console software on the attached debugging host. The System Console software allows you to capture and visualize the behavior of the attached system.
25–2 Chapter 25: Trace System MegaCore Function Parameter Settings Each trace monitor sends information about interesting events through its capture interface. The trace system multiplexes these data streams together and, if the trace systems is running, stores them into a FIFO buffer. The contents of this buffer are streamed to the host using as much as the available trace bandwidth.
Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console 25–3 Table 25–2. Trace System Signals (Part 2 of 2) Signal Direction Description usb_if_reset_n In Reset driven by On-Board USB-Blaster II. usb_if_full Out Host to the target full signal. usb_if_empty Out Target to the host empty signal. usb_if_wr_n In Write enable to the host to target FIFO. usb_if_rd_n In Read enable to the target to host FIFO. usb_if_oe_n In Output enable for data signals.
25–4 Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console Loading the Project and Connecting to the Hardware To connect to the Trace System, the System Console needs access to the hardware and to the information about what the board does. To enable access for System Console, follow these steps: 1. Connect to the host by doing one of the following: ■ Connect the On-Board USB-Blaster II to the host with the USB cable.
Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console 25–5 4. After loading your design, link it to the devices detected by System Console. Do one of the following: ■ In the System Console window, right click on the device folder, and click Link device to. Then select your uploaded design. If your design has a JTAG USERCODE, the System Console is able to match it to the device and automatically links it after design is loaded.
25–6 Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console Table 25–3 lists the function for each trace bar icon. Table 25–3. Functions for Trace Control Bar Icons Icon Function Settings Displays the configuration dialogue again. Start Tells the trace system to start acquiring data. Data is displayed in the table view as soon as possible after it is acquired. Stop Stops acquiring data.
Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console 25–7 Table 25–4. Trace System Commands (Part 2 of 2) Command Arguments trace_read_monitor trace_write_monitor trace_get_max_db_size Function Reads a 32-bit value from configuration space within the specified monitor. Refer to the trace monitor documentation for the register maps. Writes a 32-bit value from configuration space within the specified monitor.
25–8 Video and Image Processing Suite User Guide Chapter 25: Trace System MegaCore Function Operating the Trace System from System Console January 2013 Altera Corporation
A. Avalon-ST Video Verification IP Suite This chapter describes the Avalon-ST Video Verification IP Suite. The Avalon-ST Video Verification IP Suite provides a set of SystemVerilog classes (the class library) that you can use to ensure that a Video IP conforms to the Avalon-ST Video standard.
A–2 Appendix A: Avalon-ST Video Verification IP Suite Avalon-ST Video Class Library In Figure A–1, DUT is fed with Avalon-ST Video-compliant video packets and control packets. The responses from the DUT are collected, analyzed, and the resultant video written to an output file.
Appendix A: Avalon-ST Video Verification IP Suite Avalon-ST Video Class Library A–3 Figure A–2. UML-Style Class Diagram av_st_video_source_bfm_class.sv av_st_video_sink_bfm_class.
A–4 Appendix A: Avalon-ST Video Verification IP Suite Avalon-ST Video Class Library Table A–1 describes each of the classes in the av_st_video_classes package shown in Figure A–2. Table A–1. Class Descriptions Class class c_av_st_video_item Description Parameter The most fundamental of all the classes. Represents any item that is sent over the Avalon-ST bus and contains a packet_type field. You can set the field to video_packet, control_packet, or user_packet types.
Appendix A: Avalon-ST Video Verification IP Suite Avalon-ST Video Class Library A–5 The classes listed in Table A–1 do not contain information about the physical transport mechanism and the Avalon-ST Video protocol. To foster advanced verification techniques, Altera uses a high-level abstract view. Table A–2 describes the classes included in the av_st_video_file_io_class package and the source and sink class packages. Table A–2.
A–6 Appendix A: Avalon-ST Video Verification IP Suite Avalon-ST Video Class Library Table A–2. Additional Class Descriptions (Part 2 of 2) Class class c_av_st_video_sink_bfm_’SINK Description Operates in the same way as the source class except it contains a receive_video() task and performs the opposite function to the source.
Appendix A: Avalon-ST Video Verification IP Suite Types of Example Test Environment A–7 Figure A–3 shows the solution to the Avalon-ST BFM API function. Figure A–3. How the Class Library interfaces to the Avalon-ST BFM tb.
A–8 Appendix A: Avalon-ST Video Verification IP Suite Types of Example Test Environment Running the Tests This example system is available in the Quartus II install directory at: 1 ■ For example video files test: $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification/example_video_files ■ For constrained random test: $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification/ example_constrained_random The actual commands used in this section are for a Linux example.
Appendix A: Avalon-ST Video Verification IP Suite Types of Example Test Environment A–9 Figure A–4. QSys Dialog Box 6. Create the tb.v netlist from the Qsys project by selecting Generation, set Create simulation model to Verilog. Select Generate. Close the generate completed dialog box, and exit Qsys. Qsys has now generated the tb.v netlist and all the required simulation files, as shown in Figure A–5. Figure A–5. tb.
A–10 Appendix A: Avalon-ST Video Verification IP Suite Types of Example Test Environment 7. Run the test by changing to the example video files test or example constrained random test directory and start the QuestaSim™ software: ■ For example video files test: >cd $ALTERA_VIDEO_VERIFICATION/example_video_files >vsim –do run.tcl ■ For constrained random test: >cd $ALTERA_VIDEO_VERIFICATION/example_constrained_random >vsim –do run.tcl 1 To run with other simulators, edit the run.
Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test A–11 Video File Reader Test This section describes the example test environment shown in Figure A–1 on page A–1—the simplest way of using the class library. A video file is read, translated into video_item objects, streamed to the DUT by the BFM, and then retranslated back into video, and written to file again. This section focuses on the non-standard elements of the environment that requires input shown in Figure A–1 on page A–1.
A–12 Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test tb_test.sv—Section 1 Example A–1 shows the first section of the code. Example A–1. tb_test.sv—Section 1 `timescale 1ns / 1ns module tb_test; `define CHANNELS_PER_PIXEL `define BITS_PER_CHANNEL 3 8 import av_st_video_classes::*; import av_st_video_file_io_class::*; // Create clock and reset: logic clk, reset; initial clk <= 1'b0; always #2.
Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test A–13 tb_test.sv—Section 2 Example A–2 shows the second section of the code. Example A–2. tb_test_sv (Section 2) // // // // This creates a class with a names specific to `SOURCE0, which is needed because the class calls functions for that specific `SOURCE0. A class is used so that individual mailboxes can be easily associated with individual sources/sinks : // This names MUST match the instance name of the source in tb.
A–14 Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test tb_test.sv—Section 3 Example A–3 shows the third section of the code. Example A–3. tb_test.sv (Section 3) initial begin wait (resetn == 1'b1) repeat (4) @ (posedge (clk)); // Constructors associate the mailboxes with the source and sink classes `SOURCE = new(m_video_items_for_src_bfm); `SINK = new(m_video_items_for_sink_bfm); `SOURCE.set_pixel_transport(`TRANSPORT); `SINK.set_pixel_transport(`TRANSPORT); `SOURCE.
Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test A–15 tb_test.sv—Section 4 Example A–4 shows the final section of the code. Example A–4. tb_test.sv (Section 4) fork `SOURCE.start(); `SINK.start(); begin // File reader : // Associate the source BFM's video in mailbox with the video // file reader object via the file reader's constructor : video_file_reader = new(m_video_items_for_src_bfm); video_file_reader.set_object_name("file_reader_0"); video_file_reader.open_file("flag_i_crop.
A–16 Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test The use of mailboxes allows you to set up events without concern as to whether a particular source or sink is ready. This allows you to issue all the commands to the file reader before constructing the file writer (refer to the final part of Example A–4). The writer is constructed, named, and an output file specified. wait_for_and_write_video_packets_to_file method is then called.
Appendix A: Avalon-ST Video Verification IP Suite Video File Reader Test A–17 In Stage 3, the video source BFM retrieves the data from its mailbox, recasts the data back into a c_av_st_video_data video object, and begins translating it into transactions for the Avalon-ST source BFM. To indicate that a video packet is being sent, there is one transaction per pixel and an initial transaction with LSBs of 0×0 when using RGB24 data, 24-bit data buses, and parallel transmission.
A–18 Appendix A: Avalon-ST Video Verification IP Suite Constrained Random Test Constrained Random Test This section describes the function of a constrained random test. The test is easily assembled using the class library. Figure A–7 shows the constrained random test environment structure. Figure A–7. Example of a Constrained Random Test Environment tb_test.v (test environment) tb.
Appendix A: Avalon-ST Video Verification IP Suite Constrained Random Test A–19 Example A–5. Constrained Random Generation fork `SOURCE.start(); `SINK.start(); forever begin // Randomly determine which packet type to send : r = $urandom_range(100, 0); if (r>67) begin video_data_pkt1.set_max_length(100); video_data_pkt1.randomize(); video_data_pkt1.populate(); // Send it to the source BFM : m_video_items_for_src_bfm.
A–20 Appendix A: Avalon-ST Video Verification IP Suite Constrained Random Test The code in Example A–5 starts the source and sink, then randomly generates either a video data, control or user packet.
Appendix A: Avalon-ST Video Verification IP Suite Constrained Random Test A–21 Example A–6 shows the codes for the scoreboards. Example A–6. Scoreboard c_av_st_video_item ref_pkt; c_av_st_video_item dut_pkt; initial begin forever begin @event_constrained_random_generation begin // Get the reference item from the scoreboard mailbox : m_video_items_for_scoreboard.get(ref_pkt); // If the reference item is a video packet, then check // for the control & video packet response : if (ref_pkt.
A–22 Appendix A: Avalon-ST Video Verification IP Suite Constrained Random Test If the reference video item is a video_packet type, the scoreboard code shown in Example A–6 receives the reference video item from the scoreboard mailbox. The code then receives two consecutive items from the DUT and checks whether or not these items are a control and video packet.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–23 A complete test would set up functional coverpoints in the DUT code and use the SystemVerilog’s get_coverage() call to run the test until the required amount of coverage has been seen. The Avalon-ST BFM monitors (available in Qsys) include a comprehensive set of functional coverage points (in the altera_avalon_st_monitor_coverage.
A–24 Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference Table A–3. Method Calls for the c_av_st_video_control Class (Part 2 of 2) Method Call Description function void set_garbage_probability (int i); — function string info(); Returns a formatted string containing the width, height and interlacing members. Table A–4 lists the members of the method calls. Table A–4.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–25 Table A–5. Method Calls for the c_av_st_video_data Class (Part 2 of 2) Method Call Description function void unpopulate(bit display); Pops all pixels from the packet, displaying them if display = 1. function void push_pixel(c_pixel #(BITS_PER_CHANNEL, CHANNELS_PER_PEXEL)pixel); Pushes a pixel into the packet. Table A–6 lists the members of the method calls. Table A–6.
A–26 Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference Table A–7. Method Calls for the c_av_st_video_file_io Class (Part 2 of 3) Method Call Description If the send_early_eop_packets control is set to random, function void set_early_eop_probability(int s); the early_eop_probability control determines what proportion of video packets are terminated early.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–27 Table A–7. Method Calls for the c_av_st_video_file_io Class (Part 3 of 3) Method Call Description Sets the fourcc[3] code associated with the raw video data.
A–28 Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference Table A–8 lists the members of the method calls. Table A–8. Members of the c_av_st_video_file_io Class (Part 1 of 2) Members Description local int video_packets_handled = 0; Video_packets_handled is added whenever a packet is read or written to or from the file. local int control_packets_handled = 0; control_packets_handled is added whenever a control packet is put in the object’s mailbox.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–29 Table A–8.
A–30 Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference c_av_st_video_source_sink_base The following is the declaration for the c_av_st_video_source_sink_base class: class c_av_st_video_source_sink_base; Table A–11 lists the method calls for the c_av_st_video_source_sink_base class. Table A–11. Method Calls for the c_av_st_video_source_sink_base Class Method Call Description Constructor. The video source and sink classes transfer video objects through their mailboxes.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–31 Table A–12. Members of the c_av_st_video_source_sink_base Class Member Description real long_delay_probability = 0.01; The readiness_probability control provides a ‘steady state’ readiness condition. The long_delay_probability allows for the possibility of a much rarer and longer period of unreadiness, of durations of the order of the raster line period or even field period.
A–32 Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference c_av_st_video_source_bfm_’SOURCE The following is the declaration for the c_av_st_video_source_bfm_’SOURCE class: ‘define CLASSNAME c_av_st_video_source_bfm_’SOURCE class ‘CLASSNAME extends c_av_st_video_source_sink_base; Table A–14 lists the method calls for the c_av_st_video_source_bfm_’SOURCE class. 1 This class has no additional members to those of the base class. Table A–14.
Appendix A: Avalon-ST Video Verification IP Suite Complete Class Reference A–33 Table A–15. Method Calls for the c_av_st_video_user_packet Class (Part 2 of 2) Method Call Description function bit [BITS_PER_CHANNEL*CHANNELS_PER_PIXEL1:0] query_data(int i); Returns the next beat of user data without removing it from the object. function void push_data(bit [BITS_PER_CHANNEL*CHANNELS_PER_PIXEL-1:0] d); — Table A–16 lists the members of the method calls for the c_av_st_video_user_packet class.
A–34 Appendix A: Avalon-ST Video Verification IP Suite Raw Video Data Format Raw Video Data Format Altera provides and recommends two Microsoft Windows utilities for translating between .avi and .raw file formats. Example A–8 shows ways to convert an .avi file. Example A–8. Convert .raw to .avi file >avi2raw.exe vip_car_0.avi vip_car_0.raw "dshow" decoder created Information on the input file: filename: vip_car_0.
Appendix A: Avalon-ST Video Verification IP Suite Raw Video Data Format A–35 Example A–9 shows ways to produce a .raw file together with a .spc file that contains the FOURCC information: Example A–9. .raw and .spc Files > more vip_car_0.spc fourcc = RGB32 width = 160 height = 120 stride = 640 frame_rate = 25 To decode the data, the file I/O class reader must see both the .raw and .spc files. The file I/O class reader writes a .raw/.spc file pair that you can view using the .
A–36 Appendix A: Avalon-ST Video Verification IP Suite Raw Video Data Format Example A–11 shows and describes the data format required by the file I/O class for each of the supported FOURCC codes. Example A–11.
B. Choosing the Correct Deinterlacer Figure B–1 through Figure B–3 show some example output from the various deinterlacer options available. The lowest quality is a simple Bob deinterlacer. The highest quality is motion adaptive high quality (HQ) setting in the Deinterlacer II MegaCore function. Figure B–1. Bob Deinterlacing Option To enable this option, open the Deinterlacer MegaWizard Plug-In Manager.
B–2 Appendix B: Choosing the Correct Deinterlacer Figure B–2. Deinterlacer I and Deinterlacer II Motion Adaptive To enable this option in the Deinterlacer MegaCore function, open the Deinterlacer MegaWizard Plug-In Manager. In the Parameter Settings tab, under the Behavior parameter, select Motion Adaptive from the Deinterlacing method drop-down option and select Triple buffering with rate conversion from the Frame buffering mode drop-down option.
Appendix B: Choosing the Correct Deinterlacer Cadence Detection and Reverse Pulldown in the Deinterlacer II MegaCore Function—In Depth B–3 Figure B–3. Deinterlacer II Motion Adaptive High Quality To enable this option, open the Deinterlacer II MegaWizard Plug-In Manager. In the Parameter Settings tab, under the Behavior parameter, select Motion Adaptive High Quality from the Deinterlacing method drop-down option.
B–4 Appendix B: Choosing the Correct Deinterlacer Cadence Detection and Reverse Pulldown in the Deinterlacer II MegaCore Function—In Depth For broadcast, a telecine is applied to minimize artifacts due to the rate conversion, which introduces a 3:2 cadence to the fields, as shown in Figure B–5: Figure B–5.
Appendix B: Choosing the Correct Deinterlacer Cadence Detection and Reverse Pulldown in the Deinterlacer II MegaCore Function—In Depth B–5 When the cadence detect component enters a lock state, the deinterlacer continuously assembles a coherent frame from the incoming fields, by either weaving the current incoming field with the previous one (shown as weave current in Figure B–7) or by weaving the two past fields together (weave past), as shown in Figure B–7: Figure B–7.
B–6 Video and Image Processing Suite User Guide Appendix B: Choosing the Correct Deinterlacer Cadence Detection and Reverse Pulldown in the Deinterlacer II MegaCore Function—In Depth January 2013 Altera Corporation
Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table lists the revision history for this document. Date Version January 2013 July 2012 12.0 February 2012 May 2011 January 2013 11.1 11.0 January 2011 July 2010 12.1 10.1 10.0 Altera Corporation Changes ■ Added Deinterlacer II Sobel-Based HQ Mode section in the “Deinterlacer II MegaCore Function” chapter.
Info–2 Additional Information How to Contact Altera Date Version November 2009 March 2009 9.1 8.0 Changes ■ Added new Frame Reader, Control Synchronizer, and Switch MegaCore functions. ■ The Frame Buffer MegaCore function supports controlled frame dropping or repeating to keep the input and output frame rates locked together. The Frame Buffer also supports buffering of interlaced video streams.
Additional Information Typographic Conventions Visual Cue Info–3 Meaning Indicates variables. For example, n + 1. italic type Variable names are enclosed in angle brackets (< >). For example, and .pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. “Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.
Info–4 Video and Image Processing Suite User Guide Additional Information Typographic Conventions January 2013 Altera Corporation
