V-color Technology Corp. Memory Module Data Sheet DDR4 R-DIMM Based on 2Gx4 Hynix IC TR432G24D417 Part Number TR432G24D417 Module Type Registered DIMM Memory Type DDR4 Standard JEDEC Pin Number 288 Capacity 32GB Speed 2400 MHz Voltage 1.2V Rank Number 2Rx4 CAS Latency 17 Operation Temperature 0°C ~ +85°C 1 www.v-color.com.
Description V-Color Registered DDR4 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. FEATURES Power Supply: VDD=1.2V (1.14V to 1.26V) VDDQ = 1.2V (1.14V to 1.26V) VPP-2.5V (2.375V to 2.75V) VDDSPD=2.25V to 2.
DRAM Component Operating Temperature Range Symbol TOPER Parameter Normal Operating Temperature Range Rating Units Notes 0 to 85 °C 1,2 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
Pin Assignments Pin 1 Front Side Pin Label Pin NC 145 2 VSS 3 DQ4 4 5 6 VSS Back Side Pin Label Front Side Pin NC 74 146 VREFCA 147 VSS VSS 148 DQ5 DQ0 149 VSS 150 DQ1 151 VSS 78 TDQS9_C, DQS9_C 152 DQS0_c 9 VSS 153 10 DQ6 154 11 VSS 12 DQ2 13 14 15 16 VSS Pin Pin Label Back Side Pin Label CK0_t 218 75 CK0_c 219 CK1_c 76 VDD 220 VDD 77 VTT 221 VTT EVENT_n 222 PARITY 79 A0 223 VDD DQS0_t 80 VDD 224 BA1 VSS 81 BA0 225 A10/AP 155
Pin Front Side Pin Back Pin 37 PinVSS Label 181 DQ29 Side 108 38 DQ24 182 VSS 109 DQ25 110 Pin 39 VSS 183 Label 40 TDQS12_t, DQS12_t, Front Side Pin DQ40 Label VSS TDQS14_t, DQS14_t, Pin Back Side 252 Pin VSS Label 253 DQ41 254 VSS DM5_n, DBI5_n 184 VSS 111 TDQS14_c, DQS14_c 255 DQS5_C TDQS12_C, DQS12_C 185 DQS3_c 112 VSS 256 DQS5_t 42 VSS 186 DQS3_t 113 DQ46 257 VSS 43 DQ30 187 VSS 114 VSS 258 DQ47 44 VSS 188 DQ31 115 DQ42 259 VSS 45 DQ2
Pin Descriptions Pin Name A0-A171 Description Pin Name Register address input SCL Description I2C serial bus clock for SPD-TSE and register I2C serial data line for SPD-TSE and BA0, BA1 Regisiter bank select input BG0, BG1 Regisiter bank group select input SA0-SA2 RAS_n2 Register row address strobe input PAR and register Register parity input CAS_n3 Register column address strobe input VDD SDRAM core power supply WE_n4 Register write enable input C0, C1, C2 Chip ID lines for SDRAMx CS
Absolute Maximum Ratings Symbol Rating Units Notes Voltage on VDD pin relative to Vss - 0.3 V ~ 1.50 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss - 0.3 V ~ 1.50 V V 1,3 VPP Voltage on VPP pin relative to Vss - 0.3 V ~ 3.0 V V 4 - 0.3 V ~ 1.50 V V 1,3,5 -55 to +100 °C VDD Parameter VIN, VOUT Voltage on any pin except VREFCA relative to Vss TSTG Storage Temperature 1, 2 Notes: 1.
Standard Speed Bins DDR3-1600 Speed Bins and Operations Speed Bin DDR3-1600K CLnRCD-nRP Parameter 11-1111 Symbol Internal read command to first tAA data min Internal read command to first tAA_DBI NOTE 18.00 ns 11 tAA(max) +2nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns 13 13.75 (13.50) Unit max 5,11 tAA(min) + 2nCK data with read DBI enabled ACT to internal read or write tRCD delay time 13.75 (13.50) PRE command period tRP 13.75 (13.
DDR3-1866 Speed Bins and Operations Speed Bin DDR3-1866M CLnRCD-nRP Parameter 13-1313 Symbol Internal read command to first tAA data 13.92 (13.50) Internal read command to first tAA_DBI Unit NOTE 18.00 ns 11 tAA(max) +2nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns min max 13 5,11 tAA(min) + 2nCK data with read DBI enabled ACT to internal read or write delay tRCD time 13.92 (13.50) PRE command period tRP 13.92 (13.
DDR4-2133 Speed Bins and Operations Speed Bin DDR4-2133P CL-nRCDnRP 15-1515 Parameter Symbol Internal read command to first data tAA tAA_DBI NOTE 18.00 ns 11 tAA(max)+3nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 1.6 ns min 14.06 (13.50) Internal read command to first data Unit max 13 5,11 tAA(min)+3nCK with read DBI enabled ACT to internal read or write delay tRCD time 14.06 (13.50) PRE command period tRP 14.06 (13.
DDR4-2400 Speed Bins and Operations Speed Bin DDR4-2400T CL-nRCDnRP 17-1717 Parameter Symbol Internal read command to first data tAA tAA_DBI NOTE 18.00 ns 11 tAA(max)+3nCK ns 11 - ns 11 - ns 11 9 x tREFI ns 11 - ns 11 ns 1,2,3,4,10 ns 1,2,3,4,10 ns 4 <1.5 ns 1,2,3,4,8 <1.5 ns 1,2,3,8 ns 4 max 14.16 (13.75) Internal read command to first data Unit min 5,11 tAA(min)+3nCK with read DBI enabled ACT to internal read or write delay tRCD time 14.16 (13.
Speed Bin Table Notes Absolute Specification - VDDQ = VDD = 1.20V +/- 0.06 V - VPP = 2.5V +0.25/ -0.125 V - The values defined with above -mentioned table are DLL ON case. - DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled. 1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requir ementsfrom CL setting as well as requirements from CWL setting. 2. tCK(avg).
8. Any DDR4-2400 speed bin also supports functional operation at l ower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Pro duction Tests but verified by Design/Characterization. 10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. 11.
Timings used for IDD, IPP and IDDQ Measurement DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 11-1111 1313-13 1515-15 17-17-17 tCK 1.25 1.071 0.937 0.
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