VZ22Q LTE Module VZ22Q LTE module PCB layout guide Document Title Originator VZ22Q LTE module PCB layout guide Tony Huang Approval V0.1 Version 1.
VZ22Q LTE Module History Version V0.
VZ22Q LTE Module Content 1. INTRODUCTION .....................................................................................4 2. PCB DESIGN .............................................................................................5 2.1 2.2 2.3 3. PCB DESIGN GUIDE....................................................................................................... 5 DESIGN FOR PCB STACK-UP(RECOMMEND) .................................................................
VZ22Q LTE Module 1. Introduction This document introduces USI VZ22Q LTE Module and provides some advices and layout rules. Please comply with all rules as careful as possible, and module performance will be better and user’s cost will be reduced. V0.
VZ22Q LTE Module 2. PCB Design 2.1 PCB Design Guide i. Keep away high interference signal as far as possible. （Ex: clock, high frequency signal, switch, ...etc.） ii. RF and analog signals should be protected. If there is enough space, please divide ground plane into analog and digital part. NO SIGNALS WHATEVER is permitted to cross this gap. iii. Ensure power integrity and current capability, and using “Power plane” will be a good solution. iv. Ground integrity under module will reduce interference. v.
VZ22Q LTE Module 2.2 Design for PCB Stack-up(recommend) Using 4 layer stack-up design for PCB could reduce cost, and please refer to Table 2-1. Table 2-1. Example for Stack-up V0.
VZ22Q LTE Module 2.3 Recommended Package Dimension The pad size of PCB recommended is SMD(Solder mask define) . Figure 2-2: Recommended PCB footprint V0.
VZ22Q LTE Module 2.4 Pin define Pin Pin name NO. Function 1 GND GND 2 NETWORK_LED NETWORK indicator LED 3 1V8 IO reference power 4 Internal PU/PD PU Type Power domain O 1.8V O 1.8V USB_EXT_VBUS_VLD USB cable detection I 1.8V 5 FFF_FFH FFF/FFH mode select , High =FFF ,Low=FFH I 1.8V 6 ACTIVITY_LED ACTIVITY indicator LED O 1.8V 7 MODULE_ON_IND Module on indicator O 1.8V 8 HWID1 USB/HSIC/UART interface select pin1 I 1.
VZ22Q LTE Module Pin NO. Pin name Function Internal PU/PD Type Power domain 29 SDIO_HOST_D3 SDIO DATA 3 30 GND GND 31 GND GND 32 GND GND 33 GND GND 34 GND GND 35 PCM_RXD PCM receive data. I 1.8V 36 PCM_CLK PCM clock input, from 128kHz to 8192kHz O 1.8V 37 PCM_FS PCM frame synchroniztion at 8kHz O 1.8V 38 PCM_TXD PCM transmit data. O 1.
VZ22Q LTE Module Pin NO.
VZ22Q LTE Module Pin NO. Pin name Function 95 SQN3221_GPIO_21 General Purpose I/O,For customize. 96 WAKE_1 WAKE_1 Internal PU/PD Type Power domain 1V8 I 1V8 Min : 3.3V, 97 VCC1_PA VCC1 PA POWER INPUT I Mean : 3.8V, Max : 4.4V 98 VCC2_PA VCC2 PA POWER INPUT I Min : 0.5V, 99 VCC2_PA VCC2 PA POWER INPUT I Max : 3.6V 100 VCC_APT APT POWER OUTPUT O Min : 0.5V, 101 VCC_APT APT POWER OUTPUT O Max : 3.6V 102 VBAT_2 POWER INPUT For APT DC/DC I Min : 3.
VZ22Q LTE Module Pin NO. Pin name Function Internal PU/PD T17 GND GND X T18 GND GND X T19 GND GND X T20 GND GND X T21 GND GND X T22 GND GND X T23 GND GND X T24 GND GND X T25 GND GND X T26 GND GND X T27 GND GND X T28 GND GND X T29 GND GND X T30 GND GND X Type Power domain V0.
VZ22Q LTE Module 3. Power Design Power integrity is a key factor for performance of LGA module, and it might cause some issues as follows. i. EMC performance ii. Phase and sensitivity 3.1 Power Integrity i. Filter capacitors of power would be placed near the pads of module as close as possible. Especially, small capacitors should be the closest to pads. ii. Power traces should be designed as wide as possible. It is better to be designed by “plane” type if there is enough space. 3.2 Layout Rule 3.2.
VZ22Q LTE Module 4. RF Layout Design On PCB, all RF signal trace must be controlled its impedance of 50 ohm. Ground vias should be arranged uniformly in both side of RF trace. Impedance specifications normally depended on medium coefficient, trace width, and distance to ground plane. Please refer to the following to improve better performance. Figure 4-1. Microstrip Structure Figure 4-2.
VZ22Q LTE Module 4.1 Layout Rules i. Antenna trace must be controlled its impedance of 50 ohm. ii. RF trace must be as short as possible for better RF performance. (USI main antenna trace is about 1249mil, diversity antenna trace length is about 941mil) iii. Keep away from other signals and power switch area. iv. Surrounded by GND via and GND plane. v. The antenna connect PN is Murata MM4829-2702 Figure 4-3. Example for RF trace V0.
VZ22Q LTE Module 5. Audio Codec Layout Guide (TBD) To ensure maximum performance from the ALC5623 codec, Please refer to “Realtek realtekALC5623 Codec Layout Guide ver 0.1” for proper component placement and routing are very important. This document includes properly isolating the digital circuitry and analog circuitry.
VZ22Q LTE Module 5.2 Component Placement For a layout that helps to reduce noise, separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. In addition to ground planes scheme, digital and analog power supply planes should be partitioned directly over their respective ground planes.
VZ22Q LTE Module 5.3 Decoupling and Bypassing Capacitors Bypass capacitors on the PCB are used to short digital noise into ground. Commonly, codec generates noise when its internal digital circuitry turns currents on and off. These current changes arise in the power and ground pins for the related section of the codec. The goal is to force AC currents to flow in the shortest possible loop from the supply pin through the bypass cap and back into the codec through the nearby ground pin.
VZ22Q LTE Module i. To avoid a cross-talk issue result from having no enough space between channels or input/output traces. The cross-talk may interfere in analog signal, especially the MIC1P/MIC1N and MIC2P/MIC2N. In Figure 5-4, the isolation between LINE_IN_R/LINE_IN_L, and MIC1P/MIC1N are routing as wider as possible (L at least 60 mils). Figure 5-4. The routing for Analog Inputs (L>60 mils, D≦10 mils) ii. The MIC1P/MIC1N and MIC2P/MIC2N input signals are more sensitive than the other signals.
VZ22Q LTE Module LINE_IN_L/LINE_IN_R > 10 mils (15 mils is better) AUX_OUT/AUX_OUTN >10 mils (15mils is better) SPKOUT/ SPKOUTN > 20 mils (30 mils is better) iv. The signal length from codec to input/output connector should be as short as possible. v. The trace length difference between the differential signal (ex: MIC1P/N, SPK_OUT_R/ SPK_OUT_RN, ...etc) should be kept as small as possible. (better within 1 inch). vi. The width between differential pair should be small (D≦10 mils). vii.
VZ22Q LTE Module 6. USB Layout Design 6.1 Design & Layout Rule i. USB pair impedance: 90 ohm differential. ii. Avoid creating unnecessary stubs on data lines. If a stub is VZ22Q voidable (for example: ESD issue), please keep the stub as short as possible. Figure 6-1. Layout management iii. Keep away from other signals and power switch area. iv. Surrounded by GND plane. v. Recommend the length don’t exceed 4 inch. vi. The length tolerance between USB_D+& USB_D- is ± 10 mils. 6.2 Poor Routing i.
VZ22Q LTE Module 7. Layout Design of SIM Socket i. The trace of SIM socket should be as short as possible. Recommended maximum value is 10 cm. Relative signals should be arranged together. ii. The routing of SIM socket should follow the BUS routing. Notice the protection of the routing to avoid high frequency signal and interferences from clock, or it might take risk of SIM card restarting. iii.
VZ22Q LTE Module 8. Grounding i. The ground between module and main board should be well connected. ii. Good ground management could enhance module performance. It would ensure signal integrity, upgrade RF performance, reduce EMI, and cool down devices. iii. Notice structure of RF trace. Reference ground should be fully in side of the trace. iv. Audio and clock signals should be wrapped by ground to isolate the interference and sensitive signals. v.
