JODY-W3 series Host-based modules with Wi-Fi 6 and Bluetooth 5.3 System integration manual Abstract This document describes the system integration of JODY-W3 series modules. These host-based modules support concurrent dual-band Wi-Fi 802.11n/ac/ax and Bluetooth® 5.3 and are designed for both simultaneous and independent operations. JODY-W3 modules include an integrated MAC/baseband processor and RF front-end components of automotive grade. UBX-19011209 - R07 C2-Restricted www.u-blox.
JODY-W3 series - System integration manual Document information Title JODY-W3 series Subtitle Host-based modules with Wi-Fi 6 and Bluetooth 5.3 Document type System integration manual Document number UBX-19011209 Revision and date R07 Disclosure Restriction C2-Restricted 8-Aug-2022 Product status Corresponding content status Functional Sample Draft For functional testing. Revised and supplementary data will be published later.
JODY-W3 series - System integration manual Contents Document information ................................................................................................................................ 2 Contents .......................................................................................................................................................... 3 1 System description .......................................................................................................................
JODY-W3 series - System integration manual 2.4 Data communication interfaces ............................................................................................................28 2.4.1 PCI Express ........................................................................................................................................28 2.4.2 SDIO 3.0 ..............................................................................................................................................29 2.
JODY-W3 series - System integration manual 3.9.2 4 Runtime debug options ...................................................................................................................52 Handling and soldering ..................................................................................................................... 53 4.1 Special ESD handling precautions.........................................................................................................53 4.
JODY-W3 series - System integration manual 1 System description 1.1 Overview JODY-W3 series modules provide complete short range transceiver solutions that can be easily integrated into automotive and industrial applications. The modules are intended for the most advanced in-car infotainment and connectivity systems and deliver the highest data rates in Wi-Fi using advanced Wi-Fi 6 802.11ax technology. JODY-W3 series modules operate in concurrent dualbands, Wi-Fi 2.4 and 5 GHz, dual-MAC, and 2x2 MIMO.
JODY-W3 series - System integration manual Figure 1: JODY-W354 and JODY-W374 block diagram Commented [CT1]: In next update of this doc, rework this and similar diagrams using approved corporate colors, Hero, grey, etc. Figure 2 shows the block diagram for the JODY-W377 module variant. Commented [LB2R1]: This is copied from DS which is the “master” Commented [MZ3R1]: ROLLOVER Commented [CT4R1]: Revised Commented [LB5R1]: There’s a blob missing on the GPIO arrow.
JODY-W3 series - System integration manual General status Power state Description Deep sleep Used in power save modes. Table 2: Description for Wi-Fi power states 1.2 Pin configuration and function 1.2.
JODY-W3 series - System integration manual 1.2.2 Pin list Figure 3 and Table 3 show the pin-out of JODY-W3 series modules with the pins grouped by function. Figure 3: JODY-W3 series module pin assignments (top view) Function Pin name Power and ground SDIO host Type Description Active Power down 3V3 2 PWR 3.3 V power supply PWR - VIO 3 PWR 1.8 V or 3.3 V VIO supply PWR - 1V8 4 PWR 1.
JODY-W3 series - System integration manual Function Pin name Pin no. Power Type Description Active Power down interface1 SD_D2 50 1V8 I/O SDIO data line bit [2] I/O Tristate SD_D3 51 1V8 I/O SDIO data line bit [3] I/O Tristate 36 VIO O BT UART output signal. Connect to Host RX O Drive low 37 VIO I BT UART input signal. Connect to Host TX I Tristate BT_UART_RTS 38 VIO O BT UART request-to-send output signal.
JODY-W3 series - System integration manual Function Pin name Pin no. Power Type Description Active Power down See also Configuration pins. Same function as pin 10.
JODY-W3 series - System integration manual Function Pin name Pin no. Power Type Description Active Power down configuration CONFIG[1] 8 1V8 I Host interface configuration pin See also Configuration pins. I Tristate CONFIG[2] 6 1V8 I Host interface configuration pin See also Configuration pins.
JODY-W3 series - System integration manual Rail Allowable ripple (peak to peak)4 over DC supply Current consumption, peak 3V3 30 mVpk-pk 1500 mA5 Commented [MZ13R12]: Ripple Noise according DS: max. 30 mV 1V8 30 mVpk-pk 1900 mA5 Commented [CT14R12]: Outstanding? VIO 30 mVpk-pk 5 mA Commented [LB15R12]: This has not been verified but I suppose we can keep the values as target. Table 4: Summary of voltage supply requirements 1.3.
JODY-W3 series - System integration manual Commented [BL16]: VPA is voltage domain in 88W9098 on JODY this is 3V3 (VBAT). AVDD is 1V8 VCORE internal voltage Commented [MH17R16]: The right power-up sequence is UBX-19029 Figure 4: Power sequence of JODY-W3 module During the power up of JODY-W3 series modules, it is good practice to enable VIO first, followed by other supplies shortly thereafter.
JODY-W3 series - System integration manual Name I/O Description WL_HOST_WAKE I/O Wi-Fi Module-to-host wake-up signal (output) / GPIO[15] Used as configuration pin, see also Configuration pins. BT_HOST_WAKE I/O Bluetooth Module-to-host wake-up signal (output) / GPIO[16] Used as configuration pin, see also Configuration pins. Table 5: Wake-up signal definitions 1.4.5 Configuration pins JODY-W3 series modules support configuration pins to set specific parameters following a reset.
JODY-W3 series - System integration manual 1.5 Data communication interfaces JODY-W3 series modules support PCI express v2.0, SDIO 3.0 and high-speed UART host interfaces. This means that all Wi-Fi traffic is communicated through either PCIe or SDIO by setting the appropriate boot option. The high-speed UART interface between the host and the JODY-W3 series module is used for the Bluetooth traffic. For information about the available host interface configuration options, see also Configuration pins. 1.5.
JODY-W3 series - System integration manual Name I/O Description Power supply PCIE_PERST# I PCIe host indication to reset the device. Active low. Multiplexed with GPIO[20]. VIO PCIE_CLKREQ# OD PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated. 0 = the clock is required. Active low. An external pull-up resistor on host side is required. VIO PCIE_PME# OD PCI wake signal. Active low.
JODY-W3 series - System integration manual The PCM interface supports: • • • • Master and slave mode PCM bit width size of 8 bit or 16 bit Up to four slots with configurable bit width and start positions Short frame and long frame synchronization ☞ PCM pins are shared with the I2S interface and can be configured to I2S mode using HCI commands. Name I/O Description Remarks PCM_CLK I/O PCM clock Alternate function: I2S clock Master output. Slave input. Used as configuration pin.
JODY-W3 series - System integration manual 1.6 Coexistence interfaces 1.6.
JODY-W3 series - System integration manual 1.7.2 Approved antenna designs JODY-W3 modules come with a pre-certified antenna design that can be used to save cost and time during the certification process. To leverage this benefit, customers are required to implement an antenna layout that is fully compliant with the u-blox reference design outlined in this document. Reference design source files are available from u-blox on request.
JODY-W3 series - System integration manual 2 Design-in Follow the design guidelines stated in this chapter to optimize the integration of JODY-W3 series modules in the final application board. 2.1 Overview Although every application circuit must be properly designed, there are several points that require special attention during application design. A list of these points, in order of importance, follows: • • • • • Module antenna connection: ANT0, ANT1 and ANT2 pins.
JODY-W3 series - System integration manual 2.2.1 RF Transmission line design RF transmission lines, such as those that connect from ANT pins to their related antenna connectors, must be designed with a characteristic impedance of 50 . Figure 5 shows the design options and the most important parameters for designing a transmission line on a PCB: • • • Microstrip. A track separated with dielectric material and coupled to a single ground plane. Coplanar microstrip.
JODY-W3 series - System integration manual • • • • • • For PCBs with components larger than 0402 and dielectric thickness below 200 µm, add a keep-out, that is, some clearance (void area) on the ground reference layer below any pin on the RF transmission lines. This helps to reduce the parasitic capacitance to ground. Route RF lines in 45 ° angle and avoid acute angles. The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible.
JODY-W3 series - System integration manual • Integrated antennas, such as patch-like antennas: o Internal integrated antennas impose some physical restrictions on the PCB design: - Integrated antennas excite RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna; its dimension defines the minimum frequency that can be radiated.
JODY-W3 series - System integration manual Item Requirements Remarks Envelope Correlation Coefficient (ECC) ECC < 0.1 recommended ECC < 0.5 acceptable The ECC parameter correlates the far field parameters between antennas in the same system. A low ECC parameter is fundamental in improving the performance of MIMO-based systems. Table 17: Summary of Wi-Fi/Bluetooth coexistence requirements ⚠ When operating dual antennas in the same 2.
JODY-W3 series - System integration manual Consider that SMT connectors are typically rated for a limited number of insertion cycles. In addition, the RF coaxial cable may be relatively fragile compared to other types of cables. To increase application ruggedness, connect U.FL connector to a more robust connector such as SMA fixed on panel.
JODY-W3 series - System integration manual • • • • It is highly recommended to strictly follow the specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and matching circuitry. Further to the custom PCB and product restrictions, antennas may require tuning/matching to reach the target performance.
JODY-W3 series - System integration manual • • Low output ripple: The switching regulator peak-to-peak Voltage ripple must not exceed the specified limits. This requirement applies both to voltage ripple generated by SMPS operating frequency and to high frequency noise generated by power switching. PWM/PFM mode operation: It is preferable to select regulators with fixed Pulse Width Modulation (PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and may affect RF performance.
JODY-W3 series - System integration manual Signal Group Parameter Min. PCIe differential data Single Ended impedance, 𝑍𝑆𝐸 60 Typ. Unit Ω Differential impedance, 𝑍𝑑𝑖𝑓𝑓 100 Common mode impedance, 𝑍𝐶𝑀 50 Impedance control, 𝑍𝑆𝐸 , 𝑍𝑑𝑖𝑓𝑓 , 𝑍𝐶𝑀 Max.
JODY-W3 series - System integration manual Signal Group Parameter Min. Typ. Max. Unit CMD Pull-Up range, Rcmd 10 10 50 kΩ CLK, CMD, DAT[0:3] Series termination (Host side), Rterm9 0 0 CLK, CMD, DAT[0:3] Bus length10 CMD, DAT[0:3] Bus skew length mismatch to CLK -3 CLK Center to center CLK to other SDIO signals11 4*W CMD, DAT[0:3] Center to center between signals11 3*W Ω 100 mm +3 mm Table 20: SDIO bus requirements ☞ JODY-W3 series supports only 1.8 V SDIO signal voltage.
JODY-W3 series - System integration manual ☞ The HCI command complete event is generated at the old baud rate. Once the host receives the command complete at the old baud rate, it can switch to the new baud rate and should wait for 5 ms or more before sending any new command. Commented [CT42]: Ambiguous. See earlier comment ^ Is this referring to the “hcitool” command given in the example. 2.
JODY-W3 series - System integration manual • • • • • • • ⚠ It is strongly recommended to avoid digital routing beneath all layers of RF traces. Ground cuts or separation are not allowed below the module. Minimize the length of the RF traces as first priority. Then, minimize bus length to reduce potential EMI issues from digital busses. All traces (Including low speed or DC traces) must couple with a reference plane (GND or power), Hi-speed busses should be referenced to the ground plane.
JODY-W3 series - System integration manual Figure 10 shows the pin layout for the JODY-W3 series module. The proposed land pattern layout reflects the pin layout of the module. Both Solder Mask Defined (SMD) and Non Solder Mask Defined (NSMD) pins can be used, however the following considerations apply: • • • • Pins 1 to 94 should be NSMD Inner pads must have a good thermal bonding to PCB ground planes to help spreading the heat generated by the module.
JODY-W3 series - System integration manual • • • • Ground vias density under the module: 50 𝑣𝑖𝑎𝑠/𝑐𝑚2 , thermal vias can be placed in gaps between the thermal pads of the module. Minimum layer count and copper thickness: 4 𝑙𝑎𝑦𝑒𝑟𝑠, 35 𝜇𝑚. Minimum board size: 55𝑥70 𝑚𝑚. Power planes and signal traces should not cross the layers beneath the module to maximize heat flow from the module. Those recommendations allow the design to achieve a thermal characterization parameter of ψ𝐽𝐵 = 7.
JODY-W3 series - System integration manual Table 24: Minimum ESD immunity requirements based on EN 61000-4-2 Compliance with standard protection level as specified in EN 61000-4-2 [4] can be achieved by including proper ESD protection in parallel to the line and close to areas that are accessible to the end user. ⚠ Special care should be taken if the ANT pins must be protected by choosing an ESD absorber with adequate parasitic capacitance.
JODY-W3 series - System integration manual 3 Software The instructions in this chapter describe how to set up the JODY-W3 series module on a Linux operating system. Including several examples, it also describes how the reference driver packages are compiled and deployed in the target system. The described configuration is based on the proprietary driver for the 88Q9098 chipset family from NXP that has been integrated onto an i.MX 8QuadMax Multisensory Enablement Kit (MEK) from NXP.
JODY-W3 series - System integration manual The proprietary NXP driver package is currently available for the PCIE-UART host interface combination (PCIE-WLAN-UART-BT-9098), which uses the PCIe interface to operate Wi-Fi and the UART interface for Bluetooth.
JODY-W3 series - System integration manual 3.4 Software architecture From the software point of view, JODY-W3 series modules contain only on-board OTP memory with calibration parameters and MAC addresses. Consequently, the modules require a host-side driver and device firmware to run. At startup and at every reset or power cycle, the host driver needs to download the firmware binary file to the module. The host driver interfaces the bus drivers with the upper layer protocol stacks of the operating system.
JODY-W3 series - System integration manual Figure 13 shows the basic architecture of the Wi-Fi driver. Commented [MZ74]: Top right box should be “uaputl/mlanutl/iw/iwconfig” -TCP instead of TCIP -“Common driver interface” – it’s not a driver, but an interface for drivers -Bottom half resides in WLAN firmware, not Host driver -Box above HAL should be “WLAN driver” Commented [CT75R74]: Fixed Figure 13: Basic Wi-Fi host driver and firmware architecture 3.4.
JODY-W3 series - System integration manual The architecture of the Bluetooth driver and protocol stack is shown in Figure: 14. Figure: 14: Bluetooth driver and protocol stack 3.5 Compiling the drivers The README files included in the driver package contain basic steps of the compilation procedure. ☞ 3.5.1 The recipes in the Yocto/OpenEmbedded meta layer provided by u-blox are used to integrate the software package into Yocto projects.
JODY-W3 series - System integration manual Using the Yocto recipes provided by u-blox, the utilities and modules typically install like this: \ ├── │ │ ├── │ │ │ │ │ │ │ │ │ │ │ │ │ │ └── etc └── modprobe.d └── jody-w3-driver-pcieuart.conf lib ├── firmware │ └── nxp │ └── jody-w3-pcieuart │ ├── pcie9098_wlan_v1.bin │ ├── pcieuart9098_combo_v1.bin │ └── uart9098_bt_v1.bin └── modules └── 4.14.98-imx[…] └── updates └── nxp └── 88q9098 ├── hci_uart_jody-w3-pcieuart.ko ├── mlan_jody-w3-pcieuart.
JODY-W3 series - System integration manual Application Functionality mlanutl Features and configuration related to station mode in Wi-Fi uaputl Features and configuration related to AP mode in Wi-Fi Table 28: Utilities to configure Wi-Fi modes 3.6.3 Additional software requirements Although the NXP configuration utilities provide the necessary interface to configure features at granular levels, most product vendors prefer open-source applications and stacks.
JODY-W3 series - System integration manual 3.8 Runtime usage This section describes how to load specific drivers in different modes and configurations. It also provides examples for operating the module in several typical use-cases, such as station, accesspoint, and so on. 3.8.1 Device detection Prior to loading the drivers, make sure that the JODY-W3 series module is detected by the host system. ☞ PD# must not be asserted to enable the JODY-W3 series module.
JODY-W3 series - System integration manual The following log example shows the firmware request and loading operation of the PCIe driver. [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 187.830477] 187.995594] 188.000731] 188.007113] 188.012991] 188.017477] 188.020672] 188.033816] 188.706540] 190.221805] 190.238578] 190.242184] 190.247849] 190.290702] 190.302365] 190.308754] 190.314760] 190.319228] 190.322577] 190.349922] 190.358426] 190.363722] 190.380792] 190.384298] 190.389942] 190.401149] 190.
JODY-W3 series - System integration manual [ [ [ [ [ [ [ [ [ [ 17.257260] 17.330706] 17.337810] 17.358325] 17.376908] 17.426684] 17.434397] 17.440017] 17.482183] 17.490179] WLAN FW is active wlan: version = SD9098---17.68.0.p159-MXM4X17153-GPL-(FP68) vendor=0x02DF device=0x914E class=0 function=2 Attach moal handle ops, card interface type: 0x106 Attach mlan adapter operations.card_type is 0x106. Request firmware: mrvl/sd9098_wlan_v1_jody-w3-sdio.
JODY-W3 series - System integration manual type managed phy#0 Interface wfd0 addr 02:50:43:02:fe:01 type managed Interface uap0 addr 00:50:43:02:00:01 type AP Interface mlan0 addr 00:50:43:02:fe:01 type managed Table 31 describes the functions of the Wi-Fi interfaces. Interface MAC/PHY Function mlan0 1 Network interface used for station mode functionality. Can be configured using mlanutl. uap0 1 Network interface used for access-point functionality. Can be configured using uaputl.
JODY-W3 series - System integration manual In the following example, the MAC addresses of the Wi-Fi interfaces have been changed in the init_cfg.conf file. The changes have been implemented to meet the application requirements so that each interface is assigned with a unique MAC address to avoid conflicts. The addresses are assigned to the uap0 and muap0 interfaces. # File: /lib/firmware/nxp/init_cfg.
JODY-W3 series - System integration manual vht_oper_chwidth=1 vht_oper_centr_freq_seg0_idx=42 ieee80211ax=1 he_su_beamformer=1 he_bss_color=1 he_oper_chwidth=1 he_oper_centr_freq_seg0_idx=42 eapol_version=1 wpa_key_mgmt=WPA-PSK wpa=2 rsn_pairwise=CCMP wpa_passphrase=1234567890 The access point is started with the command: hostapd hostapd_ax5g.conf -B ☞ Use the command with the options -dddt to generate detailed log files for debugging purpose. A hostapd configuration file example for 802.
JODY-W3 series - System integration manual The following commands set up the 5 GHz 802.
JODY-W3 series - System integration manual # he capability id 23 # HE MAC capability info 00 00 00 82 00 08 # HE PHY capability info, first byte 04: 80MHz, 02: 20MHz 04 70 7e c9 fd 01 a0 0e 03 3d 00 # Tx Rx HE-MCS NSS support fa ff fa ff # PPE Thresholds (optional) # PE: 16 us e1 ff c7 71 [/HECap] While starting the access point on 4.x kernel, use the following mlanutl command with respective configuration file before starting the access point: mlanutl uap0 11axcfg config/11axcfg_80-2x2.conf 3.8.
JODY-W3 series - System integration manual 3.8.8 ☞ Bluetooth usage Once the Bluetooth drivers are loaded for the UART interface, it is necessary to bind the serial interface to the Bluetooth stack. For this, use the hciattach tool in the BlueZ package. The following code snippet shows how to attach to BlueZ through the /dev/ttyUSB0 serial device. In the example below, Bluetooth is connected to the host using USB cable connected through FTDI. $ hciattach /dev/ttyUSB0 any 3000000 flow [ 442.
JODY-W3 series - System integration manual 3.9 Driver debugging Driver debugging is provided through the kernel print function printk and the proc file system. Driver states are recorded and are retrieved through the proc file system during runtime.
JODY-W3 series - System integration manual 4 ⚠ Handling and soldering JODY-W3 series modules are Electrostatic Sensitive Devices that demand the observance of precautions against electrostatic discharge. Failure to observe precautions can result in severe damage to the product. Standard ESD safety practices must be applied. Figure 15: Standard workstation setup for safe handling of ESD-sensitive devices 4.
JODY-W3 series - System integration manual 4.3 Reflow soldering process JODY-W3 series modules are surface mounted devices supplied on a multi-layer FR4-type PCB with gold-plated connection pads. The modules are produced in a lead-free process using lead-free soldering paste. The thickness of solder resist between the host PCB top side and the bottom side of JODY-W3 series modules must be considered for the soldering process.
JODY-W3 series - System integration manual 4.3.1 Cleaning Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. • • • Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pins.
JODY-W3 series - System integration manual 5 Regulatory compliance 5.1 General requirements JODY-W3 series modules are designed to comply with the regulatory demands of Federal Communications Commission (FCC), Innovation, Science and Economic Development Canada (ISED)20 and the CE mark21. This section contains instructions on the process needed for an integrator when including the JODY-W3 module into an end-product.
JODY-W3 series - System integration manual The evaluation of the end product shall be performed with the JODY-W3 module installed and operating in a way that reflects the intended end product use case. The upper frequency measurement range of the end product evaluation is the 10th harmonic of 5.8 GHz as described in KDB 996369 D04.
JODY-W3 series - System integration manual ☞ ⚠ For modules where the FCC ID / ISED certification ID is printed on the label, the integrator must replace the module’s label with a new label containing the new FCC/ISED ID. For more information about the labeling requirements, see also the JODY-W3 series data sheet [1]. It is the responsibility of the integrator to comply with any upcoming regulatory requirements. 5.2.
JODY-W3 series - System integration manual • • • • • • The configuration of the modular transmitter when installed into the host product must be within the authorization of the modular transmitter at all times and cannot be changed to include unauthorized modes of operation through accessible interfaces of the host product. The Wi-Fi Tx output power limits must be followed.
JODY-W3 series - System integration manual Channel number Channel center frequency [MHz] Allowed channels 1 – 11 2412 – 2462 Yes 12 – 13 2467 – 2472 No 36 – 48 5180 – 5240 Yes 52 – 64 5260 – 5320 Yes23 100 – 116 5500 – 5580 Yes2324 120 – 128 5600 – 5640 No 132 – 144 5660 – 5720 Yes2324 149 – 165 5745 – 5825 Yes Remarks Canada (ISED): Devices are restricted to indoor operation only and the end product must be labelled accordingly.
JODY-W3 series - System integration manual 5.2.6 End product labeling requirements For an end-product using the JODY-W3, there must be a label containing, at least, the following information: This device contains FCC ID: (XYZ)(UPN) IC: (CN)-(UPN) (XYZ) represents the FCC "Grantee Code", this code may consist of Arabic numerals, capital letters, or other characters, the format for this code will be specified by the Commission's Office of Engineering and Technology24.
JODY-W3 series - System integration manual In case, where the final product will be installed in locations where the end-consumer is unable to see the FCC/ISED ID and/or this statement, the FCC/ISED ID and the statement shall also be included in the end-product manual. 5.3 CE End-product regulatory compliance 5.3.1 Safety standard In order to fulfill the safety standard EN 60950-1 [8], the JODY-W3 module must be supplied with a Class-2 Limited Power Source. 5.3.
JODY-W3 series - System integration manual Linx ANT-2.4-CW-RCT-RP Single-band dipole antenna 2.
JODY-W3 series - System integration manual 6 Product testing 6.1 u-blox in-line production testing As part of our focus on high quality products, u-blox maintain stringent quality controls throughout the production process. This means that all units in our manufacturing facilities are fully tested and that any identified defects are carefully analyzed to improve future production quality.
JODY-W3 series - System integration manual 6.2 OEM manufacturer production test As all u-blox products undergo thorough in-line production testing prior to delivery, OEM manufacturers do not need to repeat any firmware tests or measurements that might otherwise be necessary to confirm RF performance. Testing over analog and digital interfaces is also unnecessary during an OEM production test.
Appendix A Reference schematic Figure 18: JODY-W3 reference schematic UBX-19011209 - R07 C2-Restricted Appendix Page 66 of 71
B Glossary Abbreviation Definition AEC Automotive Electronics Council AP Access Point API Application Programming Interface ATE Automatic Test Equipment BT Bluetooth CDM Charged Device Model CE European Conformity CLI Command Line Interface CTS Clear to Send DC Direct Current DDR Double Data Rate DFS Dynamic Frequency Selection DHCP Dynamic Host Configuration Interface EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read-Only Memory EIRP Equivalent Isotropic
Abbreviation Definition PHY Physical layer (of the OSI model) PMU Power Management Unit RF Radio Frequency RSDB Real Simultaneous Dual Band RST Request to Send SDIO Secure Digital Input Output SMD Solder Mask Defined SMPS Switching Mode Power Supply SMT Surface-Mount Technology SSID Service Set Identifier STA Station TBD To be Decided THT Through-Hole Technology UART Universal Asynchronous Receiver-Transmitter VCC IC power-supply pin VIO Input offset voltage VSDB Virtual S
C Wi-Fi transmit output power limits Pending.
Related documents [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] ☞ JODY-W3 series data sheet, UBX-19010615 Product packaging guide, UBX-14001652 u-blox Limited Use License Agreement, LULA-M IEC EN 61000-4-2 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test ETSI EN 301 489-1 - Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and
Revision history Revision Date Name Comments RO1 5-June-2020 lber, mzes Initial release. R02 26-Aug-2020 lber, mzes Updated reference schematic in Appendix A. Fixed PCIe signal descriptions in Table 10Table 13. R03 29-Jan-2021 lber, mzes Added professional grade product variants JODY-W374 and JODY-W377. Updated pin list and descriptions in Table 4. Corrected configuration pins in Table 7. Added section 1.4.6 Sleep clock. Added GPIO usage in section 1.7.2. Marked SDIO-SDIO support pending.
