LARA-R2 series LTE Cat 1 / EGPRS modules System Integration Manual Abstract This document describes the features and the system integration of LARA-R2 series multi-mode cellular modules. These modules are a complete, cost efficient and performance optimized LTE Cat 1 / 2G multi-mode solution covering up to three LTE bands and up to two 2G GSM/EGPRS bands in the very small and compact LARA form factor. . www.u-blox.
LARA-R2 series - System Integration Manual Document Information Title LARA-R2 series Subtitle LTE Cat 1 / EGPRS modules Document type System Integration Manual Document number UBX-16010573 Revision, date R02 Document status Objective Specification 03-Oct-2016 Document status explanation Objective Specification Document contains target values. Revised and supplementary data will be published later. Advance Information Document contains data based on early testing.
LARA-R2 series - System Integration Manual Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development. AT Commands Manual: This document provides the description of the AT commands supported by the u-blox cellular modules.
LARA-R2 series - System Integration Manual Contents Preface ................................................................................................................................ 3 Contents.............................................................................................................................. 4 1 System description ....................................................................................................... 7 1.1 1.2 Overview .....................................
LARA-R2 series - System Integration Manual 1.14.8 1.14.9 2 SSL/TLS ........................................................................................................................................ 56 Bearer Independent Protocol ....................................................................................................... 57 1.14.10 AssistNow clients and GNSS integration ................................................................................... 57 1.14.11 1.14.
LARA-R2 series - System Integration Manual 3 Handling and soldering ........................................................................................... 126 3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 126 3.2 Handling ........................................................................................................................................... 126 3.3 Soldering ...........................................
LARA-R2 series - System Integration Manual 1 System description 1.1 Overview The LARA-R2 series comprises LTE Cat 1 / 2G multi-mode modules supporting up to three LTE bands and up to two 2G GSM/(E)GPRS bands for voice and/or data transmission in the very small LARA LGA form-factor (26.0 x 24.
LARA-R2 series - System Integration Manual Table 2 reports a summary of cellular radio access technologies characteristics of LARA-R2 series modules. 4G LTE 2G GSM/GPRS/EDGE 3GPP Release 9 Long Term Evolution (LTE) Evolved Uni.
LARA-R2 series - System Integration Manual 1.2 Architecture Figure 1 summarizes the internal architecture of LARA-R2 series modules. Duplexer ANT1 Switch Filters Filters LNAs Filters PAs Filters ANT_DET SIM 26 MHz DDC(I2C) Duplexer LNAs Filters Filters LNAs Filters Filters LNAs Filters Filters ANT2 PAs SDIO RF transceiver UART Memory Cellular Base-band processor Switch 32.
LARA-R2 series - System Integration Manual Baseband and power management section The Baseband and Power Management section is composed of the following main elements: A mixed signal ASIC, which integrates Microprocessor for control functions DSP core for cellular Layer 1 and digital processing of Rx and Tx signal paths Memory interface controller Dedicated peripheral blocks for control of the USB, SIM and generic digital interfaces Interfaces to RF transceiver ASIC Memory system, which includes NAND
LARA-R2 series - System Integration Manual 1.3 Pin-out Table 3 lists the pin-out of the LARA-R2 series modules, with pins grouped by function. Function Pin Name Pin No I/O Description Remarks Power VCC 51, 52, 53 I Module supply input VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes. See section 1.5.1 for description and requirements. See section 2.2.1 for external circuit design-in.
LARA-R2 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks SIM VSIM 41 O SIM supply output VSIM = 1.8 V / 3 V output as per the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_IO 39 I/O SIM data Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_CLK 38 O SIM clock 3.
LARA-R2 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks USB VUSB_DET 17 I USB detect input VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in.
LARA-R2 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks SDIO SDIO_D0 47 I/O SDIO serial data [0] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_D1 49 I/O SDIO serial data [1] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.
LARA-R2 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks GPIO GPIO1 16 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in. GPIO2 23 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.12 for functional description. See section 2.8 for external circuit design-in. GPIO3 24 I/O GPIO 1.
LARA-R2 series - System Integration Manual 1.4 Operating modes LARA-R2 series modules have several operating modes. The operating modes defined in Table 4 and described in detail in Table 5 provide general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode Power-Off Mode VCC supply not present or below operating range: module is switched off. VCC supply within operating range and module is switched off.
LARA-R2 series - System Integration Manual Mode Description Transition between operating modes Active The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.3, 1.9.1.4 and to the u-blox AT Commands Manual [2]). When the module is switched on by an appropriate power-on event (see 2.3.1), the module enters active-mode from not-powered or power-off mode.
LARA-R2 series - System Integration Manual 1.5 Supply interfaces 1.5.1 Module supply input (VCC) The modules must be supplied via the three VCC pins that represent the module power supply input.
LARA-R2 series - System Integration Manual 1.5.1.1 VCC supply requirements Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6. VCC supply circuit affects the RF compliance of the device integrating LARA-R2 series modules with applicable required certification schemes as well as antenna circuit design.
LARA-R2 series - System Integration Manual 1.5.1.2 VCC current consumption in 2G connected-mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network.
LARA-R2 series - System Integration Manual When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the 3GPP specifications the maximum Tx RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as can be in case of a 2G single-slot call.
LARA-R2 series - System Integration Manual 1.5.1.3 VCC current consumption in LTE connected-mode During an LTE connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation used in LTE radio access technology. The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.
LARA-R2 series - System Integration Manual 1.5.1.4 VCC current consumption in cyclic idle/active-mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, reducing current consumption.
LARA-R2 series - System Integration Manual 1.5.1.5 VCC current consumption in fixed active-mode (power saving disabled) Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle-mode whenever possible: the module remains in active-mode.
LARA-R2 series - System Integration Manual 1.5.2 RTC supply input/output (V_BCKP) The V_BCKP pin of LARA-R2 series modules connects the supply for the Real Time Clock (RTC) and Power-On internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 10.
LARA-R2 series - System Integration Manual 1.5.3 Generic digital interfaces supply output (V_INT) The V_INT output pin of the LARA-R2 series modules is connected to an internal 1.8 V supply with current capability specified in the LARA-R2 series Data Sheet [1]. This supply is internally generated by a switching stepdown regulator integrated in the Power Management Unit and it is internally used to source the generic digital I/O interfaces of the cellular module, as described in Figure 11.
LARA-R2 series - System Integration Manual 1.6 System function interfaces 1.6.1 Module power-on When the LARA-R2 series modules are in the not-powered mode (switched off, i.e. the VCC module supply is not applied), they can be switched on as following: Rising edge on the VCC input pins to a valid voltage for module supply: the modules switch on if the VCC supply is applied with a rise time of less than 10 ms from 2.1 V to 3.0 V, reaching a proper nominal voltage value within the VCC operating range.
LARA-R2 series - System Integration Manual Figure 13 shows the module power-on sequence from the not-powered mode, describing the following phases: The external supply is applied to the VCC module supply inputs, representing the start-up event. The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value. The PWR_ON and the RESET_N pins suddenly rise to high logic level due to internal pull-ups.
LARA-R2 series - System Integration Manual 1.6.2 Module power-off LARA-R2 series can be properly switched off by: AT+CPWROFF command (see u-blox AT Commands Manual [2]). The current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed. An abrupt under-voltage shutdown occurs on LARA-R2 series modules when the VCC module supply is removed.
LARA-R2 series - System Integration Manual Figure 14 describes the LARA-R2 series modules power-off sequence, properly started sending the AT+CPWROFF command, allowing storage of current parameter settings in the module’s non-volatile memory and a proper network detach, with the following phases: When the +CPWROFF AT command is sent, the module starts the switch-off routine. The module replies OK on the AT interface: the switch-off routine is in progress.
LARA-R2 series - System Integration Manual 1.6.3 Module reset LARA-R2 series modules can be properly reset (rebooted) by: AT+CFUN command (see the u-blox AT Commands Manual [2] for more details). This command causes an “internal” or “software” reset of the module, which is an asynchronous reset of the module baseband processor. The current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed: this is the proper way to reset the modules.
LARA-R2 series - System Integration Manual 1.7 Antenna interface 1.7.1 Antenna RF interfaces (ANT1 / ANT2) LARA-R2 series modules provide two RF interfaces for connecting the external antennas: The ANT1 represents the primary RF input/output for transmission and reception of LTE/3G/2G RF signals. The ANT1 pin has a nominal characteristic impedance of 50 and must be connected to the primary Tx / Rx antenna through a 50 transmission line to allow proper RF transmission and reception.
LARA-R2 series - System Integration Manual Item Requirements Remarks Impedance 50 nominal characteristic impedance Frequency Range See the LARA-R2 series Data Sheet [1] Return Loss S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable Efficiency > -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable The impedance of the antenna RF connection must match the 50 impedance of the ANT2 port.
LARA-R2 series - System Integration Manual 1.7.2 Antenna detection interface (ANT_DET) The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the u-blox AT Commands Manual [2] for more details on this feature.
LARA-R2 series - System Integration Manual 1.9 Data communication interfaces LARA-R2 series modules provide the following serial communication interfaces: UART interface: Universal Asynchronous Receiver/Transmitter serial interface available for the communication with a host application processor (AT commands, data communication, FW update by means of FOAT), for FW update by means of the u-blox EasyFlash tool and for diagnostic. (see section 1.9.1) USB interface: Universal Serial Bus 2.
LARA-R2 series - System Integration Manual All the functionalities supported by LARA-R2 series modules can be set and configured by AT commands: AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8] u-blox AT commands (for the complete list and syntax see the u-blox AT Commands Manual [2]) All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see u-blox AT Commands Manual [2], &K, +IFC, \Q AT commands): hardware, sof
LARA-R2 series - System Integration Manual 1.9.1.2 UART AT interface configuration The UART interface of LARA-R2 series modules is available as AT command interface with the default configuration described in Table 10 (for more details and information about further settings, see the u-blox AT Commands Manual [2]).
LARA-R2 series - System Integration Manual CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is enabled (data can be sent and received). The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART (see 1.9.1.4 for more details).
LARA-R2 series - System Integration Manual DTR signal behavior The DTR module input line is set by default to the OFF state (high level) at UART initialization. The module then holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status can be changed by AT command (for more details, see u-blox AT Commands Manual [2], AT&D command description).
LARA-R2 series - System Integration Manual RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from the OFF state to the ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 17), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call.
LARA-R2 series - System Integration Manual 1.9.1.4 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description, see u-blox AT Commands Manual [2]). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, and otherwise the active-mode is maintained by the module (see section 1.4 for definition and description of module operating modes referred to in this section).
LARA-R2 series - System Integration Manual AT+UPSV HW flow control RTS line DTR line Communication during idle-mode and wake up 3 Enabled (AT&K3) ON ON 3 Enabled (AT&K3) ON OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE. Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE.
LARA-R2 series - System Integration Manual set from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s). Every subsequent character received during the active-mode, resets and restarts the timer; hence the active-mode duration can be extended indefinitely.
LARA-R2 series - System Integration Manual Wake up via data reception The UART wake up via data reception consists of a special configuration of the module TXD input line that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In particular, the UART is enabled and the module switches from the low power idle-mode to active-mode within ~20 ms from the first character received: this is the system “wake up time”.
LARA-R2 series - System Integration Manual The “wake-up via data reception” feature cannot be disabled. 11 In command mode , with “wake-up via data reception” enabled and autobauding enabled, the DTE should always send a dummy character to the module before the “AT” prefix set at the beginning of each command line: the first dummy character is ignored if the module is in active-mode, or it represents the wake-up character if the module is in low power idle-mode.
LARA-R2 series - System Integration Manual 1.9.2 USB interface 1.9.2.1 USB features LARA-R2 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate, representing the main interface for transferring high speed data with a host application processor, supporting: AT command mode Data mode and Online command mode FW upgrades by means of the FOAT feature (see 1.14.
LARA-R2 series - System Integration Manual Then, after a time period (which depends on the host / device enumeration timings), the VID and PID are updated to the ones related to the default USB profile providing the following set of USB functions: 6 CDC-ACM modem COM ports enumerated as follows: o o USB1: AT and data USB2: AT and data o USB3: AT and data o o USB4: GNSS tunneling USB5: SAP (SIM Access Profile) o USB6: Primary Log (diagnostic purpose) VID and PID of this USB profile with the set o
LARA-R2 series - System Integration Manual 1.9.2.2 USB in Windows USB drivers are provided for Windows operating system platforms and should be properly installed / enabled by following the step-by-step instructions available in the EVK-R2xx User Guide [3] or in the Windows Embedded OS USB Driver Installation Application Note [4]. USB drivers are available for the following operating system platforms: Windows 7 Windows 8 Windows 8.1 Windows 10 Windows Embedded CE 6.
LARA-R2 series - System Integration Manual 1.9.3 HSIC interface The HSIC interface is not supported by “02” modules product versions except for diagnostic purpose. 1.9.3.1 HSIC features LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with maximum 480 Mb/s data rate according to the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10] and USB Specification Revision 2.0 [9]. The module itself acts as a device and can be connected to any compatible host.
LARA-R2 series - System Integration Manual 1.9.4 DDC (I2C) interface 2 Communication with u-blox GNSS receivers over I C bus compatible Display Data Channel interface, ® AssistNow embedded GNSS positioning aiding, CellLocate positioning through cellular info, and custom functions over GPIOs for the integration with u-blox positioning chips / modules are not supported by LARA-R2 series modules “02” product versions.
LARA-R2 series - System Integration Manual The RTC synchronization signal to the GNSS receiver: “GNSS RTC sharing” function provided by GPIO4 improves GNSS receiver performance, decreasing the Time To First Fix (TTFF), and thus allowing to calculate the position in a shorter time with higher accuracy.
LARA-R2 series - System Integration Manual 1.10 Audio interface Audio is not supported by LARA-R204 module “02” product version. 1.10.
LARA-R2 series - System Integration Manual 1.11 Clock output LARA-R2 series modules provide master digital clock output function on GPIO6 pin, which can be configured to provide a 13 MHz or 26 MHz square wave. This is mainly designed to feed the master clock input of an external audio codec, as the clock output can be configured in “Audio dependent” mode (generating the square wave only when the audio path is active), or in “Continuous” mode.
LARA-R2 series - System Integration Manual 1.14 System features 1.14.1 Network indication GPIOs can be configured by the AT command to indicate network status (for further details see section 1.12 and to u-blox AT Commands Manual [2], GPIO commands): No service (no network coverage or not registered) Registered 2G / LTE home network Registered 2G / LTE visitor network (roaming) Call enabled (RF data transmission / reception) 1.14.
LARA-R2 series - System Integration Manual 1.14.4 Dual stack IPv4/IPv6 LARA-R2 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel. For more details about dual stack IPv4/IPv6 see the u-blox AT Commands Manual [2]. 1.14.5 TCP/IP and UDP/IP LARA-R2 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured, established and handled via the data connection management packet switched data commands.
LARA-R2 series - System Integration Manual 1.14.8 SSL/TLS LARA-R2 series modules support the Secure Sockets Layer (SSL) / Transport Layer Security (TLS) with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols.
LARA-R2 series - System Integration Manual Algorithm MD5 SHA/SHA1 NO YES SHA256 YES YES SHA384 Table 17: Message digest Description Registry value TLS_RSA_WITH_AES_128_CBC_SHA TLS_RSA_WITH_AES_128_CBC_SHA256 0x00,0x2F 0x00,0x3C YES YES TLS_RSA_WITH_AES_256_CBC_SHA TLS_RSA_WITH_AES_256_CBC_SHA256 0x00,0x35 0x00,0x3D YES YES TLS_RSA_WITH_3DES_EDE_CBC_SHA TLS_RSA_WITH_RC4_128_MD5 0x00,0x0A 0x00,0x04 YES NO TLS_RSA_WITH_RC4_128_SHA 0x00,0x05 NO TLS_PSK_WITH_AES_128_CBC_SHA TLS_PSK_WITH_AES_2
LARA-R2 series - System Integration Manual 1.14.11 Hybrid positioning and CellLocate® ® Hybrid positioning and CellLocate are not supported by “02” product versions. Although GNSS is a widespread technology, its reliance on the visibility of extremely weak GNSS satellite signals means that positioning is not always possible.
LARA-R2 series - System Integration Manual ® 3. If a new device reports the observation of Cell A CellLocate is able to provide the estimated position from the area of visibility 4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of visibility. ® ® CellLocate is implemented using a set of two AT commands that allow configuration of the CellLocate service (AT+ULOCCELL) and requesting position according to the user configuration (AT+ULOC).
LARA-R2 series - System Integration Manual 2 The use of hybrid positioning requires a connection via the DDC (I C) bus between the cellular modules and the u-blox GNSS receiver (see section 2.6.4). See GNSS Implementation Application Note [22] for the complete description of the feature. ® u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate server u-blox is unable to track the SIM used or the specific device. 1.14.
LARA-R2 series - System Integration Manual 1.14.15 Smart temperature management Cellular modules – independently from the specific model – always have a well-defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/is not air circulating, etc.
LARA-R2 series - System Integration Manual Figure 24 shows the flow diagram implemented for the Smart Temperature Supervisor.
LARA-R2 series - System Integration Manual Threshold definitions When the application of cellular module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the cellular module (Ti, internal).
LARA-R2 series - System Integration Manual 2 Design-in 2.1 Overview For an optimal integration of LARA-R2 series modules in the final application board follow the design guidelines stated in this section. Every application circuit must be properly designed to guarantee the correct functionality of the related interface, however a number of points require higher attention during the design of the application device.
LARA-R2 series - System Integration Manual 2.2 Supply interfaces 2.2.1 Module supply (VCC) 2.2.1.1 General guidelines for VCC supply circuit selection and design All the available VCC pins have to be connected to the external supply minimizing the power loss due to series resistance.
LARA-R2 series - System Integration Manual the typical choice when the charging source has a relatively low nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a proper charger / regulator with integrated power path management function can be selected to supply the module while simultaneously and independently charging the battery. See sections 2.2.1.
LARA-R2 series - System Integration Manual Figure 26 and the components listed in Table 19 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering to VCC pins the specified maximum peak / pulse current, with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz.
LARA-R2 series - System Integration Manual Figure 27 and the components listed in Table 20 show an example of a low cost power supply circuit, where the VCC module supply is provided by a step-down switching regulator capable of delivering to VCC pins the specified maximum peak / pulse current, transforming a 12 V supply input.
LARA-R2 series - System Integration Manual 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to a voltage value within the module VCC normal operating range.
LARA-R2 series - System Integration Manual Figure 29 and the components listed in Table 22 show an example of a low cost power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak / pulse current, with proper power handling capability. The regulator described in this example supports a limited input voltage range and it includes internal circuitry for current and thermal protection.
LARA-R2 series - System Integration Manual 2.2.1.
LARA-R2 series - System Integration Manual 2.2.1.6 Additional guidelines for VCC supply circuit design To reduce voltage drops, use a low impedance power source. The series resistance of the power supply lines (connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize power losses. Three pins are allocated for VCC supply. Several pins are designated for GND connection.
LARA-R2 series - System Integration Manual 2.2.1.
LARA-R2 series - System Integration Manual the module. Battery charging is completely managed by the STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.
LARA-R2 series - System Integration Manual suitable charger / regulator with integrated power path management function to supply the module and the whole device while simultaneously and independently charging the battery. Figure 33 reports a simplified block diagram circuit showing the working principle of a charger / regulator with integrated power path management function. This component allows the system to be powered by a permanent primary supply source (e.g.
LARA-R2 series - System Integration Manual Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for the application Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively reduced until the charge termination is done.
LARA-R2 series - System Integration Manual 2.2.1.10 Guidelines for removing VCC supply As described in section 1.6.2 and Figure 14, the VCC supply can be removed after the end of LARA-R2 series modules internal power-off sequence, which has to be properly started sending the AT+CPWROFF command (see u-blox AT Commands Manual [2]). Removing the VCC power can be useful in order to minimize the current consumption when the LARA-R2 series modules are switched off.
LARA-R2 series - System Integration Manual 2.2.1.11 Guidelines for VCC supply layout design Good connection of the module VCC pins with DC supply source is required for correct RF performance. Guidelines are summarized in the following list: All the available VCC pins must be connected to the DC source. VCC connection must be as wide as possible and as short as possible. Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be avoided.
LARA-R2 series - System Integration Manual 2.2.2 RTC supply (V_BCKP) 2.2.2.1 Guidelines for V_BCKP circuit design LARA-R2 series modules provide the V_BCKP RTC supply input/output, which can be mainly used to: Provide RTC back-up when VCC supply is removed If RTC timing is required to run for a time interval of T [s] when VCC supply is removed, place a capacitor with a nominal capacitance of C [µF] at the V_BCKP pin.
LARA-R2 series - System Integration Manual Combining a LARA-R2 series cellular module with a u-blox GNSS positioning receiver, the positioning receiver VCC supply is controlled by the cellular module by means of the “GNSS supply enable” function provided by the GPIO2 of the cellular module.
LARA-R2 series - System Integration Manual 2.2.3 Interface supply (V_INT) 2.2.3.1 Guidelines for V_INT circuit design LARA-R2 series provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly used to: Indicate when the module is switched on (see sections 1.6.1, 1.6.2 for more details) Pull-up SIM detection signal (see section 2.5 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see section 2.6.
LARA-R2 series - System Integration Manual 2.3 System functions interfaces 2.3.1 Module power-on (PWR_ON) 2.3.1.1 Guidelines for PWR_ON circuit design LARA-R2 series modules’ PWR_ON input is equipped with an internal active pull-up resistor to the VCC module supply as described in Figure 37: an external pull-up resistor is not required and should not be provided. If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device.
LARA-R2 series - System Integration Manual 2.3.2 Module reset (RESET_N) 2.3.2.1 Guidelines for RESET_N circuit design LARA-R2 series RESET_N is equipped with an internal pull-up to the V_BCKP supply as described in Figure 38. An external pull-up resistor is not required. If connecting the RESET_N input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device (e.g.
LARA-R2 series - System Integration Manual 2.3.3 Module / host configuration selection 2.3.3.1 Guidelines for HOST_SELECT circuit design Selection of module / host configuration over HOST_SELECT is not supported by “02” product versions. LARA-R2 series modules include one pin (HOST_SELECT) to select the module / host application processor configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC (USB High-Speed Inter-Chip) interface.
LARA-R2 series - System Integration Manual 2.4 Antenna interface LARA-R2 series modules provide two RF interfaces for connecting the external antennas: The ANT1 pin represents the primary RF input/output for LTE/3G/2G RF signals transmission and reception. The ANT2 pin represents the secondary RF input for LTE Rx diversity RF signals reception.
LARA-R2 series - System Integration Manual o Radiation performance depends on the whole PCB and antenna system design, including product mechanical design and usage. Antennas should be selected with optimal radiating performance in the operating bands according to the mechanical specifications of the PCB and the whole product. o It is recommended to select a pair of custom antennas designed by an antennas’ manufacturer if the required ground plane dimensions are very small (e.g. less than 6.
LARA-R2 series - System Integration Manual Guidelines for RF transmission line design Any RF transmission line, such as the ones from the ANT1 and ANT2 pads up to the related antenna connector or up to the related internal antenna pad, must be designed so that the characteristic impedance is as close as possible to 50 .
LARA-R2 series - System Integration Manual the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 40 and Figure 41) the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g.
LARA-R2 series - System Integration Manual Guidelines for RF termination design RF terminations must provide a characteristic impedance of 50 as well as the RF transmission lines up to the RF terminations themselves, to match the characteristic impedance of the ANT1 / ANT2 ports of the modules. However, real antennas do not have perfect 50 load on all the supported frequency bands.
LARA-R2 series - System Integration Manual Examples of antennas Table 31 lists some examples of possible internal on-board surface-mount antennas. Manufacturer Part Number Product Name Description Taoglas PA.710.A Warrior Taoglas PA.711.A Warrior II Taoglas PCS.06.A Havok Antenova SR4L002 Lucida GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna Pairs with the Taoglas PA.710.
LARA-R2 series - System Integration Manual Table 33 lists some examples of possible external antennas. Manufacturer Part Number Product Name Description Taoglas GSA.8827.A.101111 Phoenix Taoglas TG.30.8112 Taoglas MA241.BI.001 GSM / WCDMA / LTE adhesive-mount antenna with cable and SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz 105 x 30 x 7.7 mm GSM / WCDMA / LTE swivel dipole antenna with SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz 148.
LARA-R2 series - System Integration Manual 2.4.2 Antenna detection interface (ANT_DET) 2.4.2.1 Guidelines for ANT_DET circuit design Figure 43 and Table 34 describe the recommended schematic / components for the antennas detection circuit that must be provided on the application board and for the diagnostic circuit that must be provided on the antennas’ assembly to achieve primary and secondary antenna detection functionality.
LARA-R2 series - System Integration Manual The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna).
LARA-R2 series - System Integration Manual 2.5 2.5.1.
LARA-R2 series - System Integration Manual Guidelines for single SIM card connection without detection A removable SIM card placed in a SIM card holder has to be connected to the SIM card interface of LARA-R2 series modules as described in Figure 44, where the optional SIM detection feature is not implemented. Follow these guidelines connecting the module to a SIM connector without SIM presence detection: Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
LARA-R2 series - System Integration Manual Guidelines for single SIM chip connection A solderable SIM chip (M2M UICC Form Factor) has to be connected the SIM card interface of LARA-R2 series modules as described in Figure 45. Follow these guidelines connecting the module to a solderable SIM chip without SIM presence detection: Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.
LARA-R2 series - System Integration Manual Guidelines for single SIM card connection with detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of LARA-R2 series modules as described in Figure 46, where the optional SIM card detection feature is implemented. Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection: Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.
LARA-R2 series - System Integration Manual Guidelines for dual SIM card / chip connection Two SIM card / chip can be connected to the SIM interface of LARA-R2 series modules as described in Figure 47. LARA-R2 series modules do not support the usage of two SIM at the same time, but two SIM can be populated on the application board, providing a proper switch to connect only the first or only the second SIM at a time to the SIM interface of the modules, as described in Figure 47.
LARA-R2 series - System Integration Manual FIRST SIM CARD LARA-R2 series VSIM 41 3V8 VPP (C6) 4PDT C11 Analog Switch VCC 1VSIM VSIM 2VSIM VCC (C1) DAT 1DAT 2DAT SIM_CLK 38 CLK 1CLK 2CLK SIM_RST 40 RST 1RST 2RST SIM_IO 39 IO (C7) CLK (C3) RST (C2) C1 C2 C3 C4 C5 GND (C5) D1 D2 D3 D4 J1 SECOND SIM CARD VPP (C6) SEL GND VCC (C1) U1 IO (C7) CLK (C3) Application Processor RST (C2) GPIO C6 C7 C8 C9 C10 R1 GND (C5) D5 D6 D7 D8 J2 Figure 47: Application circuit for the connection to
LARA-R2 series - System Integration Manual 2.6 Data communication interfaces 2.6.1 UART interface 2.6.1.1 Guidelines for UART circuit design Providing the full RS-232 functionality (using the complete V.24 link) If RS-232 compatible signal levels are needed, two different external voltage translators can be used to provide full RS-232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for the translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the translation from 3.
LARA-R2 series - System Integration Manual Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link) If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available: Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used.
LARA-R2 series - System Integration Manual Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.
LARA-R2 series - System Integration Manual Providing the TXD and RXD lines only (not using the complete V24 link) If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available: Connect the module RTS input line to GND or to the CTS output line of the module: since the module requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, which is the default setting).
LARA-R2 series - System Integration Manual Additional considerations If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the apposite 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost solution, by means of an appropriate voltage divider.
LARA-R2 series - System Integration Manual 2.6.2 USB interface 2.6.2.1 Guidelines for USB circuit design The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer. USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.
LARA-R2 series - System Integration Manual 2.6.2.2 Guidelines for USB layout design The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to 480 Mb/s) supported by the USB serial interface. The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0 specification [9].
LARA-R2 series - System Integration Manual 2.6.3 HSIC interface 2.6.3.1 Guidelines for HSIC circuit design The HSIC interface is not supported by “02” modules product versions except for diagnostic purpose. LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with maximum 480 Mb/s data rate according to the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10] and USB Specification Revision 2.0 [9].
LARA-R2 series - System Integration Manual 2.6.3.2 Guidelines for HSIC layout design HSIC lines require accurate layout design to achieve reliable signaling at high speed data rate (up to 480 Mb/s), as supported by the HSIC serial interface: signal integrity may be degraded if PCB layout is not optimal, especially when the HSIC lines are very long.
LARA-R2 series - System Integration Manual 2.6.4 DDC (I2C) interface 2.6.4.1 2 Guidelines for DDC (I C) circuit design General considerations 2 Communication with u-blox GNSS receivers over DDC (I C) is not supported by “02” product versions. 2 The DDC I C-bus master interface can be used to communicate with u-blox GNSS receivers and other external 2 I C-bus slaves as an audio codec.
LARA-R2 series - System Integration Manual Connection with u-blox 1.8 V GNSS receivers Figure 60 shows an application circuit for connecting the cellular module to a u-blox 1.8 V GNSS receiver: The SDA and SCL pins of the cellular module are directly connected to the related pins of the u-blox 1.8 V GNSS receiver, with appropriate pull-up resistors connected to the 1.8 V GNSS supply enabled after the 2 V_INT supply of the I C pins of the cellular module.
LARA-R2 series - System Integration Manual Figure 61 illustrates an alternative solution as supply for u-blox 1.8 V GNSS receivers: the V_INT 1.8 V regulated supply output of the cellular module can be used to supply a u-blox 1.8 V GNSS receiver of the u-blox 6 generation (or any newer u-blox GNSS receiver generation) instead of using an external voltage regulator as shown in the previous Figure 60. The V_INT supply is able to support the maximum current consumption of these positioning receivers.
LARA-R2 series - System Integration Manual Connection with u-blox 3.0 V GNSS receivers Figure 62 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS receiver: As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the related 2 2 I C pins of the u-blox 3.0 V GNSS receiver must be provided using a proper I C-bus Bidirectional Voltage Translator (e.g.
LARA-R2 series - System Integration Manual 2.6.5 SDIO interface 2.6.5.1 Guidelines for SDIO circuit design The functionality of the SDIO Secure Digital Input Output interface pins is not supported by LARA-R2 series modules “02” product versions: the pins should not be driven by any external device. LARA-R2 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with an external u-blox short range Wi-Fi module.
LARA-R2 series - System Integration Manual 2.7 Audio interface Audio is not supported by LARA-R204 module “02” product version. 2.7.1 Digital audio interface 2.7.1.1 Guidelines for digital audio circuit design 2 I S digital audio interface can be connected to an external digital audio device for voice applications.
LARA-R2 series - System Integration Manual Examples of manufacturers offering compatible audio codec parts are the following: Maxim Integrated (as the MAX9860, MAX9867, MAX9880A audio codecs) Texas Instruments / National Semiconductor Cirrus Logic / Wolfson Microelectronics Nuvoton Technology Asahi Kasei Microdevices Realtek Semiconductor 2 Figure 63 and Table 47 describe an application circuit for the I S digital audio interface providing basic voice capability using an external au
LARA-R2 series - System Integration Manual Reference Description Part Number – Manufacturer C1 C2, C4, C5, C6 100 nF Capacitor Ceramic X5R 0402 10% 10V 1 µF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R71C104KA01 – Murata GRM155R60J105KE19 – Murata C3 C7, C8, C9, C10 10 µF Capacitor Ceramic X5R 0603 20% 6.
LARA-R2 series - System Integration Manual Keep ground separation from microphone lines to other noisy signals. Use an intermediate ground layer or vias wall for coplanar signals. In case of external audio device providing differential microphone input, route microphone signal lines as a differential pair embedded in ground to reduce differential noise pick-up. The balanced configuration will help reject the common mode noise. Cross other signals lines on adjacent layers with 90° crossing.
LARA-R2 series - System Integration Manual 2.8 General Purpose Input/Output (GPIO) 2.8.1.1 Guidelines for GPIO circuit design A typical usage of LARA-R2 series modules’ GPIOs can be the following: Network indication provided over GPIO1 pin (see Figure 64 / Table 48 below) GNSS supply enable function provided by the GPIO2 pin (see section 2.6.4) GNSS Tx data ready function provided by the GPIO3 pin (see section 2.6.4) GNSS RTC sharing function provided by the GPIO4 pin (see section 2.6.
LARA-R2 series - System Integration Manual 2.9 Reserved pins (RSVD) LARA-R2 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board except the following RSVD pin, as described in Figure 65: the RSVD pin number 33 that must be externally connected to ground LARA-R2 RSVD 33 RSVD Figure 65: Application circuit for the reserved pins (RSVD) 2.
LARA-R2 series - System Integration Manual 2.11 Module footprint and paste mask Figure 66 and Table 49 describe the suggested footprint (i.e. copper mask) and paste mask layout for LARA modules: the proposed land pattern layout reflects the modules’ pins layout, while the proposed stencil apertures layout is slightly different (see the F’’, H’’, I’’, J’’, O’’ parameters compared to the F’, H’, I’, J’, O’ ones).
LARA-R2 series - System Integration Manual 2.12 Thermal guidelines Modules’ operating temperature range is specified in LARA-R2 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload in connected-mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power.
LARA-R2 series - System Integration Manual 2.13 ESD guidelines The sections 2.13.1 and 2.13.2 are related to EMC / ESD immunity. The modules are ESD sensitive devices and the ESD sensitivity for each pin (as Human Body Model according to JESD22-A114F) is specified in LARA-R2 series Data Sheet [1]. Special precautions are required when handling: see section 3.2 for handling guidelines. 2.13.
LARA-R2 series - System Integration Manual 2.14 Schematic for LARA-R2 series module integration Figure 67 is an example of a schematic diagram where a LARA-R2 series cellular module “02” product version is integrated into an application board, using all the available interfaces and functions of the module. LARA-R2 series (‘02’ product version) + 330µF 100nF 10nF Mount for modules supporting 2G 56pF 15pF 51 VCC 52 VCC 53 VCC 8.
LARA-R2 series - System Integration Manual 2.15 Design-in checklist This section provides a design-in checklist. 2.15.1 Schematic checklist The following are the most important points for a simple schematic check: DC supply must provide a nominal voltage at VCC pin within the operating range limits. VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in particular if the application device integrates an internal antenna.
LARA-R2 series - System Integration Manual 2.15.2 Layout checklist The following are the most important points for a simple layout check: Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT1 and the ANT2 ports (antenna RF interfaces). Ensure no coupling occurs between the RF interface and noisy or sensitive signals (primarily analog audio input/output signals, SIM signals, high-speed digital lines such as SDIO, USB and other data lines).
LARA-R2 series - System Integration Manual 3 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 3.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to LARA-R2 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning, see the LARA-R2 series Data Sheet [1] and the u-blox Package Information Guide [25]. 3.
LARA-R2 series - System Integration Manual 3.3 Soldering 3.3.1 Soldering paste Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste: OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification: 95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.
LARA-R2 series - System Integration Manual To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module.
LARA-R2 series - System Integration Manual 3.3.5 Repeated reflow soldering Only a single reflow soldering process is encouraged for boards with a LARA-R2 series module populated on it. 3.3.6 Wave soldering Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. Only a single wave soldering process is encouraged for boards populated with LARA-R2 series modules. 3.3.
LARA-R2 series - System Integration Manual 4 Approvals For the complete list and specific details regarding the certification schemes approvals, see LARA-R2 series Data Sheet [1], or please contact the u-blox office or sales representative nearest you. 4.
LARA-R2 series - System Integration Manual 4.2 US Federal Communications Commission notice United States Federal Communications Commission (FCC) IDs: u-blox LARA-R204 cellular modules: XPY1EIQN2NN 4.2.1 Safety warnings review the structure Equipment for building-in.
LARA-R2 series - System Integration Manual IMPORTANT: Manufacturers of portable applications incorporating the LARA-R2 series modules are required to have their final product certified and apply for their own FCC Grant related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Additional Note: as per 47CFR15.
LARA-R2 series - System Integration Manual The IC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating: "Contains IC: 8595A-1EIQN2NN " resp. Canada, Industry Canada (IC) Notices This Class B digital apparatus complies with Canadian CAN ICES-3(B) / NMB-3(B) and RSS-210.
LARA-R2 series - System Integration Manual Pour des informations supplémentaires concernant l'exposition aux RF au Canada rendez-vous sur: http://www.ic.gc.ca/eic/site/smt-gst.nsf/fra/sf08792.html IMPORTANT: les fabricants d'applications portables contenant les modules LARA-R2 series doivent faire certifier leur produit final et déposer directement leur candidature pour une certification FCC ainsi que pour un certificat Industrie Canada délivré par l'organisme chargé de ce type d'appareil portable.
LARA-R2 series - System Integration Manual 5 Product testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested automatically in production line. Stringent quality control process has been implemented in the production line. Defective units are analyzed in detail to improve the production quality. This is achieved with automatic test equipment (ATE) in production line, which logs all production and measurement data.
LARA-R2 series - System Integration Manual 5.2 Test parameters for OEM manufacturer Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test.
LARA-R2 series - System Integration Manual This feature allows the measurement of the transmitter and receiver power levels to check component assembly related to the module antenna interface and to check other device interfaces from which depends the RF performance. To avoid module damage during transmitter test, a proper antenna according to module specifications or a 50 termination must be connected to ANT1 port.
LARA-R2 series - System Integration Manual Appendix A Migration between SARA-U2 and LARA-R2 A.1 Overview Migrating between u-blox SARA-U2 series 3G / 2G cellular modules and LARA-R2 series LTE Cat 1 / 2G cellular modules is a straightforward procedure that allows customers to take maximum advantage of their hardware and software investments.
LARA-R2 series - System Integration Manual SARA and LARA modules are also form-factor compatible with u-blox LISA and TOBY cellular module families: although SARA, LARA, LISA (33.2 x 22.4 mm, 76-pin LCC) and TOBY (35.6 x 24.8 mm, 152-pin LGA) modules each have different form factors, the footprints of all the SARA, LARA, LISA and TOBY modules have been developed to ensure layout compatibility.
LARA-R2 series - System Integration Manual Table 51 summarizes the interfaces provided by SARA-U2 and LARA-R2 series modules: all the interfaces provided by different modules are electrically compatible, so that the same compatible external circuit can be implemented on the application board.
LARA-R2 series - System Integration Manual A.2 Pin-out comparison between SARA-U2 and LARA-R2 SARA-U2 LARA-R2 Pin No Pin Name Description Pin Name Description 1 GND Ground GND Ground Remarks for migration 2 V_BCKP RTC Supply I/O Output characteristics: 1.8 V typ, 3 mA max Input op. range: 1.0 V – 1.9 V V_BCKP RTC Supply I/O Output characteristics: 1.8 V typ, 3 mA max Input op. range: 1.0 V – 1.9 V 3 GND Ground GND Ground 4 V_INT Interfaces Supply Out Output characteristics: 1.
LARA-R2 series - System Integration Manual SARA-U2 LARA-R2 Pin No Pin Name Description Pin Name Description 26 SDA I C Data I/O 1.8 V, open drain Driver strength: 1 mA SDA I C Data I/O 1.8 V, open drain Driver strength: 1 mA No functional difference 27 SCL I2C Clock Output 1.8 V, open drain Driver strength: 1 mA SCL I2C Clock Output 1.8 V, open drain Driver strength: 1 mA No functional difference 28 USB_D- USB Data I/O (D-) High-Speed USB 2.
LARA-R2 series - System Integration Manual A.3 Schematic for SARA-U2 and LARA-R2 integration Figure 75 shows an example of schematic diagram where a SARA-U2 or a LARA-R2 series module can be integrated into the same application board, using all the available interfaces and functions of the modules. The different mounting options for the external parts are herein remarked according to the functions supported by each module.
LARA-R2 series - System Integration Manual B Glossary 3GPP 3rd Generation Partnership Project 8-PSK 8 Phase-Shift Keying modulation 16QAM 16-state Quadrature Amplitude Modulation ACM Abstract Control Model ADC Analog to Digital Converter AP Application Processor ASIC Application-Specific Integrated Circuit AT AT Command Interpreter Software Subsystem, or attention BAW Bulk Acoustic Wave CDC Communication Device Class CSFB Circuit Switched Fall-Back DC Direct Current DCE Data Commun
LARA-R2 series - System Integration Manual LCC Leadless Chip Carrier LDO Low-Dropout LGA Land Grid Array LNA Low Noise Amplifier LPDDR Low Power Double Data Rate synchronous dynamic RAM memory LTE Long Term Evolution MCS Modulation Coding Scheme N/A Not Applicable NCM Network Control Model OEM Original Equipment Manufacturer device: an application device integrating a u-blox cellular module OTA Over The Air PA Power Amplifier PCM Pulse Code Modulation PFM Pulse Frequency Modulati
LARA-R2 series - System Integration Manual Related documents [1] u-blox LARA-R2 series Data Sheet, Docu No UBX-16005783 [2] [3] u-blox AT Commands Manual, Docu No UBX-13002752 u-blox EVK-R2xx User Guide, Docu No UBX-16016088 [4] u-blox Windows Embedded OS USB Driver Installation Application Note, Docu No UBX-14003263 [5] ITU-T Recommendation V.24 - 02-2000 - List of definitions for interchange circuits between the Data Terminal Equipment (DTE) and the Data Circuit-terminating Equipment (DCE).
LARA-R2 series - System Integration Manual Revision history Revision Date Name Status / Comments R01 20-Sep-2016 sses Initial release UBX-16010573 - R02 Objective Specification Revision history Page 147 of 148
LARA-R2 series - System Integration Manual Contact For complete contact information visit us at www.u-blox.com. u-blox Offices North, Central and South America u-blox America, Inc. Phone: +1 703 483 3180 E-mail: info_us@u-blox.com Regional Office West Coast: Phone: +1 408 573 3640 E-mail: info_us@u-blox.com Headquarters Europe, Middle East, Africa u-blox AG Phone: +41 44 722 74 44 E-mail: info@u-blox.com Support: support@u-blox.com Technical Support: Phone: +1 703 483 3185 E-mail: support_us@u-blox.
