48-V to 3.
48-V to 3.
User's Guide SLUU178A – November 2003 – Revised December 2006 Using the UCC2891 Active Clamp Current Mode PWM Controller 1 Introduction The UCC2891EVM evaluation module (EVM) is a forward converter providing a 3.3-V regulated output at 30 A of load current, operating from a 48-V input. The EVM operates over the full 36 V to 72 V telecom input range, and is able to fully regulate down to zero load current.
www.ti.com Description 2.1 Applications The UCC2891 is suited for use in isolated telecom 48-V input systems requiring high-efficiency and high-power density for very low-output voltage, high-current converter applications, including: • Server Systems • Datacom • Telecom • DSP's, ASIC's, FPGA's 2.2 Features The UCC2891EVM features include: • ZVS transformer reset using active clamp technique in forward converter • All surface mount components, double sided half brick (2.2 × 2.28 × 0.
www.ti.com UCC2891EVM Electrical Performance Specifications 3 UCC2891EVM Electrical Performance Specifications The UCC2891EVM electrical performance specifications are listed in Table 1. Table 1. UCC2891EVM Performance Summary PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Characteristics Input voltage range 36 48 72 V 75 100 mA VIN = 36 V, IOUT = 30 A 3.00 3.25 A VIN = 72 V, IOUT = 30 A 1.50 1.75 VP-P 3.30 3.
www.ti.com + + + + Schematic Figure 1.
www.ti.com EVM Test Setup High efficiency is achieved using self-driven synchronous rectification on the secondary side. Q3 and Q4 are placed in parallel and make up the forward synchronous rectifier (SR), while the reverse SR is made up of the parallel combination of Q5, Q7 and Q8.
www.ti.com EVM Test Setup 5.1 Output Load (LOAD1) For the output load to VOUT, a programmable electronic load set to constant current mode and capable of sinking between 0ADC and 30ADC, is used. Using a dc voltmeter, V2, it is also advised to make all output voltage measurements directly at J9 and J10 pins.
www.ti.com Power Up/Down Test Procedures 6 Power Up/Down Test Procedures The following test procedure is recommended primarily for power up and shutting down the EVM. Whenever the EVM is running above an output load of 15 ADC, the fan should be turned on. Also, never walk away from a powered EVM for extended periods of time. 1. Working at an ESD workstation, make sure that any wrist straps, bootstraps or mats are connected referencing the user to earth ground before power is applied to the EVM.
www.ti.com Power Up/Down Test Procedures 7 Power Up/Down Test Procedures OVERALL EFFICIENCY vs OUTPUT CURRENT 93 VIN = 48 V Percent Efficiency - % 91 89 VIN = 72 V VIN = 36 V 87 85 83 81 VOUT = 3.3 V fS = 300 kHz 79 2 6 10 14 18 22 26 IOUT - Output Current - A Figure 3. POWER LOSS vs OUTPUT CURRENT GAIN AND PHASE vs FREQUENCY 12 60 VOUT = 3.
www.ti.com Power Up/Down Test Procedures Input Ripple Voltage GAIN AND PHASE vs FREQUENCY 60 VIN = 36 V IOUT = 30 A 180 Phase 40 120 60 0 0 Gain -20 Phase - ° Gain - dB 20 500 mV/div 1 V peak-to-peak -60 VIN = 48 V IOUT = 10 A gM = -10 dB FM = 50° -40 -120 -60 10 100 1k 10 k -180 100 k t − Time − 2.5 µs/div f - Frequency - Hz Figure 8. Figure 6.
www.ti.com Power Up/Down Test Procedures SR Gate Drive Output Ripple Voltage VIN = 36 V VIN = 36 V IOUT = 30 A 6.3 V, QF Gate (J5) (5 V/div) 50 mV/div 23 mV peak-to-peak 8.4 V, QR Gate (J6) (5 V/div) t − Time − 1 µs/div t − Time − 2.5 µs/div Figure 12. Figure 10. SR Gate Drive Transformer Primary VIN = 72 V VIN = 48 V IOUT = 10 A VPRI (40 V/div) IPRI (0.5 A/div) 12 12.3 V, QF Gate (J5) (5 V/div) 5.4 V, QR Gate (J6) (5 V/div) t − Time − 2.5 µs/div t − Time − 1 µs/div Figure 11. Figure 13.
www.ti.com EVM Assembly Drawing and Layout 8 EVM Assembly Drawing and Layout Figure 14 through Figure 20 show the top-side and bottom-side component placement for the EVM, as well as device pin numbers where necessary. A four layer PCB was designed using the top and bottom layers for signal traces and component placement along with an internal ground plane. The PCB dimensions are 3.6" x 2.
www.ti.com EVM Assembly Drawing and Layout Figure 15. Top Side Silk Screen Figure 16.
www.ti.com EVM Assembly Drawing and Layout Figure 17. Internal Split Ground Plane Figure 18.
www.ti.com EVM Assembly Drawing and Layout Figure 19. Bottom Signal Trace Layer Figure 20.
www.ti.com List of Materials 9 List of Materials The following table lists the UCC2891EVM components corresponding to the schematic shown in Figure 1. Table 2. List of Materials REF QT Y DESCRIPTION MFR PART NUMBER C1, C2, C4 3 Capacitor, ceramic, 2.2 µF, 100 V, X7R, 20%, 1812 TDK C4532X7R2A225M C3, C14, C17 3 Capacitor, ceramic, 0.
www.ti.com References Table 2. List of Materials (continued) REF 10 QT Y DESCRIPTION MFR PART NUMBER R1 1 Resistor, chip, 8.45 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-8451-F R2 1 Resistor, chip, 57.6 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-5762-F R3 1 Resistor, chip, 76.8 kΩ, 1/10 W, 1%, 805 Vishay CRCW0805-7682-F R4, R10, R15, R16, R20, R23, R24 7 Resistor, chip, 2.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 Vdc to 72 Vdc. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
