y ! " # $ %E %& ' ( )%*+ $& % % ,( Data Manual March 2007 Digital Audio Video SLES140A
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Contents Contents Section 1 2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Detailed Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 TVP5147M1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
Contents Section Page 2.11.11 2.11.12 2.11.13 2.11.14 2.11.15 2.11.16 2.11.17 2.11.18 2.11.19 2.11.20 2.11.21 2.11.22 2.11.23 2.11.24 2.11.25 2.11.26 2.11.27 2.11.28 2.11.29 2.11.30 2.11.31 2.11.32 2.11.33 2.11.34 2.11.35 2.11.36 2.11.37 2.11.38 2.11.39 2.11.40 2.11.41 2.11.42 2.11.43 2.11.44 2.11.45 2.11.46 2.11.47 2.11.48 2.11.49 2.11.50 2.11.51 2.11.52 2.11.53 2.11.54 2.11.55 2.11.56 2.11.57 2.11.58 iv SLES140 Luminance Contrast Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section 3 Page 2.11.59 Analog Output Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.60 Chip ID MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.61 Chip ID LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.62 CPLL Speed Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section Page 3.3 80 80 80 81 83 83 83 83 83 83 83 84 84 84 87 87 88 4 5 vi Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Analog Processing and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Timing . . . . . . . . . .
List of Illustrations List of Illustrations Figure 1−1 1−2 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 2−17 2−18 2−19 3−1 3−2 5−1 Title Page Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Assignments Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Processors and A/D Converters . . . . . . . .
List of Tables List of Tables Table Title 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Line Frequencies, Data Rates, and Pixel/Line Counts . . . . . . . . . . . . . . . . . . . . .
Introduction 1 Introduction The TVP5147M1 device is a high-quality, single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5147M1 decoder supports the analog-to-digital (A/D) conversion of component YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder includes two 10-bit 30-MSPS A/D converters (ADCs).
Introduction 1.1 Detailed Functionality • Two 30-MSPS, 10-bit A/D channels with programmable gain control • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, and S-video • Supports analog component YPbPr video format with embedded sync • 10 analog video input terminals for multisource connection • Supports analog video output • User-programmable video output formats 10-bit ITU-R BT.
Introduction • • • • 1.2 TVP5147M1 Applications • • • • • • • • 1.3 1.4 VBI data processor − Teletext (NABTS, WST) − CC and extended data service (EDS) − Wide screen signaling (WSS) − Copy generation management system (CGMS) − Video program system (VPS/PDC) − Vertical interval time code (VITC) − Gemstar 1×/2× mode − V-Chip decoding − Register readback of CC, WSS (CGMS), VPS/PDC, VITC and Gemstar 1×/2× sliced data I2C host port interface Reduced power consumption: 1.8-V digital core, 3.
Introduction 1.
Introduction 1.
Introduction 1.7 Terminal Functions Table 1−1. Terminal Functions TERMINAL NAME NUMBER I/O DESCRIPTION Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A 80 1 2 7 8 9 16 17 18 23 I/O I I I I I I I I I VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Section 2.11.
Introduction Table 1−1. Terminal Functions (Continued) TERMINAL NAME NUMBER I/O DESCRIPTION Power Supplies AGND 26 Analog ground. Connect to analog ground. A18GND_REF 13 Analog 1.8-V return A18VDD_REF 12 Analog power for reference 1.8 V CH1_A18GND CH2_A18GND A18GND 79 10 24 Analog 1.8-V return CH1_A18VDD CH2_A18VDD A18VDD 78 11 25 Analog power. Connect to 1.8 V. CH1_A33GND CH2_A33GND 3 6 Analog 3.3-V return CH1_A33VDD CH2_A33VDD 4 5 Analog power. Connect to 3.3 V.
Introduction 8 TVP5147M1PFP SLES140A—March 2007
Functional Description 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2−1 shows a functional diagram of the analog processors and A/D converters, which provide the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. The TVP5147M1 supports one analog video output for the selected analog input video.
Functional Description • • • • Up to 10 selectable individual composite video inputs Up to four selectable S-video inputs Up to three selectable analog YPbPr video inputs and one CVBS input Up to two selectable analog YPbPr video inputs, two S-video inputs, and two CVBS inputs The input selection is performed by the input select register at I2C subaddress 00h (see Section 2.11.1). 2.1.2 Analog Input Clamping An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
Functional Description 2.2 Digital Video Processing Figure 2−2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs.
Functional Description Peaking CVBS/Y Line Delay Delay Y – Y NTSC/PAL Remodulation SECAM Luma Contrast Brightness Saturation Adjust Notch Filter CVBS SECAM Color Demodulation U Burst Accumulator (V) V CVBS/C NTSC/PAL Demodulation Color LPF ↓2 Cr Notch Filter Color LPF ↓2 Burst Accumulator (U) Cb 5-Line Adaptive Comb Filter Notch Filter Delay Notch Filter Delay U V Figure 2−3. Composite and S-Video Processing Block Diagram 2.2.2.
Functional Description 10 0 0 −10 −10 Amplitude − dB Amplitude − dB 10 −20 −30 ITU-R BT.601 −3 dB @ 1.42 MHz −40 −60 1.5 2.0 2.5 3.0 3.5 Filter 1 −3 dB @ 1.03 MHz −40 −60 1.0 Filter 3 −3 dB @ 554 kHz −30 −50 0.5 Filter 0 −3 dB @ 1.41 MHz −20 −50 −70 0.0 Filter 2 −3 dB @ 844 kHz −70 0.0 4.0 0.5 1.0 f − Frequency − MHz Figure 2−4. Color Low-Pass Filter Frequency Response 2.2.2.2 1.5 2.0 2.5 3.0 3.5 4.0 f − Frequency − MHz Figure 2−5.
Functional Description 2.2.3 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2−8 illustrates the basic functions of the luminance data path.
Functional Description 2.3 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drive the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2).
Functional Description Table 2−1.
Functional Description 525-Line 525 1 2 3 4 5 6 7 8 9 10 20 21 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 262 263 VBLK Stop 264 265 266 267 268 269 270 271 272 273 283 284 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 VBLK Stop Figure 2−12.
Functional Description 625-Line 622 623 624 625 1 2 3 4 5 6 7 23 24 25 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 310 311 VBLK Stop 312 313 314 315 316 317 318 319 320 336 337 338 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 VBLK Stop Figure 2−13.
Functional Description 0 DATACLK Y[9:0] Cb Y Cr Y EAV EAV EAV EAV 2 1 3 4 Horizontal Blanking HS Start SAV SAV SAV SAV Cb0 1 2 3 4 Y0 Cr0 Y1 HS Stop HS A C B D AVID AVID Stop AVID Start DATACLK = 2× Pixel Clock Mode A B C D NTSC 601 106 128 42 276 PAL 601 112 128 48 288 NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference Figure 2−14.
Functional Description 0 DATACLK Y[9:0] CbCr[9:0] Y Y Y Y Horizontal Blanking Cb Cr Cb Cr Horizontal Blanking HS Start Y0 Y1 Y2 Y3 Cb0 Cr0 Cb1 Cr1 HS Stop HS A C B 2 D AVID AVID Stop AVID Start NOTE: AVID rising edge occurs 4 clock cycles early. DATACLK = 1× Pixel Clock Mode A B C D NTSC 601 53 64 19 136 PAL 601 56 64 22 142 NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference Figure 2−15.
Functional Description HS First Field B/2 B/2 VS HS H/2 + B/2 Second Field H/2 + B/2 VS 10-Bit (PCLK = 2× Pixel Clock) 20-Bit (PCLK = 1× Pixel Clock) Mode B/2 H/2 B/2 H/2 NTSC 601 64 858 32 429 PAL 601 64 864 32 432 Figure 2−16. VSYNC Position With Respect to HSYNC 2.5.2 Embedded Syncs Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits which also define vertical timing.
Functional Description Table 2−4. I2C Host Interface Terminal Description SIGNAL TYPE I2CA DESCRIPTION I Slave address selection SCL I Input clock line SDA I/O Input/output data line 2.6.1 Reset and I 2C Bus Address Selection The TVP5147M1 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal.
Functional Description I2C Registers VBUS Registers 00h HOST Processor 00 0000h I2C CC 80 051Ch WSS 80 0520h VITC E0h VBUS Data E1h E8h Line Mode VBUS[23:0] VPS VBUS Address EAh FIFO FFh 80 052Ch 80 0600h 80 0700h 90 1904h FF FFFFh VBUS Write Single Byte S B8 ACK E8 ACK VA0 ACK VA1 ACK S B8 ACK E0 ACK Send Data ACK P VA2 ACK P ACK P Multiple Bytes S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 S B8 ACK E1 ACK Send Data ACK ••• Send Data VA0 VA1 ACK VA2 ACK
Functional Description 2.7 VBI Data Processor The TVP5147M1 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code (VITC), video program system (VPS), copy generation management system (CGMS) data, and electronic program guide (Gemstar) 1x/2x. Table 2−6 shows the supported VBI system.
Functional Description 2.7.1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is output on the Y[9:2] terminals during the horizontal blanking period. Table 2−7 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes.
Functional Description 2.7.2 VBI Raw Data Output The TVP5147M1 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing. This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656 format having only luma data. The chroma samples are replaced by luma samples.
Functional Description 2.
Functional Description Table 2−10.
Functional Description Table 2−10.
Functional Description Table 2−10.
Functional Description 2.11 Register Definitions 2.11.1 Input Select Register Subaddress 00h Default 00h 7 6 5 4 3 2 1 0 Input select [7:0] Table 2−12.
Functional Description 2.11.2 AFE Gain Control Register Subaddress 01h Default 0Fh 7 6 5 4 Reserved 3 2 1 0 1 1 AGC chroma AGC luma Bit 3: 1 must be written to this bit. Bit 2: 1 must be written to this bit. AGC chroma enable: Controls automatic gain in the chroma/PbPr channel: 0 = Manual (if AGC luma is set to manual, AGC chroma is forced to be in manual) 1 = Enabled auto gain, applied a gain value acquired from the sync channel for S-video and component mode.
Functional Description 2.11.4 Operation Mode Register Subaddress 03h Default 00h 7 6 5 4 3 2 1 Reserved 0 Power save Power save: 0 = Normal operation (default) 1 = Power-save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C interface is active and all current operating settings are preserved. 2.11.5 Autoswitch Mask Register Subaddress 04h Default 23h 7 6 5 4 3 2 1 0 Reserved PAL 60 SECAM NTSC 4.
Functional Description 2.11.6 Color Killer Register Subaddress 05h Default 10h 7 6 Reserved 5 4 3 2 Automatic color killer 1 0 Color killer threshold [4:0] Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the UV terminals are forced to a zero color state. 11 = Color killer disabled Color killer threshold [4:0]: 1 1111 = 31 (maximum) 1 0000 = 16 (default) 0 0000 = 0 (minimum) 2.11.
Functional Description 2.11.8 Luminance Processing Control 2 Register Subaddress 07h Default 00h 7 6 5 Luma filter select [1:0] 4 3 Reserved 2 1 Peaking gain [1:0] 0 Reserved Luma filter selected [1:0]: 00 = Luminance adaptive comb enabled (default on CVBS) 01 = Luminance adaptive comb disabled (trap filter selected) 10 = Luma comb/trap filter bypassed (default on S-video, component mode, and SECAM) 11 = Reserved Peaking gain [1:0]: 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 2.11.
Functional Description 2.11.11 Luminance Contrast Register Subaddress 0Ah Default 80h 7 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS, S-video, and component video luminance. 1111 1111 = 255 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) 2.11.12 Chrominance Saturation Register Subaddress 0Bh Default 80h 7 6 5 4 3 2 1 0 Saturation [7:0] Saturation [7:0]: This register works for CVBS, S-video, and component video luminance.
Functional Description 2.11.15 Chrominance Processing Control 2 Register Subaddress 0Eh Default 0Eh 7 6 5 4 Reserved 3 2 PAL compensation WCF 1 0 Chrominance filter select [1:0] PAL compensation: 0 = Disabled 1 = Enabled (default) Wideband chroma LPF filter (WCF): 0 = Disabled 1 = Enabled (default) Chrominance filter select [1:0]: 00 = Disabled 01 = Notch 1 10 = Notch 2 (default) 11 = Notch 3 See Figure 2−6 and Figure 2−7 for characteristics. 2.11.
Functional Description 2.11.17 AVID Stop Pixel Register Subaddress 18h−19h Default 325h Subaddress 7 6 5 4 18h 3 2 1 0 AVID stop [7:0] 19h Reserved AVID stop [9:8] AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location from HSYNC start pixel 0.
Functional Description 2.11.21 VSYNC Stop Line Register Subaddress 20h−21h Default 007h Subaddress 7 6 5 4 20h 3 2 1 0 VSYNC stop [7:0] 21h Reserved VSYNC stop [9:8] VSYNC stop [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VSYNC stop only when the VSYNC stop MSB is written to. If the user changes these registers, the TVP5147M1 decoder retains values in different modes until this decoder resets. NTSC: default 007h PAL: default 004h 2.11.
Functional Description 2.11.25 CTI Control Register Subaddress 2Eh Default 00h 7 6 5 4 3 2 CTI coring [3:0] 1 0 CTI gain [3:0] CTI coring [3:0]: 4-bit CTI coring limit control value, unsigned linear control range from 0 to ±60, step size = 4 1111 = ±60 0001 = ±4 0000 = 0 (default) CTI gain [3:0]: 4-bit CTI gain control values, unsigned linear control range from 0 to 15/16, step size = 1/16 1111 = 15/16 0001 = 1/16 0000 = 0 disabled (default) 2.11.
Functional Description 2.11.27 Output Formatter 1 Register Subaddress 33h Default 40h 7 6 5 Reserved YCbCr code range CbCr code 4 3 2 Reserved 1 0 Output format [2:0] YCbCr output code range: 0 = ITU-R BT.601 coding range (Y ranges from 64 to 940. Cb and Cr range from 64 to 960.) 1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016.
Functional Description 2.11.29 Output Formatter 3 Register Subaddress 35h Default FFh 7 6 GPIO [1:0] 5 4 AVID [1:0] 3 2 GLCO [1:0] 1 0 FID [1:0] GPIO [1:0]: FSS terminal function select 00 = GPIO is logic 0 output. 01 = GPIO is logic 1 output. 10 = Reserved 11 = GPIO is logic input (default). AVID [1:0]: AVID terminal function select 00 = AVID is logic 0 output. 01 = AVID is logic 1 output. 10 = AVID is active video indicator output. 11 = AVID is logic input (default).
Functional Description 2.11.30 Output Formatter 4 Register Subaddress 36h Default FFh 7 6 VS/VBLK [1:0] 5 4 3 HS/CS [1:0] 2 C_1 [1:0] 1 0 C_0 [1:0] VS/VBLK [1:0]: VS terminal function select 00 = VS/VBLK is logic 0 output. 01 = VS/VBLK is logic 1 output. 10 = VS/VBLK is vertical sync or vertical blank output corresponding to bit 1 (VS/VBLK) in the sync control register at subaddress 32h (see Section 2.11.26). 11 = VS/VBLK is logic input (default).
Functional Description 2.11.31 Output Formatter 5 Register Subaddress 37h Default FFh 7 6 C_5 [1:0] 5 4 3 C_4 [1:0] 2 C_3 [1:0] 1 0 C_2 [1:0] C_5 [1:0]: C_5 terminal function select 00 = C_5 is logic 0 output. 01 = C_5 is logic 1 output. 10 = Reserved 11 = C_5 is logic input (default). C_4 [1:0]: C_4 terminal function select 00 = C_4 is logic 0 output. 01 = C_4 is logic 1 output. 10 = Reserved 11 = C_4 is logic input (default).
Functional Description 2.11.32 Output Formatter 6 Register Subaddress 38h Default FFh 7 6 5 C_9 [1:0] 4 3 C_8 [1:0] 2 1 C_7 [1:0] 0 C_6 [1:0] C_9 [1:0]: C_9 terminal function select 00 = C_9 is logic 0 output. 01 = C_9 is logic 1 output. 10 = Reserved 11 = C_9 is logic input (default). C_8 [1:0]: C_8 terminal function select 00 = C_8 is logic 0 output. 01 = C_8 is logic 1 output. 10 = Reserved 11 = C_8 is logic input (default).
Functional Description 2.11.34 Status 1 Register Subaddress 3Ah Read only 7 6 5 4 3 2 1 0 Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status Peak white detect status: 0 = Peak white is not detected. 1 = Peak white is detected.
Functional Description 2.11.35 Status 2 Register Subaddress 3Bh Read only 7 6 5 4 3 Signal present Weak signal detection PAL switch polarity Field sequence status Color killed 2 1 0 Macrovision detection [2:0] Signal present detection: 0 = Signal not present 1 = Signal present Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is zero. 1 = PAL switch is one.
Functional Description 2.11.37 Video Standard Status Register Subaddress 3Fh Read only 7 6 5 Autoswitch 4 3 2 Reserved 1 0 Video standard [2:0] Autoswitch mode: 0 = Stand-alone (forced video standard) mode 1 = Autoswitch mode Video standard [2:0]: CVBS and S-video 000 = Reserved 001 = (M, J) NTSC 010 = (B, D, G, H, I, N) PAL 011 = (M) PAL 100 = (Combination-N) PAL 101 = NTSC 4.
Functional Description 2.11.39 GPIO Input 2 Register Subaddress 41h Read only 7 6 5 4 3 2 1 0 GPIO AVID GLCO VS HS FID C_9 C_8 GPIO input terminal status: 0 = Input is a low. 1 = Input is a high. AVID input terminal status: 0 = Input is a low. 1 = Input is a high. GLCO input terminal status: 0 = Input is a low. 1 = Input is a high. VS input terminal status: 0 = Input is a low. 1 = Input is a high. HS input status: 0 = Input is a low. 1 = Input is a high.
Functional Description 2.11.40 AFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h 7 6 5 4 3 2 CGAIN 1 [3:0] 1 0 Reserved CGAIN 1 [3:0]: Coarse_Gain = 0.5 + (CGAIN 1)/10, where 0 ≤ CGAIN 1 ≤ 15 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.5 2.
Functional Description 2.11.42 AFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h 7 6 5 4 3 2 CGAIN 3 [3:0] 1 0 Reserved CGAIN 3 [3:0]: Coarse_Gain = 0.5 + (CGAIN 3)/10, where 0 ≤ CGAIN 3 ≤ 15 This register works only in the manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.
Functional Description 2.11.44 AFE Fine Gain for Pb Register Subaddress 4Ah−4Bh Default 900h Subaddress 7 6 5 4 4Ah 3 2 1 0 FGAIN 1 [7:0] 4Bh Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component Pb. Fine_Gain = (1/2048) * FGAIN 1, where 0 ≤ FGAIN 1 ≤ 4095 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.
Functional Description 2.11.47 AFE Fine Gain for CVBS_Luma Register Subaddress 50h−51h Default 900h Subaddress 7 6 5 4 50h 3 2 1 0 FGAIN 4 [7:0] 51h Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: This fine gain applies to CVBS or S-video luma (see AFE fine gain for Pb register, Section 2.11.44). This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.
Functional Description 2.11.49 F-bit and V-bit Control 1 Register Subaddress 69h Default 00h 7 6 5 Reserved 4 3 2 VPLL Adaptive Reserved 1 0 F-bit mode [1:0] VPLL: VPLL time constant control 0 = VPLL adapts the time constant to the input signal (default) 1 = VPLL time constants are fixed Adaptive: 0 = Enable F-bit and V-bit adaptation to detected lines per frame (default) 1 = Disable F-bit and V-bit adaptation to detected lines per frame F-bit mode [1:0]: 00 = Auto mode.
Functional Description 2.11.50 Back-End AGC Control Register Subaddress 6Ch Default 08h 7 6 5 4 Reserved 3 2 1 0 1 Peak Color Sync This register disables the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst, or composite peak) to decrement the front-end gain. For example, writing 0x09 to this register disables the back-end AGC whenever the front-end AGC uses the sync-height to decrement the front-end gain.
Functional Description 2.11.53 AGC White Peak Processing Register Subaddress 74h Default 00h 7 6 5 4 3 2 1 0 Luma peak A Reserved Color burst A Sync height A Luma peak B Composite peak Color burst B Sync height B Luma peak A: Use of the luma peak as a video amplitude reference for the back-end feed-forward type AGC algorithm. 0 = Enabled (default) 1 = Disabled Color burst A: Use of the color burst amplitude as a video amplitude reference for the back end.
Functional Description 2.11.54 F and V Bit Control Register Subaddress 75h Default 12h 7 6 Rabbit 5 Reserved 4 3 Fast lock 2 F and V [1:0] 1 0 Phase Det. HPLL Rabbit: Enable rabbit ear 0 = Disabled (default) 1 = Enabled Fast lock: Enable fast lock where vertical PLL is reset and a 2-second timer is initialized when vertical lock is lost; during time-out the detected input VSYNC is output.
Functional Description 2.11.55 VCR Trick Mode Control Register Subaddress 76h Default 8Ah 7 6 5 4 Switch header 3 2 1 0 Horizontal shake threshold [6:0] Switch header: When in VCR trick mode, the header noisy area around the head switch is skipped. 0 = Disabled 1 = Enabled (default) Horizontal shake threshold [6:0]: 000 0000 = Zero threshold 000 1010 = 0Ah (default) 111 1111 = Largest threshold 2.11.
Functional Description 2.11.59 Analog Output Control 1 Register Subaddress 7Fh Default 00h 7 6 5 4 3 Reserved 2 1 0 AGC enable Input select Analog Output enable AGC enable: 0 = Enabled (default) 1 = Disabled, manual gain mode (see Section 2.12.10) Input select: 00 = Input selected by TVP5147M1 decoder, (see Section 2.11.1) (default) 01 = Input selected manually (see Section 2.12.10) Analog output enable: 0 = VI_1_A is input (default). 1 = VI_1_A is analog video output. 2.11.
Functional Description 2.11.63 Status Request Register Subaddress 97h Default 00h 7 6 5 4 3 2 1 0 Reserved Capture Capture: Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count registers. Since this capture is not immediate, it is necessary to check for completion of the capture by reading the capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor.
Functional Description 2.11.
Functional Description 2.11.67 VDP TTX Filter Control Register Subaddress BBh Default 00h 7 6 5 Reserved 4 3 Filter logic [1:0] 2 1 0 Mode TTX filter 2 enable TTX filter 1 enable Filter logic [1:0]: Allow different logic to be applied when combining the decision of filter 1 and filter 2 as follows: 00 = NOR (default) 01 = NAND 10 = OR 11 = AND Mode: indicates which teletext mode is in use.
Functional Description 1P1[3] D1[3] 1M1[3] 1P1[2] D1[2] 1M1[2] 1P1[1] D1[1] 1M1[1] 1P1[0] D1[0] 1M1[0] NIBBLE 1 D2[3:0] NIBBLE 2 1P2[3:0] 1M2[3:0] PASS 1 D3[3:0] 1P3[3:0] Filter 1 Enable NIBBLE 3 00 1M3[3:0] D4[3:0] 01 NIBBLE 4 1P4[3:0] PASS 1M4[3:0] 10 D5[3:0] 1P5[3:0] NIBBLE 5 11 1M5[3:0] 2 Filter Logic FILTER 1 D1..D5 PASS 2 FILTER 2 2P1..2P5 2M1..2M5 Filter 2 Enable Figure 2−19. Teletext Filter Function 2.11.
Functional Description 2.11.69 VDP FIFO Interrupt Threshold Register Subaddress BDh Default 80h 7 6 5 4 3 2 1 0 Threshold [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value. NOTE: 1 word equals 2 bytes. 2.11.
Functional Description 2.11.73 VDP Pixel Alignment Register Subaddress C2h−C3h Default 01Eh Subaddress 7 6 5 4 C2h 3 2 1 0 Pixel alignment [7:0] C3h Reserved Pixel alignment [9:8] Pixel alignment [9:8]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the program from one line standard to the next line standard, for example, the previous line of teletext to the next line of closed caption.
Functional Description 2.11.77 VDP Full Field Enable Register Subaddress D9h Default 00h 7 6 5 4 3 2 1 0 Reserved Full field enable Full field enable: 0 = Disabled full field mode (default) 1 = Enabled full field mode This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh.
Functional Description 2.11.81 FIFO Read Data Register Subaddress E2h Read only 7 6 5 4 3 2 1 0 FIFO read data [7:0] FIFO read data [7:0]: This register is provided to access VBI FIFO data through the I2C interface. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO.
Functional Description CC F1: CC field 1 data available unmasked 0 = Not available 1 = Available Line: Line number interrupt unmasked 0 = Not available 1 = Available The host interrupt raw status 0 and 1 registers represent the interrupt status without applying mask bits. 2.11.
Functional Description VPS: VPS data available masked 0 = Not available 1 = Available VITC: VITC data available masked 0 = Not available 1 = Available CC F2: CC field 2 data available masked 0 = Not available 1 = Available CC F1: CC field 1 data available masked 0 = Not available 1 = Available Line: Line number interrupt masked 0 = Not available 1 = Available The interrupt status 0 and 1 registers represent the interrupt status after applying mask bits.
Functional Description 2.11.
Functional Description 2.11.
Functional Description Line: Line number interrupt clear 0 = Disabled (default) 1 = Clear bit 0 (line interrupt available) in the interrupt status 0 register at subaddress F2h The host interrupt clear 0 and 1 registers are used by the external processor to clear the interrupt status bits in the host interrupt status 0 and 1 registers. When no nonmasked interrupts remain set in the registers, the external interrupt terminal also becomes inactive. 2.11.
Functional Description 2.12 VBUS Register Definitions 2.12.1 VDP Closed Caption Data Register Subaddress 80 051Ch−80 051Fh Read only Subaddress 7 6 5 4 3 80 051Ch Closed caption field 1 byte 1 80 051Dh Closed caption field 1 byte 2 80 051Eh Closed caption field 2 byte 1 80 051Fh Closed caption field 2 byte 2 2 1 0 These registers contain the closed caption data arranged in bytes per field. 2.12.
Functional Description 2.12.3 VDP VITC Data Register Subaddress 80 052Ch−80 0534h Read only Subaddress 7 6 5 4 3 80 052Ch VITC frame byte 1 80 052Dh VITC frame byte 2 80 052Eh VITC seconds byte 1 80 052Fh VITC seconds byte 2 80 0530h VITC minutes byte 1 80 0531h VITC minutes byte 2 80 0532h VITC hours byte 1 80 0533h VITC hours byte 2 80 0534h VITC CRC byte 2 1 0 These registers contain the VITC data. 2.12.
Functional Description 2.12.
Functional Description 2.12.
Functional Description 2.12.
Functional Description 2.12.10 Analog Output Control 2 Register Subaddress A0 005Eh Default B2h 7 6 Reserved Reserved 5 4 3 2 Input Select [1:0] 1 0 Gain [3:0] Analog input select [1:0]: These bits are effective when manual input select bit is set to 1 at subaddress 7Fh, bit 1. 00 = 01 = 10 = 11= CH1 selected CH2 selected CH3 selected CH4 selected (default) Analog output PGA gain [3:0]: These bits are effective when analog output AGC is set to 1 at subaddress 7Fh, bit 2.
Electrical Specifications 3 Electrical Specifications 3.1 Absolute Maximum Ratings† Supply voltage range: IOVDD to I/O GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2 V A33VDD (see Note 1) to A33GND (see Note 2) . . . . . . . . . . . . . . . . −0.3 V to 3.6 V A18VDD (see Note 3) to A18GND (see Note 4) . . . . . . . . . . . . . .
Electrical Specifications 3.3 Electrical Characteristics For minimum/maximum values: IOVDD = 3 V to 3.6 V, DVDD = 1.65 V to 1.95 V, AVDD33 = 3 V to 3.6 V, AVDD18 = 1.65 V to 1.95 V, TA = 0°C to 70°C For typical values: IOVDD = 3.3 V, DVDD = 1.8 V, AVDD33 = 3.3 V, AVDD18 = 1.8 V, TA = 25°C 3.3.1 DC Electrical Characteristics (see Note 1) PARAMETER TEST CONDITIONS MIN TYP CVBS 6 S-video 6 IDDIO(D) 3.3-V IO digital supply current IDD(D) 1.8-V digital supply current IDD33(A) 3.
Electrical Specifications 3.3.3 Timing 3.3.3.1 Clocks, Video Data, Sync Timing TEST CONDITIONS (see NOTE 1) PARAMETER Duty cycle DATACLK t1 t2 High time, DATACLK t3 t4 Fall time, DATACLK 90% to 10% Rise time, DATACLK 10% to 90% MIN TYP MAX 45% 50% 55% UNIT 18.5 Low time, DATACLK ns 18.5 t5 Output delay time NOTE 1: CL = 15 pF ns 4 ns 4 ns 10 ns t2 t1 VOH DATACLK VOL t3 t4 VOH Y, C, AVID, VS, HS, FID Valid Data Valid Data VOL t5 Figure 3−1.
Electrical Specifications 82 TVP5147M1PFP SLES140A—March 2007
Example Register Settings 4 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5147M1 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 4.1 Example 1 4.1.
Example Register Settings I2C register address 00h = Input select register I2C data 46h = Sets luma to VI_2_C and chroma to VI_1_C I2C register address 04h = Autoswitch mask register I2C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch I2C register address 08h = Luminance processing control 3 register I2C data 00h = Optimizes the trap filter selection for NTSC and PAL I2C register address 0Eh = Chrominance processing control 2 register I2C data 04h = Optimizes the chrominance filter selec
Example Register Settings I2C register address 00h = Input select register I2C data 95h = Sets Pb to VI_1_B, Y to VI_2_B, and Pr to VI_3_B I2C register address 04h = Autoswitch mask register I2C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch I2C register address 08h = Luminance processing control 3 register I2C data 00h = Optimizes the trap filter selection for NTSC and PAL I2C register address 0Eh = Chrominance processing control 2 register I2C data 04h = Optimizes the chrominance filt
Example Register Settings 86 TVP5147M1PFP SLES140A—March 2007
Application Information 5 Application Information 5.1 Application Example C0 FID C1 C2 VS/VBLK 2.2 kΩ HS/CS A3.3VDD XTAL2 A1.8VDD 0.1 µF (2) 1 kΩ VI_1_A 75 Ω 22 kΩ VI_1A VI_1B VI_1C 75 Ω (3) 1 2 0.1 µF (3) 0.1 µF (2) 0.1 µF (3) VI_2A VI_2B VI_2C 75 Ω (3) 0.1 µF (3) VI_3A VI_3B VI_3C 75 Ω (3) 0.1 µF (3) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 63 62 61 0.
Application Information 5.2 Designing With PowerPADt Devices The TVP5147 device is housed in a high-performance, thermally enhanced, 80-terminal PowerPAD package (TI package designator: 80PFP). Use of the PowerPAD package does not require any special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
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