TSB12LV26 OHCIĆLynx PCIĆBased IEEE 1394 Host Controller Data Manual 2000 Bus Solutions
Printed in U.S.A.
TSB12LV26 OHCI-Lynx PCI-Based IEEE 1394 Host Controller Data Manual Literature Number: SLLS366A March 2000 Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Contents Section 1 2 3 4 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
5 6 7 iv 4.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 7.5 Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure Title Page 2–1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 3–1 TSB12LV26 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 5–1 GPIO2 and GPIO3 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 Title Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . .
4–10 4–11 4–12 4–13 4–14 4–15 4–16 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 4–26 4–27 4–28 4–29 4–30 4–31 6–1 6–2 viii Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . . Isochronous Receive Channel Mask Low Register Description . . . . . . . . Interrupt Event Register Description . . . . . .
1 Introduction 1.1 Description The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
1.3 Related Documents • 1394 Open Host Controller Interface Specification 1.0 • P1394 Standard for a High Performance Serial Bus (IEEE 1394-1995) • P1394a Draft Standard for a High Performance Serial Bus (Supplement) • PC 99 Design Guide • PCI Bus Power Management Interface Specification (Revision 1.0) • PCI Local Bus Specification (Revision 2.2) • Serial Bus Protocol 2 (SBP–2) 1.
2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to each terminal in the package. Table 2–1 is a listing of signal names arranged in terminal number order, and Table 2–2 lists terminals in alphanumeric order by signal names. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 REG18 PHY_LPS PHY_LINKON PHY_LREQ 3.3 VCC PHY_SCLK GND PHY_CTL0 PHY_CTL1 3.
Table 2–1. Signals Sorted by Terminal Number 2–2 NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. 1 GND 26 PCI_AD25 51 PCI_SERR 76 TERMINAL NAME PCI_RST 2 GPIO2 27 PCI_AD24 52 PCI_PAR 77 CYCLEOUT 3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN 4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 REG_EN 5 SDA 30 GND 55 31 PCI_AD23 56 81 3.3 VCC PHY_DATA7 7 VCCP PCI_CLKRUN 3.
Table 2–2. Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
Table 2–4. PCI System Terminals TERMINAL NAME NO. I/O DESCRIPTION G_RST 10 I Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB12LV26.
Table 2–5. PCI Address and Data Terminals TERMINAL NAME PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 NO. 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 I/O DESCRIPTION I/O PCI address/data bus.
Table 2–6. PCI Interface Control Terminals TERMINAL NAME NO. I/O DESCRIPTION PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 65 53 41 28 I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle PCI_C/BE3–PCI_C/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. PCI_CLKRUN 7 I/O Clock run. This terminal provides clock control through the PCI_CLKRUN protocol.
Table 2–7. IEEE 1394 PHY/Link Terminals TERMINAL NAME NO. I/O DESCRIPTION PHY_CTL1 PHY_CTL0 92 93 I/O PHY-link interface control. These bidirectional signals control passage of information between the two devices. The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request (PHY_LREQ). PHY_DATA7 PHY_DATA6 PHY_DATA5 PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATA0 81 82 84 85 86 88 89 90 I/O PHY-link interface data.
2–8
3 TSB12LV26 Controller Programming Model This section describes the internal registers used to program the TSB12LV26. All registers are detailed in the same format: a brief description for each register, followed by the register offset and a bit table describing the reset state for each register.
PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt & CLKRUN GPIOs MISC Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA & Response Resp Timeout PCI Host Bus Interface Central Arbiter & PCI Initiator SM PHY Register Access & Status Monitor Request Filters Link Transmit Receive Acknowledge Cycle Start Generator & Cycle Monitor Link Receive Receive FIFO ISO Receive Contexts Figure 3–1.
3.1 PCI Configuration Registers The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers. Table 3–2.
3.3 Device ID Register The device ID register contains a value assigned to the TSB12LV26 by Texas Instruments. The device identification for the TSB12LV26 is 8020h. Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 1 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 1 0 0 0 0 0 Device ID Register: Type: Offset: Default: Device ID Read-only 02h 8020h 3.
3.5 Status Register The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3–4 for a complete description of the register contents.
3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV26 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3–5 for a complete description of the register contents.
3.8 Header Type and BIST Register The header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. See Table 3–7 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Header type and BIST Read-only 0Eh 0000h Table 3–7.
3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See the OHCI Base Address Register, Section 3.9, for bit field details.
3.12 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. The TSB12LV26 configuration header double-words at offsets 44h and 48h provide the power management registers. This register is read-only and returns 44h when read.
3.14 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15–8 of the latency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4.
3.16 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. See Table 3–13 for a complete description of the register contents.
3.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB12LV26 related to PCI power management. See Table 3–14 for a complete description of the register contents.
3.18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3–15 for a complete description of the register contents.
3.20 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–17 for a complete description of the register contents.
3.21 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial ROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set. See Table 3–18 for a complete description of the register contents.
Table 3–18. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION Enable acceleration enhancements. OHCI-Lynx compatible. When set to 1, this bit notifies the PHY that the link supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. 1 enab_accel R/W 0 RSVD R Reserved. Bit 0 returns 0 when read. 3.
3.23 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–20 for a complete description of the register contents.
3–18
4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function. This section provides the register interface and bit descriptions.
Table 4–1.
Table 4–1.
4.1 OHCI Version Register This register indicates the OHCI version support, and whether or not the serial ROM is present. See Table 4–2 for a complete description of the register contents.
4.2 GUID ROM Register The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register (OHCI offset 00h, see Section 4.1) is set. See Table 4–3 for a complete description of the register contents.
4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4 for a complete description of the register contents.
4.5 CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource.
4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4–6 for a complete description of the register contents.
4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a complete description of the register contents.
4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be changed.
4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents.
4.14 Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4–9 for a complete description of the register contents.
4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4–10 for a complete description of the register contents.
4.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2-Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31–11 are read/write accessible. Reserved bits 10–0 are read-only and return 0s when read.
4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4–12 for a complete description of the register contents.
Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE 6 isoChannel38 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38. DESCRIPTION 5 isoChannel37 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37. 4 isoChannel36 RSC When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.
4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.
Table 4–14. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 17 busReset RSCU Indicates that the PHY chip has entered bus reset mode. 16 selfIDcomplete RSCU A selfID packet stream has been received. It is generated at the end of the bus initialization process. This bit is turned off simultaneously when bit 17 (busReset) is turned on.
4.22 Interrupt Mask Register The interrupt mask set/clear register is used to enable the various TSB12LV26 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and VendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4–14. See Table 4–15 for a description of bits 31 and 30.
4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.
4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the event register bits detailed in Table 4–16.
4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section 4.
4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4–18 for a complete description of the register contents.
4.28 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB12LV26. It contains controls for the receiver and cycle timer. See Table 4–19 for a complete description of the register contents.
4.29 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the NodeNumber field (bits 5–0) is referred to as the node ID. See Table 4–20 for a complete description of the register contents.
4.30 PHY Layer Control Register The PHY layer control register is used to read or write a PHY register. See Table 4–21 for a complete description of the register contents.
4.31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 is cycle master, this register is transmitted with the cycle start message. When the TSB12LV26 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
4.32 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued.
Table 4–23. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If this bit is set for local bus node number 50, then asynchronous requests received by the TSB12LV26 from that node are accepted. 17 asynReqResource49 RSC If this bit is set for local bus node number 49, then asynchronous requests received by the TSB12LV26 from that node are accepted.
4.33 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 4–24 for a complete description of the register contents.
4.34 Physical Request Filter High Register The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register.
Table 4–25. Physical Request Filter High Register Description (Continued) BIT 4–32 FIELD NAME TYPE DESCRIPTION 19 physReqResource51 RSC If this bit is set for local bus node number 51, then physical requests received by the TSB12LV26 from that node are handled through the physical request context. 18 physReqResource50 RSC If this bit is set for local bus node number 50, then physical requests received by the TSB12LV26 from that node are handled through the physical request context.
4.35 Physical Request Filter Low Register The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register.
4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. It returns all 0s when read.
4.37 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4–27 for a complete description of the register contents.
4.38 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables the context by setting the asynchronous context control register (see Section 4.37) bit 15 (run). See Table 4–28 for a complete description of the register contents.
4.39 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,…, 7). See Table 4–29 for a complete description of the register contents.
4.40 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register (see Section 4.39) bit 15 (run). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7).
Table 4–30. Isochronous Receive Context Control Register Description (Continued) BIT 29 FIELD NAME cycleMatchEnable TYPE DESCRIPTION RSCU When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24–12) in the isochronous receive context match register (see Section 4.43) matches the 13-bit cycleCount field in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits in this register.
4.42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous receive context by setting the isochronous receive context control register (see Section 4.41) bit 15 (run). The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
4.43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specified cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4–31 for a complete description of the register contents.
4–42
5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. Figure 5–1 shows the logic diagram for GPIO2 and GPIO3 implementation. GPIO Read Data GPIO Port GPIO Write Data D Q GPIO_Invert GPIO Enable Figure 5–1.
5–2
6 Serial ROM Interface The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial ROM. The TSB12LV26 communicates with the serial ROM via the 2-wire serial interface. After power-up the serial interface initializes the locations listed in Table 6–1. While the TSB12LV26 is accessing the serial ROM, all incoming PCI slave accesses are terminated with retry status.
Table 6–2. Serial ROM Map BYTE ADDRESS BYTE DESCRIPTION 00 PCI maximum latency (0h) 01 PCI vendor ID 02 PCI vendor ID (msbyte) 03 PCI subsystem ID (lsbyte) 04 05 6–2 PCI_minimum grant (0h) PCI subsystem ID [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD [4] RSVD [3] RSVD [2] Link_enhancementControl.
7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Recommended Operating Conditions OPERATION MIN NOM MAX UNIT 3.3 V 3 3.3 3.6 V 3.3 V 3 3.3 3.6 5V 4.5 5 5.5 3.3 V 0.475 VCCP VCCP 5V 2 VCCP PHY interface 2 VCCP Miscellaneous‡ 2 VCCP 3.3 V 0 0.325 VCCP 5V 0 0.8 PHY interface 0 0.8 Miscellaneous‡ 0 0.
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) TEST CONDITIONS OPERATION VOH High-level output voltage PCI IOH = – 0.5 mA IOH = – 2 mA PHY interface IOH = – 4 µA IOH = – 8 mA Miscellaneous‡ IOH = – 4 mA IOL = 1.5 mA PCI VOL† Low-level output voltage IOL = 6 mA IOL = 4 mA PHY interface MIN MAX 0.9 VCC 2.4 V 2.8 VCC – 0.6 VCC – 0.6 0.1 VCC 0 0.55 IOZ 3-state output high-impedance Output pins 3.
7–4
8 Mechanical Information The TSB12LV26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the PZ package. PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
8–2
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
