TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 • • • • • • • • • • • • • • • IEEE 802.5 and IBM Token-Ring Network Compatible IEEE 802.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 pinout The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 description The TMS380C26 is a single-chip network communications processor (commprocessor) that supports token ring, or Ethernet Local Area Networks (LANs). Either token ring at data rates of 16 Mbps or 4 Mbps, or Ethernet at a data rate of 10 Mbps, can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 block diagram and signal descriptions TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical layer circuitry. As a rule of thumb in the pin nomenclature and descriptions that follow, pin names starting with the letter S attach to the host system bus and pin names starting with the letter M attach to the local memory bus. Active-low signals have names with overbars, e.g., SCS.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions PIN NAME BTSTRP NO. 23 I/O IN DESCRIPTION Bootstrap. The value on this pin is loaded into the BOOT bit of the SIFACL register at reset (i.e., when the SRESET pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value. This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME MAXPH NO. 130 I/O I/O DESCRIPTION Local Memory Extended Address and Parity High Byte. For the first quarter of a memory cycle this signal carries the extended address bit (AX1); for the second quarter of a memory cycle this signal carries the extended address bit (AX0); and for the last half of the memory cyle this signal carries the parity bit for the high data byte.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME NO. I/O DESCRIPTION Memory Output Enable. This signal is used to enable the outputs of the DRAM memory during a read cycle. This signal is high for EPROM or BIA ROM read cycles. MOE 118 OUT H = Disable DRAM outputs. L = Enable DRAM outputs. MRAS 115 OUT Row Address Strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME PRTYEN NO. 22 I/O IN DESCRIPTION Parity Enable. The value on this pin is loaded into the PEN bit of the SIFACL register at reset (i.e., when the SRESET pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value. This bit enables parity checking for the local memory. H = Local memory data bus checked for parity (see Note 1).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Intel Mode (SI/M = H) PIN NAME NO. SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 73 72 71 70 69 68 64 63 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 54 53 52 49 48 47 46 45 SALE 43 I/O I/O DESCRIPTION System Address/Data Bus—high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Intel Mode (SI/M = H) PIN NAME SDDIR NO. 38 I/O DESCRIPTION OUT System Data Direction. This output provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the TMS380C26).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Intel Mode (SI/M = H) PIN NAME SRAS/SAS NO. 39 I/O I/O DESCRIPTION System Memory Address Strobe (see Note 3). This pin used to latch the SCS, SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied to the SALE output of the System Bus.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Intel Mode (SI/M = H) PIN NAME SYNCIN S8/SHALT NO. I/O 108 IN 32 IN DESCRIPTION Reserved. This signal must be left unconnected (see Note 1). System 8/16-bit bus select. This pin selects the bus width used for communications through the system interface.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Motorola Mode (SI/M = L) PIN NAME NO. SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 73 72 71 70 69 68 64 63 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 54 53 52 49 48 47 46 45 SALE 43 I/O I/O DESCRIPTION System Address/Data Bus—high byte (see Note 1).These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Motorola Mode (SI/M = L) PIN NAME SDDIR NO. 38 I/O DESCRIPTION OUT System Data Direction. This output provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the TMS380C26).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) System Interface – Motorola Mode (SI/M = L) PIN NAME NO. I/O DESCRIPTION Upper Data Strobe (see Note 3). This pin serves as the active-low upper data strobe. This pin is an input during DIO and an output during DMA. SRD/SUDS 61 I/O H = Not valid data on SADH0-SADH7 lines. L = Valid data on SADH0-SADH7 lines. SRDY/SDTACK 60 I/O System Data Transfer Acknowledge (see Note 3).
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) Network Media Interface – Token-Ring Mode (TEST1 = H, TEST2 = H) PIN NAME DRVR DRVR NO. 89 88 I/O DESCRIPTION OUT Differential Driver Data Output. These pins are the differential outputs that send the TMS380C16 transmit data to the TMS38054 for driving onto the ring transmit signal pair. Frequency Acquisition Control.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) Network Media Interface – Ethernet Mode (TEST1 = L, TEST2 = H) I/O DESCRIPTION DRVR DRVR PIN NAME NO. 89 88 OUT These pins have no Ethernet function. In Ethernet Mode these pins are placed in their token ring reset state of DRVR = High, DRVR = Low. FRAQ/TXD 85 OUT Ethernet Transmit Data. This output signal provides the Ethernet physical layer circuitry with bit-rate from the TMS380C26.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME NO. I/O DESCRIPTION Network Select inputs. These pins are used to select the network speed and type to be used by the TMS380C26. These inputs should only be changed during adapter reset. TEST 0 TEST 1 TEST 2 79 78 77 IN IN IN TEST3 TEST4 TEST5 76 75 74 IN IN IN XFAIL 80 IN TEST0 TEST1 TEST2 L L H H X L H L H X H H H H 0 Description Reserved 16 Mbps token ring Ethernet (802.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME NO. I/O DESCRIPTION VSSL 17 83 IN Ground reference for digital logic. All VSS pins must be attached to the common system ground plane. VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 91 106 125 1 51 67 IN Ground connections for output buffers. All VSS pins must be attached to system ground plane.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 architecture The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF). The functionality of each block is described in the following sections.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 On every cycle the system interface compares all the system clocks to a reference clock. If any of the clocks become invalid, the TMS380C26 enters the slow clock mode, which prevents latchup of the TMS380C26. If the SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and then the TMS380C26 is placed in slow clock mode.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 The Protocol Handler contains many state machines which provide the following features: • • • • • • • • • Transmit and receive frames Capture tokens (token ring) Provide token-priority controls (token ring) Automatic retry of frame transmissions after collisions (Ethernet) Implement the Random Exponential Backoff algorithm (Ethernet) Manage the TMS380C26 buffer memory Provide frame address recognition (group, specific, functional, and
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Adapter-Internal Pointers for Token-Ring † ADDRESS >00.FFF8‡ >00.FFFA‡ >01.0A00 DESCRIPTION Pointer to software raw microcode level in chapter 0. Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0. Pointer to burned-in address in chapter 1. >01.0A02 Pointer to software level in chapter 1. >01.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Adapter-Internal Pointers for Ethernet † ADDRESS >00.FFF8‡ >00.FFFA‡ Software raw microcode level in chapter 0. DESCRIPTION >01.0A00 Pointer to burned-in address in chapter 1. Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0. >01.0A02 Pointer to software level in chapter 1. >01.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 User-Access Hardware Registers 808x 16-Bit Mode: (SI/M = 1, S8/SHALT = 0)† Normal Mode SBHE = 0 SRS2 = 0 Word Transfers Byte Transfers SRSX SRS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Pseudo-DMA Mode Active SBHE = 0 SRS2 = 0 SBHE = 0 SRS2 = 1 SBHE = 1 SRS2 = 0 SBHE = 0 SRS2 = 1 SBHE = 1 SRS2 = 0 SIFDAT MSB SIFDAT/INC MSB SIFADR MSB SIFCMD SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SIFDAT LSB SIFDAT/INC LSB SIFADR LSB SIFSTS SIFACL
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 SIF Adapter Control Register (SIFACL) The SIFACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Bit 6: SWHRQ — Current SHRQ Signal Value This bit contains the current value on the SHRQ/SBRQ pin when in Intel mode, and the inverse of the SHRQ/SBRQ pin when in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is requested.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Bit 12: SINTEN — System-Interrupt Enable This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26. The system interrupt request from the TMS380C26 is on the SINTR/SIRQ pin. The following equation shows how the SINTR/SIRQ pin is driven. The table also explains the results of the states.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 SIFACL Control for Pseudo-DMA Operation Pseudo-DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACL register control of pseudo-DMA operation is shown in Figure 3.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V Output voltage range . . . . . . . . . . .
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. These levels are compatible with TTL devices. Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 volts, and the level at which the signal is said to be low is 0.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Reference 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods OSCIN When CLKDIV = 1 OSCOUT MBCLK1† MBCLK2† † The MBCLK1 and MBCLK2 signals have no timing relationship to the OSCOUT signal. The MBCLK1 and MBCLK2 signals can start on any OSCIN rising edge, depending on when the memory cycle starts execution. Figure 5.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION timing parameters The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among the various signals. The parameters are numbered for convenience.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing NO. 100† 101†‡ 102†‡ 103 104 105 106† 107 108 109 110† 111† 117† 118† 119† 288† 289† PARAMETER MIN MAX UNIT tr(VDD) td(VDDH-SCKV) Rise time from 1.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 100 Minimun VDD High Level VDD 103 106 104 101 106 105 SBCLK 102 107 110 108 OSCIN 110 109 MBCLK1 111 MBCLK2 118 117 119 SRESET 288 289 S8/SHALT NOTE A: In order to represent the information on one figure, non-actual phase and timebase characteristics are shown. Please refer to specified parameters for precise information. Figure 6.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION M8 M1 M2 M4 M3 M5 M6 M7 M8 M1 1 tM 3 MBCLK1 4 6 2 1 5 7 3 MBCLK2 8 MAX0, MAX2, MROMEN 2 12 ADD/EN Address 9 MAXPH, MAXPL, MADL0–MADL7 13 Row Col 14 10 Address MADH0–MADH7 Status 11 129 MAL 120 NMI 121 Valid 126 MRESET Valid Figure 7.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: clocks, MRAS, MCAS, and MAL to ADDRESS tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAXPH, MAXPL, MADL0–MADL7 Row Column Row 16 Column 26 17 22 15 19 18 MRAS 21 20 24 23 MCAS 25 27 MAL 28 MAX0, MAX2, MROMEN 29 ADD/EN Address 21 30 31 20 MADH0–MADH7 Address Status Address Status 22 Figure 8.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: read cycle tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAX0, MAX2, MROMEN Address/ Enable Address Data/Parity 32 MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 Address/ Status Address Address 33 36 37 35 MRAS 38 39 40 MCAS 43 45 41 46 42 47 44 MOE 49a 48a 51a 52a 50a MBIAEN 49 51 48 52 MBEN 50 53 54 55 MDDIR Figure 9.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: write cycle tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAX0, MAX2, MROMEN Address/ Enable MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 Address Address ADD/STS Data/Parity Out MRAS 58 MCAS 60 65 63 64 MW 69 67 66 70 71 MBEN 72 73 MDDIR Figure 10.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: TMS380C26 releases control of bus tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 MBEN 75a 74a MDDIR 75 74 MAL 75 74 MBIAEN 77 75 76 74 MBRQ 78 MBGR Figure 12.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: TMS380C26 resumes control of bus tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MAX0, MAX2, MOROMEN 80 79 MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 80 79 MRAS 80 79 MCAS 80 79 MW 80 79 MOE 80 79 Figure 13.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 MBEN 80 79 MDDIR 80 79 MAL 80 79 MBIAEN 81 80 79 82 MBRQ 83 MBGR Figure 14.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: external bus master read from TMS380C26 tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 84 85 Address In Address In MAX0, MAX2 86 89 87 88 91 90 MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 Data/Parity Address In 92 Address In 93 MDDIR 94 95 MACS Figure 15.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: external bus master write to TMS380C26 NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: DRAM refresh timing tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION XMATCH and XFAIL timing tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. PARAMETER 127 Delay from status bit 7 high to XMATCH and XFAIL recognized 128 Pulse duration of XMATCH or XFAIL high MADH7 MIN 7tM 50 MAX UNIT ns ns Status Bit 7 127 128 XMATCH, XFAIL Figure 18.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring — ring interface timing No.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring — transmitter timing (see Figure 20) NO. PARAMETER MIN 159 Delay from DRVR rising edge (1.8 V) to DRVR falling edge (1.0 V) or DRVR falling edge (1.0 V) to DRVR rising edge (1.8 V) TYP MAX ±2 ns ±1.5 ns 160† 161† Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DRVR rising edge (1.8 V) (see Note 15) Delay from RCLK (or PXTALIN) falling edge (1.0 V) to DRVR falling edge (1.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of clock signals NO. PARAMETER MIN 300 CLKPHS Pulse duration of TXC 45 301 CLKPER Cycle time of TXC 95 TYP MAX UNIT ns 1000 ns 301 300 2.4 V TXC 0.45 V 300 Figure 21. Ethernet Timing Of Clock Signals ethernet timing of XMIT signals NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — start of frame NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — end of frame NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — no RXC NO. 330 PARAMETER NORXC MIN TYP MAX Time with no clock pulse on RXC, when CRS is high (see Note 19) 2 UNIT µs NOTE 19: If NORXC is exceeded local clock failure circuitry may become activated, resetting the device. CRS ”1” 330 RXC Figure 25. Ethernet Timing of RCV Signals — No RXC ethernet timing of XMIT signals NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of XMIT signals NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x DIO read timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0–SRS2, SBHE Valid Valid (see Note A) 264 265 268 SRAS 256 266a 267 SIACK 272a 273a SWR 273a 272a SRD 273a 272a 286 (High) SDDIR 279 282R 283R SDBEN 275 282a SRDY† 255 HI-Z 261 260 SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note B) HI-Z 261a 259 HI-Z Output Data Valid HI-Z † When the TMS380C26 begins to drive SDBEN inactive, it has already latched the write data in
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x DIO write timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0–SRS2, SBHE Valid 264 268 265 SRAS 256 266a 267 SIACK 273a 272a SWR 273a SRD 272a 286 272a 273a 281 280 SDDIR 281a (High) 282W 283W SDBEN † 279 276 275 SRDY 282b 255 HI-Z HI-Z 263 262 SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) Data HI-Z HI-Z † When the TMS380C26 begins to drive SDBEN inactive, it has already latched the write data internally.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x interrupt acknowledge timing – first SIACK pulse NO. PARAMETER MIN 286 Pulse duration, SIACK high between DIO accesses (see Note 21) 287 Pulse duration, SIACK low on first pulse of two pulses MAX UNIT 55 ns 62.5 ns NOTE 21: The “inactive” chip select is SIACK in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge cycles.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0–SRS2, SBHE Only SCS needs to be inactive. All others are Don’t Care. SIACK 272a 273a 272a 273a 272a 273a SWR SRD SDDIR (High) 279 282R 283R SDBEN 275 276 SRDY† 282a 255 HI-Z HI-Z 261 259 SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) 260 261a HI-Z Output Data Valid † SRDY is an active-low bus ready signal. It must be asserted before data output.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing, SIF takes control NO.
Bus Exchange (T4) SIF Inputs: SIF Master I1 I2 TX T1 SBCLK 208a SBBSY, SHLDA SIF Outputs: 208b 230 SHRQ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 241 SRD, SWR 212 241a SBHE 212 SADH0–SADH7, SADL0–SADL7, SPH, SPL Address Valid 224c Write SDDIR Read 224a SOWN (see Note A) NOTE A: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled. Figure 32.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode DMA read timing NO.
TX TWAIT V T2 T1 T3 T4 T1 SBCLK HI-Z SRAS 212 SBHE (see Note B) Valid (High) SWR 227R 223R 231 SRD (see Note A) 215 216 218 217 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 217 SXAL 226 216 216a 215 SALE 212 233 SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note C) 214 218 212 Address Extended Address 207a 205 233 206 Data 229 Address 247† 218 208a 207b 208b 225R SRDY 237R SDBEN (see Note A) SDDIR Low † If parameter 208A is not met then valid data must be present before SRDY
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode DMA write timing NO.
TX T1 TWAIT V T2 T3 T4 T1 SBCLK 212 SBHE (see Note A) Valid (HIGH) SRD 223W 227W SWR 232 216 217 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 215 217 SXAL 216 215 216a SALE 212 212 SADL0–SADH7, SADH0–SADL7, SPH, SPL (see Note B) 218 233 233 218 221 219 Address Output Data Extended Address 208a SRDY 225W 237W SDBEN SDDIR 208b 225WH (HIGH) NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA. B.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing, SIF returns control NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus release timing NO. PARAMETER MIN MAX UNIT 208a Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee recognition 15 ns 208b Hold of asynchronous input SBRLS low after SBCLK low to guarantee recognition 15 ns 208c Hold of SBRLS low after SOWN high 0 ns T(W or 2) T3 T4 T1 T2 SBCLK 208a SBRLS (see Note A) 208b SOWN 208c NOTES: A.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO read timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0, SRS1 Valid 267 268 SIACK 273a SRNW 272 273 SUDS, SLDS 286 SDDIR (High) 279 282R 283R SDBEN 276 SDTACK† HI-Z 275 282a 255 HI-Z 261 259 260 261a SADH0–SADH7, SADL0–SADL7, SPH, SPL HI-Z Output Data Valid † SDTACK is an active-low bus ready signal. It must be asserted before data output. Figure 37.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO write timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX, SRS0, SRS1 Valid 267 268 SIACK 273a 272 273 SRNW 286 272a SUDS, SLDS (see Note A) 273a 281 280 281a SDDIR (High) 282W 283W SDBEN‡ 279 276 275 255 SDTACK† HI-Z HI-Z 263 282b SADH0–SADH7, SADL0–SADL7, SPH, SPL 262 (see Note 36) HI-Z Data HI-Z † SDTACK is an active-low bus ready signal. It must be asserted before data output.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx interrupt acknowledge cycle timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0, SRS1, SBHE Only SCS needs to be Inactive. All Others are Don’t Care. 267 SIACK 272a 286 SRNW 273a SLDS 286 SDDIR (High) 279 282R 283R SDBEN 275 276 282a SDTACK† 255 HI-Z 259 HI-Z 261 260 261a SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) HI-Z Output Data Valid HI-Z † SDTACK is an active-low bus ready signal. It must be asserted before data output.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing, SIF takes control NO.
(T4) I1 SIF Master I2 TX T1 T2 SBCLK 208b 208a SBGR SBERR, SDTACK, SBBSY SIF Outputs: 230 230 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 SBRQ (see Note A) 208a 208b SAS, SLDS, SUDS 241 Output (Input) 241 READ SRNW WRITE 212 SADH0–SADH7, SADL0–SADL7, SPH, SPL HI-Z SIF 224c WRITE SDDIR READ 224a SOWN (see Note B) 241a NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA read timing NO.
T4 TX T1 S1 T2 S2 S3 T3 S4 S5 T4 S6 T1 S7 SBCLK 222 239 SAS (see Note A) 209 223R 210 239 SUDS, SLDS 209 218 217 (High) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 SRNW 216 217 215 SXAL 216 218 216a 215 SALE 229 212 233a 212 233 SADL0–SADH7, SADH0–SADL7, SPH, SPL 233 206 205 214 Address Data In 247† Extended Address 207a HI-Z 207b 208a SDTACK (see Notes B and C) 208b SDDIR 237R 225R SDBEN (see Note A) † If parameter 208a is not met, then valid data must be present befor
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA write timing NO.
T4 TX T1 T2 T3 T4 T1 SBCLK 222 211 223W 239 SAS 209 233a 243 SUDS, SLDS 218 216 211a 217 SRNW POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 Low 217 215 218 SXAL 216 216a 215 SALE 212 212 233 233 221 219 SADL0–SADH7, SADH0–SADL7, SPL, SPH Address Output Data Extended Address 208a SDTACK (see Notes A and B) 208b 225W SDDIR 237W 225WH SDBEN NOTES: A. All VSS pins should be routed to minimize inductance to system ground. B.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing, SIF returns control NO.
T3 Bus Exchange I1 T4 User T1 I2 SBCLK SBGR SDTACK SIF Outputs: POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 230 SBRQ (see Note A) 220 240 SAS, SUDS, SLDS 240 223b READ HI-Z SRNW WRITE 220 SADH0–SADH7, SADL0–SADL7, SPH, SPL SIF HI-Z 224d WRITE SDDIR READ 224b SOWN NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus release and error timing NO.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION normal completion with delayed start† T1 T(W or 2) T3 TH T4 T1 SBCLK SDTACK SBERR SHALT rerun cycle with delayed start† T1 T2 T3 T4 THB THE T1 SBCLK SDTACK SBERR SHALT SOWN † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms shown. Figure 45.
TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 MECHANICAL DATA JEDEC plastic leaded quad flat package (PQ suffix) Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and circuit performance characteristics remain stable when the devices are operated in high-humidity conditions.
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