TMS3320C5515 DSP System User's Guide Literature Number: SPRUFX5A October 2010 – Revised November 2010
SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Contents ....................................................................................................................................... 9 System Control ................................................................................................................. 13 1.1 Introduction ................................................................................................................. 13 1.1.1 Block Diagram ...............................................................................
www.ti.com List of Figures 1-1. Functional Block Diagram ................................................................................................ 13 1-2. DSP Memory Map 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 1-11. 1-12. 1-13. 1-14. 1-15. 1-16. 1-17. 1-18. 1-19. 1-20. 1-21. 1-22. 1-23. 1-24. 1-25. 1-26. 1-27. 1-28. 1-29. 1-30. 1-31. 1-32. 1-33. 1-34. 1-35. 1-36. 1-37. 1-38. 1-39. 1-40. 1-41. 1-42. 1-43. 1-44. 1-45. 1-46. 1-47. 4 ................................................................
www.ti.com 1-48. EMIF System Control Register (ESCR) [1C33h] ...................................................................... 76 1-49. EMIF Clock Divider Register (ECDR) [1C26h] ........................................................................
www.ti.com List of Tables 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 1-11. 1-12. 1-13. 1-14. 1-15. 1-16. 1-17. 1-18. 1-19. 1-20. 1-21. 1-22. 1-23. 1-24. 1-25. 1-26. 1-27. 1-28. 1-29. 1-30. 1-31. 1-32. 1-33. 1-34. 1-35. 1-36. 1-37. 1-38. 1-39. 1-40. 1-41. 1-42. 1-43. 1-44. 1-45. 1-46. 1-47. 6 ............................................................................................................................... .................................................................................
www.ti.com 1-48. Output Slew Rate Control Register (OSRCR) Field Descriptions ................................................... 66 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions ...................................................... 67 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions ...................................................... 68 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions ......................................................
List of Tables SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Preface SPRUFX5A – October 2010 – Revised November 2010 Read This First About This Manual This document describes various aspects of the TMS320C5515 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h.
Related Documentation From Texas Instruments www.ti.com SPRUFO4 — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) General-Purpose Input/Output (GPIO) User's Guide. This document describes the general-purpose input/output (GPIO) on the TMS320C5515/14/05/04/VC05/VC04 digital signal processor (DSP) devices. The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of an internal register.
Related Documentation From Texas Instruments www.ti.com SPRUGH5— TMS320C5505 DSP System User's Guide. This document describes various aspects of the TMS320C5505 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control. SPRUFX6— TMS320C5514 DSP System User's Guide.
Read This First SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Chapter 1 SPRUFX5A – October 2010 – Revised November 2010 System Control 1.1 Introduction The TMS320C5515 digital signal processor (DSP) contains a high-performance, low-power DSP to efficiently handle tasks required by portable audio, wireless audio devices, industrial controls, software defined radio, fingerprint biometrics, and medical applications.
Introduction www.ti.com 1.1.2 CPU Core The C55x CPU is responsible for performing the digital signal processing tasks required by the application. In addition, the CPU acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control.
Introduction www.ti.com Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output data is in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in the scratch buffer. The 32-bit input and output data consist of 16-bit real and 16-bit imaginary data. If only real data is used, the imaginary part can be zeroed.
System Memory • • • • 1.2 www.ti.com modes. Three 32-bit timers with 16-bit prescaler; one timer supports watchdog functionality. A USB 2.0 slave. A 10-bit successive approximation (SAR) analog-to-digital converter with touchscreen conversion capability. One real-time clock (RTC) with associated low power mode.
System Memory www.ti.com Figure 1-2.
System Memory www.ti.com Table 1-2. DARAM Blocks (continued) 1.2.1.2 Memory Block CPU Byte Address Range DMA/USB Controller Byte Address Range DARAM 6 00 C000h - 00 DFFFh 0001 C000h - 0001 DFFFh DARAM 7 00 E000h - 00 FFFFh 0001 E000h - 0001 FFFFh On-Chip Single-Access RAM (SARAM) The SARAM is located at the CPU byte address range 01 0000h - 04FFFFh and is composed of 32 blocks of 4K words each (see Table 1-3). Each SARAM block can perform one access per cycle (one read or one write).
System Memory www.ti.com 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM) The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform one access per cycle (one read or one write). ROM can be accessed by the internal program or data buses, but not the DMA buses.
Device Clocking www.ti.com pins for the load mode register command. During the mobile SDRAM initialization, the device issues the load mode register initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register. The extended mode register exists only in mSDRAM, and not in non-mSDRAM.
Device Clocking www.ti.com RTC_XO pins. RTC core (CVDDRTC) must be powered all the time but the 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h - 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins.
Device Clocking www.ti.com Figure 1-3. DSP Clocking Diagram CLKSEL CLKIN 1 0 CLKREF LS (1) System Clock Generator ST3_55[CLKOFF] 1 LS (1) (1) 32.
System Clock Generator www.ti.com 1.3.2 Clock Domains The device has many clock domains defined by individually disabled portions of the clock tree structure. Understanding the clock domains and their clock enable/disable control registers is very important for managing power and for ensuring clocks are enabled for domains that are needed.
System Clock Generator www.ti.com Figure 1-4. Clock Generator 0 CLKSEL LS 1 LS CLKREF 0 RTC Clock LS RTC_CLKOUT RTC_XI 32.768 KHz RTC_XO RTC OSC Reference Divider 0 1 SYSCLK 1 1 CLKIN PLL PLLIN PLLOUT Output Divider 0 CGCR4. [OUTDIVEN] CCR2. [SYSCLKSEL] CGCR2[RDBYPASS] RTC 1.4.2 Functional Description The following sections describe the multiplier and dividers of the clock generator. 1.4.2.
System Clock Generator www.ti.com When the PLL is powered up (PLL_PWRDN = 0), the PLL will start its phase-locking sequence. You must keep the clock generator in BYPASS MODE for at least 4 mS while the phase-locking sequence is ongoing. See Section 1.4.3.2 for more details on the PLL_MODE of the clock generator. 1.4.2.3 CLKOUT Pin For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the clock generator.
System Clock Generator 1.4.2.4 www.ti.com DSP Reset Conditions of the System Clock Generator The following sections describe the operation of the system clock generator when the DSP is held in reset state and the DSP is removed from its reset state. 1.4.2.4.1 Clock Generator During Reset During reset, the PLL_PWRDN bit of the clock generator control register 1 (CGCR1) is set to 1, and the PLL does not generate an output clock.
System Clock Generator www.ti.com 1.4.3.1.2 Register Bits Used in the BYPASS MODE Table 1-7 describes the bits of the clock generator control registers that are used in the BYPASS MODE. For detailed descriptions of these bits, see Section 1.4.4. Table 1-7. Clock Generator Control Register Bits Used In BYPASS MODE Register Bit Role in BYPASS MODE SYSCLKSEL Allows you to switch to the PLL or BYPASS MODES. PLL_PWRDN Allows you to power down the PLL. 1.4.3.1.
System Clock Generator www.ti.com Table 1-9. Clock Generator Control Register Bits Used In PLL Mode (continued) Register Bit Role in Bypass Mode RDRATIO Specifies the divider ratio of the reference divider. M Specify the multiplier value for the PLL. OUTDIVEN Determines whether the output divider is bypassed. ODRATIO Specifies the divider ratio of the output divider. 1.4.3.2.3 Frequency Ranges for Internal Clocks There are specific minimum and maximum frequencies for all the internal clocks.
System Clock Generator www.ti.com Table 1-11 shows programming examples for different PLL MODE frequencies. Table 1-11. Examples of Selecting a PLL MODE Frequency, When CLK_SEL=L RDBYPASS OUTDIVEN M RDRATIO ODRATIO 1 0 173h X X PLL Output Frequency 32.768KHz x (173h+4) = 12.288 MHz 1 1 E4Ah X 2 32.768KHz x (E4Ah + 4)/3 = 40.00 MHz 1 0 723h X X 32.768KHz x (723h + 4) = 60.00 MHz 1 0 8EDh X X 32.768KHz x (8EDh + 4) = 75.01 MHz 1 0 BE8h X X 32.768KHz x (BE7h + 4) = 100.
System Clock Generator 1.4.4.1 www.ti.com Clock Generator Control Register 1 (CGCR1) [1C20h] The clock generator control register 1 (CGCR1) is shown in Figure 1-6 and described in Table 1-13. Figure 1-6. Clock Generator Control Register 1 (CGCR1) [1C20h] 15 14 13 12 11 8 Reserved Reserved PLL_PWRDN M R/W-0 R/W-0 R/W-1 R/W-0 7 6 5 4 3 2 1 0 M R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-13.
System Clock Generator www.ti.com 1.4.4.3 Clock Generator Control Register 3 (CGCR3) [1C22h] The clock generator control register 3 (CGCR3) is shown in Figure 1-8 and described in Table 1-15. Figure 1-8. Clock Generator Control Register 3 (CGCR3) [1C22h] 15 0 INIT R/W-0806h LEGEND: R/W = Read/Write; -n = value after reset Table 1-15. Clock Generator Control Register 3 (CGCR3) Field Descriptions Bit Field Value 15-0 INIT 0x0806h 1.4.4.
System Clock Generator 1.4.4.5 www.ti.com Clock Configuration Register 1 (CCR1) [1C1Eh] The clock configuration register 1 (CCR1) is shown in Figure 1-10 and described in Table 1-17. Figure 1-10. Clock Configuration Register 1 (CCR1) [1C1Eh] 15 1 0 Reserved SDCLK_EN R-0 R/W-0 LEGEND: R = Read only; -n = value after reset Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions Bit Field 15-1 Value Reserved 0 Description 0 Reserved.
Power Management www.ti.com 1.5 Power Management 1.5.1 Overview In many applications there may be specific requirements to minimize power consumption for both power supply (and battery) and thermal considerations. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and, for digital CMOS circuits, scales roughly with clock frequency and the amount of computations being performed.
Power Management www.ti.com Table 1-20. DSP Power Domains Power Domains Description Real-Time Clock Power Domain (CVDDRTC) This domain powers the real-time clock digital circuits and oscillator pins ( RTC_XI, RTC_XO). Nominal supply voltage can be 1.05 V through 1.3 V. Note: This domain must be always powered for proper operation. This domain cannot be regulated internally, external regulation must be provided.
Power Management www.ti.com There are two distinct methods of clock gating. The first uses the ICR CPU register and the CPU's IDLE instruction. This method is used for the following domains: CPU, IPORT, DPORT, MPORT, XPORT & HWA. See Figure 1-3 for a diagram of these domains. In this method, the ICR is written with a value indicating the desired clock gating configuration and then (possibly much later) the IDLE instruction is executed.
Power Management www.ti.com 1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h] Table 1-21 describes the read/write bits of ICR, and Table 1-22 describes the read-only bits of ISTR. NOTE: To prevent an emulation lock up, idle requests to these domains may be overridden or ignored when an emulator is connected to the JTAG port of the DSP. Figure 1-12.
Power Management www.ti.com Figure 1-13. Idle Status Register (ISTR) [0002h] 15 10 9 8 Reserved HWAIS IPORTIS R-0 R-0 R-0 7 6 5 MPORTIS XPORTIS DPORTIS 4 Reserved 1 CPUIS 0 R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 1-22. Idle Status Register (ISTR) Field Descriptions Bit 15-10 9 8 7 6 5 4-1 0 Field Value Reserved 0 HWAIS Description Reserved. FFT hardware accelerator idle status bit. 0 Hardware accelerator is active.
Power Management www.ti.com Table 1-23. CPU Clock Domain Idle Requirements (continued) To Idle the Following Module/Port Requirements Before Going to Idle XPORT CPU CPUI must also be set. DPORT 1.5.3.1.3 Clock Configuration Process The clock configuration indicates which portions of the CPU clock domain will be idle, and which will be active. The basic steps to the clock configuration process are: 1. To idle MPORT, DMA controller, LCD DMA, and USB CDMA must not be accessing SARMA or DARAM.
Power Management www.ti.com 1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h] The peripheral clock gating configuration registers (PCGRC1 and PCGCR2) are used to disable the clocks of the DSP peripherals. In contrast to the idle control register (ICR), these bits take effect within 6 SYSCLK cycles and do not require an idle instruction. The peripheral clock gating configuration register 1 (PCGCR1) is shown in Figure 1-14 and described in Table 1-24. Figure 1-14.
Power Management www.ti.com Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Bit 6 Reserved 4 MMCSD0CG 2 1 0 Value I2CCG 5 3 40 Field I2C clock gate control bit. This bit is used to enable and disable the I2C peripheral clock. 0 Peripheral clock is active. 1 Peripheral clock is disabled. 0 Reserved, you must always write 1 to this bit. MMC/SD0 clock gate control bit. This bit is used to enable and disable the MMC/SD0 peripheral clock.
Power Management www.ti.com The peripheral clock gating configuration register 2 (PCGCR2) is shown in Figure 1-15 and described in Table 1-25. Figure 1-15. Peripheral Clock Gating Configuration Register 2 (PCGCR2) [1C03h] 15 8 Reserved R-0 7 6 5 4 3 2 1 0 Reserved ANAREGCG DMA3CG DMA2CG DMA1CG USBCG SARCG LCDCG R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-25.
Power Management www.ti.com 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah] You must execute a handshaking procedure before stopping the clock to the EMIF, USB, and UART. This handshake procedure ensures that current bus transactions are completed before the clock is stopped. The peripheral clock stop request/acknowledge register (CLKSTOP) enables this handshaking mechanism.
Power Management www.ti.com Table 1-26. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions (continued) Bit Field 1 Value EMFCLKSTPACK 0 Description EMIF clock stop acknowledge bit. This bit is set to 1 when the EMIF has acknowledged a request for its clock to be stopped. The EMIF clock should not be stopped until this bit is set to 1. 0 The request to stop the peripheral clock has not been acknowledged.
Power Management www.ti.com 1.5.3.4.1 Clock Configuration Process The clock configuration process for the USB clock domain consists of disabling the USB peripheral clock followed by disabling the USB on-chip oscillator. This procedure will completely shut off USB module, which does not comply with USB suspend/resume protocol. To set the clock configuration of the USB clock domain to idle follow these steps: 1. Set the SUSPENDM bit in FADDR register.
Power Management www.ti.com Table 1-27. USB System Control Register (USBSCR) Field Descriptions (continued) Bit Field 13 USBVBUSDET 12 Value USB VBUS detect enable. The USB VBUS pin has two comparators that monitor the voltage level on the pin. These comparators can be disabled for power savings when not needed. 0 USB VBUS detect comparator is disabled. 1 USB VBUS detect comparator is enabled. USBPLLEN 11-7 Reserved 6 USB PLL enable. This is normally only used for test purposes.
Power Management www.ti.com 1.5.4 Static Power Management 1.5.4.1 RTC Power Management Register (RTCPMGT) [1930h] This register enables static power management with power down and wake up register bits as described in the device-specific data sheet and, more generally, below. The RTC power management register (RTCPMGT) is shown in Figure 1-18 and described in Table 1-28. Figure 1-18.
Power Management www.ti.com 1.5.4.2 RTC Interrupt Flag Register (RTCINTFL) [1920h] The RTC interrupt flag register (RTCINTFL) is shown in Figure 1-19 and described in Table 1-29. Figure 1-19. RTC Interrupt Flag Register (RTCINTFL) [1920h] 15 14 8 ALARMFL Reserved R-0 R-0 7 5 4 3 2 1 0 Reserved 6 EXTFL DAYFL HOURFL MINFL SECFL MSFL R-0 R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-29.
Power Management 1.5.4.3 www.ti.com Internal Memory Low Power Modes To save power, software can place on-chip memory (DARAM or SARAM) in one of two power modes: memory retention mode and active mode. These power modes are activated through the SLPZVDD and SLPZVSS bits of the RAM Sleep Mode Control Register 1-5 (RAMSLPMDCNTLR[1:5]). To activate memory retention mode, set SLPZVDD bit and clear SLPZVSS bit of each memory bank to be put in retention mode.
Power Management www.ti.com Figure 1-21.
Power Management www.ti.com 1.5.5 Power Configurations The power-saving features described in the previous sections, such as peripheral clock gating, and on-chip memory power down to name a few, can be combined to form a power configuration. Many different power configurations can be created by enabling and disabling different power domains and clock domains, however, this section defines some basic power configurations that may be useful. These are shown and described in Table 1-31.
Power Management www.ti.com 1.5.5.1 IDLE2 Procedure In this power configuration all the power domains are turned on, the RTC and clock generator domains are enabled, the CPU domain is disabled, and the DSP peripherals are disabled. When you enter this power configuration all CPU and peripheral activity in the DSP is stopped.
Power Management 1.5.5.2 www.ti.com IDLE3 Procedure In this power configuration all the power domains are turned on, the CPU and clock generator domains are disabled, and the RTC clock domain is enabled. The DSP peripherals and the USB are also disabled in this mode. When you enter this power configuration, all CPU and peripheral activity in the DSP is stopped. Since the clock generator domain is disabled, you must allow enough time for the PLL to re-lock before exiting this power configuration.
Interrupts www.ti.com When the core voltage is increased (1.05 V to 1.3 V) clock speed is not an issue since the device can operate faster at the higher voltage. However, when switching from 1.05 V to 1.3 V software must allow time for the voltage transition to reach the 1.3 V range. Additionally, external regulators might produce an overshoot that must not pass the maximum operational voltage of the core supply (see the Recommended Operating Conditions section in device-specific data manual).
Interrupts www.ti.com Table 1-32. Interrupt Table (continued) SOFTWARE (TRAP) EQUIVALENT NAME RELATIVE LOCATION (HEX BYTES) PRIORITY FUNCTION (1) - SINT28 0xE0 15 Software interrupt #28 - SINT29 0xE8 16 Software interrupt #29 - SINT30 0xF0 17 Software interrupt #30 - SINT31 0xF8 18 Software interrupt #31 1.6.1 IFR and IER Registers The interrupt flag register 0 (IFR0) and interrupt enable register 0 (IER0) bit layouts are shown in Figure 1-25 and described in Table 1-33.
Interrupts www.ti.com The interrupt flag register (IFR1) and interrupt enable register 1 (IER1) bit layouts are shown in Figure 1-26 and described in Table 1-34. Figure 1-26. IFR1 and IER1 Bit Locations 15 10 9 8 Reserved 11 RTOS DLOG BERR R-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 I2C EMIF GPIO USB SPI RTC RCV3 XMT3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-34.
Interrupts www.ti.com 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] The CPU has only one interrupt flag that is shared among the three timers. The CPU's interrupt flag is bit 4 (TINT) of the IFR0 & IER0 registers (see Figure 1-25). Since the interrupt flag is shared, software must have a means of determining which timer instance caused the interrupt. Therefore, the timer interrupt aggregation flag register (TIAFR) is a secondary flag register that serves this purpose.
System Configuration and Control www.ti.com 1.7 System Configuration and Control 1.7.1 Overview The DSP includes system-level registers for controlling, configuring, and reading status of the device.
System Configuration and Control 1.7.2.1 www.ti.com Die ID Register 0 (DIEIDR0) [1C40h] The die ID register 0 (DIEIDR0) is shown in Figure 1-27 and described in Table 1-36. Figure 1-27. Die ID Register 0 (DIEIDR0) [1C40h] 15 0 DIEID0 R LEGEND: R = Read only; -n = value after reset Table 1-36. Die ID Register 0 (DIEIDR0) Field Descriptions Bit Field 15-0 DIEID0 1.7.2.2 Value Description 0-FFFFh Die ID bits.
System Configuration and Control www.ti.com 1.7.2.4 Die ID Register 3 (DIEIDR3[15:0]) [1C43h] The die ID register 3 (DIEIDR3) is shown in Figure 1-30 and described in Table 1-39. Figure 1-30. Die ID Register 3 (DIEIDR3[15:0]) [1C43h] 15 12 11 0 DesignRev DIEID3 R R LEGEND: R = Read only; -n = value after reset Table 1-39. Die ID Register 3 (DIEIDR3[15:0]) Field Descriptions Bit Field 15-12 Value DesignRev 11-0 0-Fh DIEID3 1.7.2.5 Description Silicon Revision 0 Silicon 2.
System Configuration and Control 1.7.2.7 www.ti.com Die ID Register 6 (DIEIDR6) [1C46h] The die ID register 6 (DIEIDR6) is shown in Figure 1-33 and described in Table 1-42. Figure 1-33. Die ID Register 6 (DIEIDR6) [1C46h] 15 0 Reserved R LEGEND: R = Read only; -n = value after reset Table 1-42. Die ID Register 6 (DIEIDR6) Field Descriptions Bit Field 15-0 Value Reserved 1.7.2.8 Description 0 Reserved.
System Configuration and Control www.ti.com 1.7.3 Device Configuration The DSP includes registers for configuring pin multiplexing, the pin output slew rate, the internal pull-ups and pull-downs, DSP_LDO voltage selection and USB_LDO enable. 1.7.3.1 External Bus Selection Register (EBSR) The external bus selection register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3, UART, SPI, and GPIO signals to 21 signals of the external parallel port pins.
System Configuration and Control www.ti.com Table 1-44. EBSR Register Bit Descriptions Field Descriptions Bit Field 15 Reserved 14-12 PPMODE 11-10 9-8 7-6 5 4 3 62 Value 0 000 Mode 0 (16-bit LCD Controller). All 21 signals of the LCD Bridge module are routed to the 21 external signals of the parallel port. 001 Mode 1 (SPI, GPIO, UART, and I2S2).
System Configuration and Control www.ti.com Table 1-44. EBSR Register Bit Descriptions Field Descriptions (continued) Bit Field 2 Value A17_MODE 1 A17 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 17 (EM_A[17]) and general-purpose input/output pin 23 (GP[23]) pin functions. 0 Pin function is EMIF address pin 17 (EM_A[17]). 1 Pin function is general-purpose input/output pin 23 (GP[23]). A16_MODE 0 A16 Pin Mode Bit.
System Configuration and Control www.ti.com Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Bit 15-5 4 3 Field Reserved Value 0 WU_DOUT Description Reserved. Read-only, writes have no effect. Wakeup output, active low/open-drain. 0 WAKEUP pin driven low. 1 WAKEUP pin is in high-impedance (Hi-Z). WU_DIR Wakeup pin direction control. 0 WAKEUP pin configured as a input. 1 WAKEUP pin configured as a output. Note: When the WAKEUP pin is configured as an input, it is active high.
System Configuration and Control www.ti.com Figure 1-37. LDO Control Register (LDOCNTL) [7004h] 15 8 Reserved R-0 7 1 0 Reserved 2 DSP_LDO_V USB_LDO_EN R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions Bit 15-2 1 0 Field Value Reserved 0 DSP_LDO_V Description Reserved. Read-only, writes have no effect. DSP_LDO voltage select bit. 0 DSP_LDOO is regulated to 1.3 V.
System Configuration and Control 1.7.3.4 www.ti.com Output Slew Rate Control Register (OSRCR) [1C16h] To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate.
System Configuration and Control www.ti.com 1.7.3.5 Pull-Up/Pull-Down Inhibit Register (PDINHIBR1, PDINHIBR2, and PDINHIBR3 [1C17h, 1C18h, and 1C19h] The device allows you to individually enable or disable the internal pull-up and pull-down resistors. You can individually inhibit the pull-up and pull-down resistors of the I/O pins through the pull-down/up inhibit registers (PDINHIBRn). There is one pin, TRSTN, that has a pulldown that is permanently enabled and cannot be disabled.
System Configuration and Control www.ti.com Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Bit Field 2 Value S02PD 1 Serial port 0 pin 2 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled. 1 Pin pull-down is disabled. S01PD 0 Description Serial port 0 pin 1 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled.
System Configuration and Control www.ti.com Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Bit Field 5 Value A20PD 4 EMIF A[20] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled. 1 Pin pull-down is disabled. A19PD 3 EMIF A[19] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled. 1 Pin pull-down is disabled.
System Configuration and Control www.ti.com Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions (continued) Bit Field 10 PD10PD 9 8 7 6 5 4 3 2 1-0 Value Parallel port pin 10 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled. 1 Pin pull-down is disabled. PD9PD Parallel port pin 9 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down. 0 Pin pull-down is enabled.
System Configuration and Control www.ti.com 1.7.4.1 DMA Synchronization Events The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels.
System Configuration and Control www.ti.com 1.7.4.2.1 DMA Interrupt Flag Register (DMAIFR) [1C30h] and DMA Interrupt Enable Register (DMAIER) [1C31h] The DSP includes two registers for aggregating the four channel interrupts of the four DMA controllers. Use the DMA interrupt enable register (DMAIER) to enable channel interrupts.
System Configuration and Control www.ti.com 1.7.4.2.2 DMAn Channel Event Source Registers (DMAnCESR1 and DMAnCESR2) [1C1Ah, 1C1Bh, 1C1Ch, 1C1Dh, 1C36h, 1C37h, 1C38h, and 1C39h] When SYNCMODE = 1 in a channel's DMACHmTCR2 (see the TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (SPRUFT2)), activity in the DMA controller is synchronized to a DSP event. You can specify the synchronization event used by the DMA channels by programming the CHmEVT bits of the DMAnCESR registers.
System Configuration and Control To 1. 2. 3. www.ti.com reset a peripheral or group of peripherals, follow these steps: Set COUNT = 08h in PSRCR. Initiate the desired peripheral reset by setting to 1 the bits of PRCR. Do not attempt to access the peripheral for at least the number of clock cycles set in the PSRCR register. A repeated NOP may be necessary. In some cases, a single reset is used for multiple peripherals.
System Configuration and Control www.ti.com Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) Bit 5 Field Value PG3_RST Description Peripheral group 3 software reset bit. Drives the MMC/SD0, MMC/SD1, I2S0, and I2S1 reset signal.
System Configuration and Control www.ti.com Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses BYTEMODE Setting CPU Access to EMIF Register CPU Access To External Memory BYTEMODE = 00b (16-bit word access) Entire register contents are accessed ASIZE = 01b (16-bit data bus): EMIF generates a single 16-bit access to external memory for every CPU word access. ASIZE = 00b (8-bit data bus): EMIF generates two 8-bit accesses to external memory for every CPU word access.
System Configuration and Control www.ti.com 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] The EMIF clock divider register (ECDR) controls the input clock frequency to the EMIF module. When EDIV = 1 (default), the EMIF operates at the same clock rate as the system clock (SYSCLK). When EDIV = 0, the EMIF operates at half the clock rate of the system clock. This register affects both asynchronous memory mode timing as well as synchronous (mobile SDRAM, SDRAM) mode.
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