查询TMS320VC5402供应商 / SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 TABLE OF CONTENTS Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 On-Chip Peripherals . . . . . .
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description (continued) 109 111 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 75 35 74 36 73 A18 A17 VSS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD NC TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT0 HD2 NC CLKMD3 CLKMD2 CLKMD1 VSS DVDD NC NC NC NC HCNTL0 VSS BCLKR0 BCLKR1 BFSR0 BFSR1
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 description (continued) TMS320VC5402 GGU PACKAGE (BOTTOM VIEW) 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549 devices.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package† SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # NC A1 NC B1 NC N13 NC N1 A19 A13 NC M13 NC N2 NC VSS DVDD C2 A12 L12 HCNTL0 M3 L13 N3 D4 CLKMD1 K10 VSS BCLKR0 VSS DVDD B11 C1 DVDD VSS A10 K4 D6 D10 HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10 A11 D2 CLKMD3 K12 BFSR0 M
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 terminal functions The following table lists each signal, function, and operating mode(s) grouped by function. Terminal Functions TERMINAL NAME TYPE† DESCRIPTION DATA SIGNALS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)].
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION I Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. I Microprocessor/microcomputer mode select.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low. I Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION HBIL I Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor that is only enabled when HPIENA = 0. HCS I Chip select. HCS is the select input for the HPI and must be driven low during accesses.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME TYPE† DESCRIPTION I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. I/O/Z Emulator 1 pin/disable all outputs.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’5402 programmed with contents unique to any particular application. A security option is available to protect a custom ROM.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory map Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F 0080 007F 0080 On-Chip DARAM (OVLY = 1) External (OVLY = 0) Hex 0000 005F 0060 3FFF 4000 3FFF 4000 EFFF F000 External EFFF F000 ROM (DROM=1) or External (DROM=0) On-Chip ROM (4K x 16-bit) FEFF FF00 FF7F FF80 Reserved FEFF FF00 Reserved (DROM=1) or External (DROM=0
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 relocatable interrupt vector table (continued) 15 7 6 5 4 3 2 1 0 IPTR MP/MC OVLY AVIS DROM CLK OFF SMUL SST R/W R/W R/W R R R R/W R/W LEGEND: R = Read, W = Write Figure 2. Processor Mode Status (PMST) Registers extended program memory The ’5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 0 0000 1 0000 1 3FFF Page 1 Lower 16K External 2 0000 2 3FFF Page 2 Lower 16K External ... ... 2 4000 1 4000 ... F 0000 F 3FFF Page 15 Lower 16K External F 4000 Page 0 Page 1 Upper 48K External 64K Words 0 FFFF Page 2 Upper 48K External 2 FFFF 1 FFFF Page 15 Upper 48K External ...
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 on-chip peripherals The ’5402 device has the following peripherals: Software-programmable wait-state generator with programmable bank-switching wait states An enhanced 8-bit host-port interface (HPI8) Two multichannel buffered serial ports (McBSPs) Two hardware timers A clock generator with a phase-locked loop (PLL) A direct memory access (DMA) controller software-programmable wait-state generator The s
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 software-programmable wait-state generator (continued) Table 2. Software Wait-State Register (SWWSR) Bit Fields BIT NO. NAME RESET VALUE 15 XPA 0 Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. 14–12 I/O 1 I/O space.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 programmable bank-switching wait states The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 parallel I/O ports The ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’5402 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial ports The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial ports (continued) On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 clock generator (continued) The reference clock input is then divided by two (DIV mode) to generate clocks for the ’5402 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA controller The ’5402 direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA controller allows movements of data to and from internal program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA has six independent programmable channels allowing six different contexts for DMA operation.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA priority level Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner. DMA source/destination address modification The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA channel index registers (continued) The element index and the frame index affect address adjustment as follows: Element index: For all except the last transfer in the frame, the element index determines the amount to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an interrupt line with timer 1 (IMR/IFR bit 7).
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory-mapped registers The ’5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to 1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on ’5402. The device also has a set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show additional peripheral MMRs associated with the ’5402. Table 9.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory-mapped registers (continued) Table 10.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 McBSP control registers and subaddresses The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the subbank.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 DMA subbank addressed registers (continued) Table 12.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13. Table 13.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 interrupts (continued) The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8. 15–14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES DMAC5 DMAC4 BXINT1 or DMAC3 BRINT1 or DMAC2 HPINT INT3 TINT1 or DMAC1 RES or DMAC0 BXINT0 BRINT0 TINT0 INT2 INT1 INT0 Figure 8. IFR and IMR Registers Table 14.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 documentation support Extensive documentation supports all TMS320 DSP family of devices from product announcement through applications development.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.4 V Input voltage range, VI . . . . . .
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH High-level output voltage IOH = MAX VOL Low-level output voltage IIZ Input current for D[15:0], HD[7:0] out uts in high outputs impedance All other inputs IOL = MAX Bus holders enabled, DVDD = MAX, VI = VSS to DVDD II DVDD = MAX, VO = VSS to DVDD TRST With internal pull
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 internal oscillator with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of 30 Ω and power dissipation of 1 mW.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 divide-by-two clock option (PLL disabled) The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate the internal machine cycle. The selection of the clock mode is described in the clock generator section. When an external clock source is used, the frequency injected must conform to specifications listed in the timing requirements table.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multiply-by-N clock option The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator section. When an external clock source is used, the external frequency injected must conform to specifications listed in the timing requirements table.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing timing requirements for a memory read (MSTRB = 0) [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) CLKOUT td(CLKL-A) th(CLKL-A)R A[19:0] th(A-D)R tsu(D)R ta(A)M th(D)R D[15:0] th(D)MSTRBH td(CLKL-MSL) td(CLKL-MSH) ta(MSTRBL) MSTRB R/W PS, DS NOTE A: A[19:16] are always driven low during accesses to external data space. Figure 13.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a memory write (MSTRB = 0) [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) CLKOUT td(CLKH-A) td(CLKL-A) th(A)W A[19:0] td(CLKL-D)W th(D)MSH tsu(D)MSH D[15:0] td(CLKL-MSL) tsu(A)W tdis(RWH-D) td(CLKL-MSH) MSTRB td(CLKH-RWL) ten(D-RWL) td(CLKH-RWH) tw(SL)MS td(RWL-MSTRBL) R/W PS, DS NOTE A: A[19:16] are always driven low during accesses to external data space. Figure 14.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port write (IOSTRB = 0) [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states timing requirements for externally generated wait states [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] th(RDY) tsu(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Wait State Generated by READY NOTE A: A[19:16] are always driven low during accesses to external data space. Figure 18.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] th(RDY) tsu(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Wait State Generated by READY NOTE A: A[19:16] are always driven low during accesses to I/O space. Figure 19.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] th(RDY) tsu(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally NOTE A: A[19:16] are always driven low during accesses to I/O space. Figure 20.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HOLD and HOLDA timings timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 21) MIN tw(HOLD) tsu(HOLD) Pulse duration, HOLD low Setup time, HOLD low/high before CLKOUT low MAX UNIT 4H+7 ns 7 ns switching characteristics over recommended operating conditions for memory control signals and HOLDA, [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 reset, BIO, interrupt, and MP/MC timings timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 reset, BIO, interrupt, and MP/MC timings (continued) X2/CLKIN tsu(RS) tw(RSL) RS, INTn, NMI tsu(INT) th(RS) CLKOUT tsu(BIO) th(BIO) BIO tw(BIO)S Figure 22. Reset and BIO Timings CLKOUT tsu(INT) tsu(INT) th(INT) INTn, NMI tw(INTH)A tw(INTL)A Figure 23. Interrupt Timing CLKOUT RS th(MPMC) tsu(MPMC) MP/MC Figure 24.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings (continued) switching characteristics over recommended operating conditions for XF and TOUT [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing timing requirements for McBSP [H=0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) tc(BCKRX) tw(BCKRXH) tr(BCKRX) tw(BCKRXL) BCLKR td(BCKRH–BFRV) td(BCKRH–BFRV) tr(BCKRX) BFSR (int) tsu(BFRH–BCKRL) th(BCKRL–BFRH) BFSR (ext) th(BCKRL–BDRV) tsu(BDRV–BCKRL) BDR (RDATDLY=00b) Bit (n–1) (n–2) tsu(BDRV–BCKRL) (n–3) (n–4) th(BCKRL–BDRV) BDR (RDATDLY=01b) Bit (n–1) (n–2) tsu(BDRV–BCKRL) BDR (RDATDLY=10b) (n–3) th(BCKRL–BDRV) Bit (n–1)
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP general-purpose I/O (see Figure 30) MIN tsu(BGPIO-COH) th(COH-BGPIO) Setup time, BGPIOx input mode before CLKOUT high† Hold time, BGPIOx input mode after CLKOUT high† MAX UNIT 9 ns 0 ns † BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing switching characteristics over recommended operating conditions†‡§¶ [H = 0.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing (continued) timing requirements†‡§ (see Figure 35, Figure 36, Figure 37, and Figure 38) MIN MAX UNIT tsu(HBV-DSL) th(DSL-HBV) Setup time, HBIL and HAD valid before DS low or before HAS low¶# Hold time, HBIL and HAD valid after DS low or after HAS low¶# 5 ns 5 ns tsu(HSL-DSL) tw(DSL) Setup time, HAS low before DS low 10 ns Pulse duration, DS low 20 ns tw(DSH) tsu(HDV-DSH) Pulse duration, DS
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing (continued) Second Byte First Byte Second Byte HAS tsu(HBV-DSL) tsu(HSL-DSL) th(DSL-HBV) HAD† Valid Valid tsu(HBV-DSL)‡ th(DSL-HBV)‡ HBIL HCS tw(DSH) tw(DSL) HDS td(DSH-HYH) td(DSH-HYL) HRDY ten(DSL-HD) td(DSL-HDV2) td(DSL-HDV1) th(DSH-HDV)R HD READ Valid Valid tsu(HDV-DSH) Valid tv(HYH-HDV) th(DSH-HDV)W HD WRITE Valid Valid Valid td(COH-HYH) CLKOUT † HAD refers to HCNTL0, HCNTL1, and
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 HPI8 timing (continued) First Byte Second Byte Second Byte HCS HDS td(HCS-HRDY) HRDY Figure 36. Using HCS to Control Accesses CLKOUT td(COH-HTX) HINT Figure 37. HINT Timing CLKOUT tsu(GPIO-COH) th(GPIO-COH) GPIOx Input Mode† td(COH-GPIO) GPIOx Output Mode† † GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O). Figure 38.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 MECHANICAL DATA PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147/C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 MECHANICAL DATA GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY PACKAGE 12,10 SQ 11,90 9,60 TYP 0,80 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4073221-2/B 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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