Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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TMS320DM647/DM648

Video Port/VCXO Interpolated Control (VIC)

Port

User's Guide

Literature Number: SPRUEM1

May 2007

Summary of content (174 pages)

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TMS320DM647/DM648 Video Port/VCXO Interpolated Control (VIC) Port User's Guide Literature Number: SPRUEM1 May 2007
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SPRUEM1 – May 2007 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 13 1 1.1 1.2 Overview ................................................................................................................. 16 Video Port ................................................................................................................ 17 Video Port FIFO ......................................................................................
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3.4 3.3.3 Y/C Image Window and Capture ............................................................................. 50 3.3.4 Y/C FIFO Packing .............................................................................................. 51 BT.656 and Y/C Mode Field and Frame Operation .......................................................... 51 ..................................................................... 3.4.2 Vertical Synchronization ........................................................
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3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) ................................................... 86 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM).................................................. 87 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) ...................................... 88 3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM) ..................................... 88 3.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) ..............
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........................................................................................... 122 4.12.1 Video Display Status Register (VDSTAT) ................................................................ 122 4.12.2 Video Display Control Register (VDCTL) ................................................................. 123 4.12.3 Video Display Frame Size Register (VDFRMSZ) ........................................................ 127 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) .............
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6.3 6.4 6.5 Operational Details .................................................................................................. 169 Enabling VIC Port .................................................................................................... 170 VIC Port Registers ................................................................................................... 170 6.5.1 VIC Control Register (VICCTL).............................................................................. 171 6.5.
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List of Figures 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 8 Video Port Block Diagram ................................................................................................. BT.656 Video Capture FIFO Configuration .............................................................................
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3-39 3-40 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) ............................................ 90 TCI System Time Clock Ticks Interrupt Register (TCITICKS)........................................................
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4-52 4-53 4-54 4-55 4-56 4-57 4-58 4-59 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 6-3 6-4 6-5 10 Video Display Event Register (VDDISPEVT) ......................................................................... Video Display Clipping Register (VDCLIP) ............................................................................ Video Display Default Display Value Register (VDDEFVAL) .......................................................
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List of Tables 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 4-1 4-2 4-3 4-4 Video Capture Signal Mapping ........................................................................................... 26 Video Display Signal Mapping ............................................................................................
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4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 6-4 6-5 6-6 12 Video Display Control Registers ....................................................................................... Video Display Status Register (VDSTAT) Field Descriptions .......................................................
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Preface SPRUEM1 – May 2007 Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
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www.ti.com Related Documentation From Texas Instruments SPRUEK8 — TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus.
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www.ti.com Related Documentation From Texas Instruments SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs.
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SPRUEM1 – May 2007 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs). An overview of the video port functions, FIFO configurations, and signal mapping are included. Topic 1.1 1.2 1.3 1.4 1.5 1.6 16 Overview .................................................................................................. Video Port ................................................................................ Video Port FIFO ..............................
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www.ti.com Video Port 1.1 Video Port The video port peripheral can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. It provides the following functions: • Video capture mode: – Capture rate of up to 80 MHZ. – Two channels of 8-bit digital video input from a digital camera or an analog camera (using a video decoder). Digital video input is in YCbCr 4:2:2 format with 8-bit resolution multiplexed in ITU-R BT.656 format.
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www.ti.com Video Port This document describes the full feature set offered by the video port. See the device-specific datasheet for details about I/O timing information. Figure 1-1. Video Port Block Diagram Internal peripheral bus 32 VCLK1 VCLK2 VCTL1 VCTL2 VCTL3 Timing and control logic Memory mapped registers DMA interface 64 VDIN[19−2] 16 BT.656 capture pipeline 8 Y/C video capture pipeline 16 Raw video capture pipeline 16 TSI capture pipeline 8 8 Capture/display buffer (2560 bytes) BT.
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www.ti.com Video Port FIFO 1.2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with EDMA transfers to move data between the video port FIFO and external or on-chip memory. You can program threshold settings so that EDMA events generate when the video port FIFO reaches a certain fullness (for capture) or goes below a certain fullness (for display).
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www.ti.com Video Port FIFO 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configurations depending on the capture mode. For BT.656 operation, the FIFO is split into channel A and B, as shown in Figure 1-2. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus.
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www.ti.com Video Port FIFO For 8-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1-3. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus. Each channel's FIFO has a separate write pointer and read register (YSRCx). The FIFO configuration is identical for TCI capture, but channel B is disabled. Figure 1-3.
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www.ti.com Video Port FIFO For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Figure 1-4 shows how Y data is received on the VDIN[9-2] half of the bus and Cb/Cr data is received on the VDIN[19-12] half of the bus and de-multiplexed into the Cb and Cr buffers. Figure 1-4.
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www.ti.com Video Port FIFO For 16-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1-5. The FIFO receives 16-bit data from the VDIN[19-2] bus. The FIFO has a single write pointer and read register (YSRCA). Figure 1-5. 16-Bit Raw Video Capture FIFO Configuration Capture FIFO VDIN[19−2] YSRCA 64 16 Data Buffer (5120 bytes) 1.2.3 Video Display FIFO Configurations During video display operation, the video port FIFO has one of five configurations depending on the display mode.
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www.ti.com Video Port FIFO For locked raw video, the FIFO is split into channel A and B. The channels are locked together and use the same clock and control signals. Each channel uses a single buffer and write register (YDSTx) as shown in Figure 1-8. For 16-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1-9. The FIFO outputs data on VDOUT[19-2]. The FIFO has a single read pointer and write register (YDSTA). Figure 1-8.
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www.ti.com Video Port Registers For Y/C video display, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate read pointers and write registers (YDSTA, CBDST, and CRDST). Figure 1-10 shows how Y data is output on the VDOUT[9-2] half of the bus and Cb/Cr data is multiplexed and output on the VDOUT[19-12] half of the bus. Figure 1-10. Y/C Video Display FIFO Configuration Display FIFO VDOUT[9−2] YDSTA 64 8 Y Buffer (2560 bytes) CBDST CRDST 1.
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www.ti.com Video Port Pin Mapping 1.4 Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1-1. Pin functionality detail for video display mode is listed in Table 1-2. All unused port signals (except VCLK1 and VCLK1) can be configured as general-purpose I/O (GPIO) pins. Table 1-1. Video Capture Signal Mapping (1) Usage BT.
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www.ti.com Video Port Pin Mapping 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1-3. Table 1-3. VDIN Data Bus Usage for Capture Modes (1) Capture Mode BT.
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www.ti.com Video Port Pin Multiplexing 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1-4. Table 1-4. VDOUT Data Bus Usage for Display Modes (1) Display Mode BT.
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SPRUEM1 – May 2007 Video Port This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, EDMA operation, external clock inputs, video port throughput and latency, and the video port control registers. Topic 2.1 2.2 2.3 2.4 .................................................................................................. Reset Operation ........................................................................
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www.ti.com Reset Operation 2.1 Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation. The reset is initiated by a power-on reset input to the video port.
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www.ti.com Interrupt Operation Note: The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should be polled to make sure the bit is cleared prior to writing to the video port registers. Once the port is configured and the VPHLT bit is cleared, the setting of other VPCTL bits (except VPRST) is disabled. The VCLK2 output may also be driven at this time, if display mode is selected.
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www.ti.com EDMA Operation • • Display complete not acknowledged (DCNA) bit is set. GPIO interrupt (GPIO) bit is set. The interrupt signal is a pulse only and does not hold state. The interrupt pulse is generated only when the number of set flags in VPIS transitions from none to one or more. Another interrupt pulse is not generated by setting additional flag bits. Interrupts can be masked via the video port interrupt enable register (VPIE) using individual interrupt enables and the VIE global enable bit.
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www.ti.com EDMA Operation 2.3.2 Display EDMA Event Generation Display EDMA events are generated based on the amount of room available in the FIFO. The VDTHRLDn value indicates the level at which the FIFO has room to receive another EDMA. If the FIFO has at least VDTHRLDn locations available, a EDMA event is generated.
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www.ti.com Video Port Control Registers 2.3.4 EDMA Interface Operation When the video port is configured for capture (or TCI) mode, it only accepts read requests from the EDMA interface. Write requests are false acknowledged (so the bus does not stall) and the data is discarded. When the video port is configured for display mode, it only accepts write requests. Read requests are false acknowledged (so the bus does not stall) and an arbitrary data value is returned.
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www.ti.com Video Port Control Registers 2.4.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of the video port. Not all combinations of the port control bits are unique. The control bit encoding is shown in Table 2-3. Additional mode options are selected using the video capture channel A control register (VCACTL) and video display control register (VDCTL). The video port control register (VPCTL) is shown in Figure 2-1 and described in Table 2-2.
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www.ti.com Video Port Control Registers Table 2-2. Video Port Control Register (VPCTL) Field Descriptions (continued) Bit 5 field (1) VCT2P symval (1) Value Description OF(value) VCTL2 pin polarity bit. Does not affect GPIO operation. DEFAULT 0 Indicates the VCTL2 control signal (input or output) is active high. 1 Indicates the VCTL2 control signal (input or output) is active low. NONE ACTIVELOW 4 VCT1P OF(value) VCTL1 pin polarity bit. Does not affect GPIO operation.
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www.ti.com Video Port Control Registers 2.4.2 Video Port Status Register (VPSTAT) The video port status register (VPSTAT) indicates the current condition of the video port. The video port status register (VPSTAT) is shown in Figure 2-2 and described in Table 2-4. Figure 2-2. Video Port Status Register (VPSTAT) 31 16 Reserved R-0 15 3 2 Reserved 4 DCDIS HIDATA 1 Reserved 0 R-0 R-x R-x R-0 LEGEND: R = Read only; -n = value after reset Table 2-4.
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www.ti.com Video Port Control Registers 2.4.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The video port interrupt enable register (VPIE) is shown in Figure 2-3 and described in Table 2-5. Figure 2-3.
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www.ti.com Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) (1) Bit field 17 COVRB symval (1) Value Description OF(value) DEFAULT Capture overrun on channel B interrupt enable bit. 0 Interrupt is disabled. 1 Interrupt is enabled. DISABLE ENABLE 16 GPIO OF(value) DEFAULT Video port general purpose I/O interrupt enable bit. 0 Interrupt is disabled. DISABLE ENABLE 1 Interrupt is enabled. 15 Reserved - 0 Reserved.
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www.ti.com Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) Bit 3 field (1) symval SERRA (1) Value Description OF(value) Channel A synchronization error interrupt enable bit. DEFAULT 0 Interrupt is disabled. 1 Interrupt is enabled. DISABLE ENABLE 2 CCMPA OF(value) Capture complete on channel A interrupt enable bit. DEFAULT 0 Interrupt is disabled. 1 Interrupt is enabled.
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www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) (1) Bit field 23 LFDB symval (1) Value Description OF(value) Long field detected on channel B interrupt detected bit. (A long field is only detected when the VRST bit in VCBCTL is cleared to 0; when VRST = 1, a long field is always detected.) BT.656 or Y/C capture mode - LFDB is set when long field detection is enabled and VCOUNT is not reset before VCOUNT = YSTOP + 1.
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www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) (1) Bit field 17 COVRB symval (1) Value Description OF(value) DEFAULT Capture overrun on channel B interrupt detected bit. COVRB is set when data in the FIFO was overwritten before being read out (by the EDMA). 0 No interrupt is detected. 1 Interrupt is detected. Bit is cleared.
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www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) (1) Bit field 7 LFDA symval (1) Value Description OF(value) Long field detected on channel A interrupt detected bit. (A long field is only detected when the VRST bit in VCACTL is cleared to 0; when VRST = 1, a long field is always detected.) BT.656 or Y/C capture mode - LFDA is set when long field detection is enabled and VCOUNT is not reset before VCOUNT = YSTOP + 1.
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www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) Bit 1 field (1) COVRA symval (1) Value Description OF(value) DEFAULT Capture overrun on channel A interrupt detected bit. COVRA is set when data in the FIFO was overwritten before being read out (by the EDMA). 0 No interrupt is detected. CLEAR 1 Interrupt is detected. Bit is cleared. - 0 Reserved. The reserved bit location is always read as 0.
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SPRUEM1 – May 2007 Video Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, an EDMA is performed to move data from the FIFO into DSP memory. In some cases, color separation is performed on the incoming video data requiring multiple FIFOs and EDMAs to be used. The video port enables capture of both interlaced and progressive scan data.
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www.ti.com Video Capture Mode Selection 3.1 Video Capture Mode Selection The video capture module operates in one of five modes as listed in Table 3-1. The transport channel interface (TCI) selection is made using the TCI bit in the video port control register (VPCTL). The CMODE bits are in the video capture channel x control register (VCxCTL). The Y/C and 16-bit raw capture modes may only be selected for channel A and only if the DCDIS bit in VPCTL is cleared to 0.
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www.ti.com BT.656 Video Capture Mode Table 3-2. BT.
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www.ti.com BT.656 Video Capture Mode Table 3-4. Error Correction by Protection Bits (continued) Received F, V, and H Bits Received P3-P0 Bits 000 001 010 011 1011 1100 100 101 110 010 - 010 - 001 110 1101 001 001 1110 - 1111 - 111 010 - 101 010 - - 110 - 110 110 - 001 - 001 110 - - - 011 - 101 110 - 001 010 - 100 - - - 3.2.3 BT.656 Image Window and Capture The BT.656 format is an interlaced format consisting of two fields.
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www.ti.com BT.656 Video Capture Mode Table 3-5. Common Video Source Parameters Number of Active Lines (Field 1/Field 2) Number of Active Pixels Field Rate (Hz) square pixel 60 Hz/525 lines 240/240 640 60 BT.601 60 Hz/525 lines 244/243 720 60 square pixel 50Hz/625 lines 288/288 768 50 BT.601 50 Hz/625 lines 288/288 720 50 Video Source For the BT.656 video capture mode, the FIFO buffer is divided into three sections (three buffers).
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www.ti.com Y/C Video Capture Mode Figure 3-2. 8-Bit BT.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation For the Y/C video capture mode, the FIFO buffer is divided into three sections (three buffers). One section is 2560 bytes deep and is dedicated for storage of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively. The buffers for Cb and Cr samples are each 1280 bytes deep.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation to which a continuous stream of fields are stored without DSP intervention. In other cases, the DSP may need to modify EDMA pointer addresses after each field or frame is captured. In some applications, only one field may be captured and the other ignored completely, or a frame may need to be ignored in order to have time to process a previous frame.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation Table 3-6. BT.656 and Y/C Mode Capture Operation (continued) VCxCTL Bit CON FRAME CF2 CF1 Operation 1 0 0 1 Continuous field 1 capture. Capture only field 1. F1C is set after field 1 capture and causes CCMPx to be set (CCMPx interrupt can be disabled). The video port continues capturing field 1 fields, regardless of the state of F1C. 1 0 1 0 Continuous field 2 capture. Capture only field 2.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation VMode 2 and VMode 3 are used for BT.656 or Y/C capture without embedded EAV/SAV codes and allow alignment with either the active or inactive edge of the vertical control signal on VCTL2. This can be a VBLNK or VSYNC signal from the video decoder. Figure 3-4.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line. The encoding of these bits is shown in Table 3-8. Table 3-8. Horizontal Synchronization Programming VCxCTL Bit HMode EXC HRST Horizontal Counter Reset Point 0 0 0 EAV code (H=1) - beginning of horizontal blanking.
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www.ti.com BT.656 and Y/C Mode Field and Frame Operation Figure 3-6. HCOUNT Operation Example (EXC = 1) Active Video Cb 0 Y 718 Cr 359 Y 719 80.0 10.0 80.0 10.0 80.0 10.0 Blanking 80.0 10.0 80.0 10.0 80.0 10.0 Cb 0 Y0 Cr 0 Y1 Cb 1 Y2 1440 10.0 80.0 276 10.0 80.0 VDIN[9−2] 80.0 10.0 80.0 10.0 80.0 10.0 80.0 10.
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www.ti.com Video Input Filtering The field indicator method uses the FID input directly to determine the current field. This is useful for Y/C data streams that do not have embedded EAV and SAV codes. The FID input is sampled at the start of each field. If FID = 0, then field 1 is starting; if FID = 1, then field 2 is starting. The start of each field is defined by the VRST bit in VCxCTL and is either the start or end of vertical blanking as determined by the VBLNK input.
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www.ti.com Video Input Filtering 3.5.1 Input Filter Modes The input filter has four modes of operation: no-filtering, ½ scaling, chrominance re-sampling, and ½ scaling with chrominance re-sampling. Filter operation is determined by the CMODE, SCALE, and RESMPL bits of VCxCTL. Table 3-10 shows the input filter mode selection. When 8-bit BT.656 or Y/C capture operation is selected (CMODE = x00), scaling is selected by setting the SCALE bit and chrominance re-sampling is selected by setting the RESMPL bit.
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www.ti.com Video Input Filtering The filtering for the luminance portion of the scaling filter changes depending on if chrominance re-sampling is also enabled. (By changing the luminance filter, the chrominance filters can remain the same.) The resulting values are clamped to between 01h and FEh and sent to the Y, Cb, and Cr capture buffers. Scaling for co-sited capture is shown in Figure 3-9 and scaling for chrominance re-sampling is shown in Figure 3-10. Figure 3-9.
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www.ti.com Ancillary Data Capture Note that edge pixel replication only comes into effect when the full BT.656 stream is being captured. If VCXSTART is greater than 0, then only some of the leading edge replicated pixels are used by the filter. If VCXSTART is greater than m, then none of the leading edge replicated pixels are used. Similarly, if VCXSTOP is less than the number of samples before EAV, then none or only some of the trailing edge replicated pixels are used by the filters. Figure 3-11.
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www.ti.com Raw Data Capture Mode 3.6.1 Horizontal Ancillary (HANC) Data Capture No special provisions are made for the capture of HANC data. HANC data may be captured using the normal video capture mechanism by programming VCXSTRT to occur before the SAV (when HCOUNT is reset by the EAV code) or by programming VCXSTOP to occur past the EAV code (when HCOUNT is reset by the SAV code). Note that the EAV code and any subsequent HANC data will still be YCbCr separated.
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www.ti.com Raw Data Capture Mode For channel B operation or when the RDFE bit in VCACTL is not set, no field information is available. Some flexibility in capture and DSP notification is still provided in order to accommodate various EDMA structures and processing flows. Each raw data packet is treated similar to a progressive scan video frame. The raw data mode uses the CON and FRAME bits of VCxCTL in a slightly different manner, as listed in Table 3-11. Table 3-11.
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www.ti.com TCI Capture Mode Figure 3-14. 16-Bit Raw Data FIFO Packing VCLKINA VDIN[19−12] / VDIN[9−2] 63 Raw FIFO 4847 Raw 11 Raw 7 Raw 3 3231 Raw 10 Raw 6 Raw 2 1615 0 Raw 9 Raw 5 Raw 1 Raw 8 Raw 4 Raw 0 Little-Endian Packing 3.8 TCI Capture Mode The transport channel interface (TCI) capture mode captures MPEG-2 transport data. 3.8.
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www.ti.com TCI Capture Mode Figure 3-15. Parallel TCI Capture VCLKIN CAPEN PACSTRT VDIN[9:2] ÉÉÉ ÉÉÉ ÉÉÉ Sync Byte Byte 1 Byte 2 Byte 3 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Byte 4 Start Capture 3.8.3 TCI Capture Error Detection The video port checks for two types of errors during TCI capture. The first is a packet error on the incoming packet as indicated by an active PACERR signal.
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www.ti.com TCI Capture Mode counter counts from 0 to 299 at 27 MHz. Each time the 9-bit counter rolls over to 0, the 33-bit counter is incremented by 1. This is equivalent to the PCR timestamp transmitted in the bit-stream. The 33-bit field can also be programmed to count at 27 MHz for compatibility with the MPEG-1 32-bit PCR, by setting the CTMODE bit in VCCTL to 1; in which case, the PCR extension portion of the counter is not used. Figure 3-17 shows the system time clock counter operation. Figure 3-17.
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www.ti.com TCI Capture Mode Table 3-12. TCI Capture Mode Operation (continued) VCACTL Bit CON FRAME CF2 CF1 Operation 0 1 x x Single packet capture. FRMC is set after packet capture and causes CCMPA to be set. Capture is halted until the FRMC bit is cleared. 1 0 x x Continuous packet capture. FRMC is set after packet capture and causes CCMPA to be set (CCMPx interrupt can be disabled). The port will continue capturing packets regardless of the state of FRMC. 1 1 x x Reserved 3.8.
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www.ti.com Capture Line Boundary Conditions The video port generates a YEVT after the specified number of new samples has been captured in the buffer. The number of samples required to generate YEVT is programmable and is set in the VCTHRLD1 bits of VCATHRLD. VCTHRLD1 should be set to the packet size plus 8 bytes of timestamp. On every YEVT, the EDMA should move data from the buffer to the DSP memory.
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www.ti.com Capturing Video in Raw Data Mode number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx, CbEVTx, and CrEVTx are generated by the video capture module. 7. Configure an EDMA channel to move data from YSRCx to a destination in the DSP memory. The channel transfers should be triggered by the YEVTx. The size of the transfers should be set appropriately during the configuration of the EDMA channel parameters.
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www.ti.com Capturing Data in TCI Capture Mode 5. Write to VCxTHRLD to set the capture threshold. The threshold needs to be set in units of double word. One double word is equal to 8 bytes. Every time the number of received bytes reaches the number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx is generated by the video capture module. 6. Configure a EDMA channel to move data from YSRCx to a destination in the DSP memory.
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www.ti.com Video Capture Registers 5. Write to TCISTCMPL, TCISTCMPM, TCISTMSKL, and TCISTMSKM if needed to initiate an interrupt, based on STC absolute time. 6. Write to TCITICKS if an interrupt is desired every x cycles of STC. 7. Write to VPCTL to select TCI capture operation (TCI = 1). 8. Write to VPIE to enable overrun (COVRA) and capture complete (CCMPA) interrupts, if desired. 9. Write to VCACTL to set capture mode (CMODE = 010). 10. Set VCEN bit in VCACTL to enable capture. 11.
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www.ti.com Video Capture Registers Table 3-13. Video Capture Control Registers (continued) Offset Address (1) Acronym Register Name Section 154h VCBSTOP2 Video Capture Channel B Field 2 Stop Register Section 3.13.6 158h VCBVINT Video Capture Channel B Vertical Interrupt Register Section 3.13.7 15Ch VCBTHRLD Video Capture Channel B Threshold Register Section 3.13.8 160h VCBEVTCT Video Capture Channel B Event Count Register Section 3.13.
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www.ti.com Video Capture Registers Table 3-14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Description (1) Bit field 31 FSYNC symval (1) Value OF(value) DEFAULT 30 FRMC VCOUNT = VINT1 or Not used. VINT2, as selected by the FSCL2 bit in VCxVINT. Not used. 1 VCOUNT = 1 in field 1. Not used. 0 Complete frame has not been captured. Complete data block has not been captured. Entire data packet has not been captured. 1 Complete frame has been captured.
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www.ti.com Video Capture Registers Figure 3-22.
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www.ti.com Video Capture Registers Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) Description Bit field 19 EXC (1) symval (1) Value OF(value) DEFAULT BT.656 or Y/C Mode Raw Data Mode TCI Mode External control select bit. (Channel A only) 0 Use EAV/SAV codes. Not used. Not used. 1 Use external control signals. Not used. Not used. EAVSAV EXTERN 18 FLDD OF(value) DEFAULT Field detect method bit.
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www.ti.com Video Capture Registers Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) Description Bit 7 field (1) CON (2) symval (1) Value OF(value) DEFAULT BT.656 or Y/C Mode Raw Data Mode TCI Mode Continuous capture enable bit. 0 Continuous capture is disabled. 1 Continuous capture is enabled. DISABLE ENABLE 6 FRAME (2) OF(value) DEFAULT Capture frame (data) bit. 0 Do not capture frame. Do not capture single data block.
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www.ti.com Video Capture Registers Figure 3-23. Video Capture Channel x Field 1 Start Register (VCxSTRT1) 31 15 28 27 16 Reserved VCYSTART R-0 R/W-0 14 12 11 0 SSE Reserved VCXSTART/VCVBLNKP R/W-1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-16.
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www.ti.com Video Capture Registers Figure 3-24. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) 31 28 27 16 Reserved VCYSTOP R-0 R/W-0 15 12 11 0 Reserved VCXSTOP R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-17.
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www.ti.com Video Capture Registers Table 3-18. Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions Description Bit field (1) symval (1) Value 31-28 Reserved - 27-16 VCYSTART OF(value) 0-FFFh DEFAULT 0 15-12 Reserved - 0 11-0 OF(value) 0-FFFh DEFAULT 0 (1) VCXSTART 0 BT.656 or Y/C Mode Raw Data Mode TCI Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Starting line number. Not used. Not used.
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www.ti.com Video Capture Registers 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCxVINT) The video capture channel x vertical interrupt register (VCAVINT, VCBVINT) controls the generation of vertical interrupts in each field. In BT.656 or Y/C mode, an interrupt can be generated upon completion of the specified line in a field (end of line when VCOUNT = VINTn). This allows the software to synchronize to the frame or field.
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www.ti.com Video Capture Registers 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) The video capture channel x threshold register (VCATHRLD, VCBTHRLD) determines when EDMA requests are sent. The VCTHRLD1 bits determine when capture EDMA events are generated. Once the threshold is reached, generation of further EDMA events is disabled until service of the previous event(s) begins (the first FIFO read by the EDMA occurs). In BT.
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www.ti.com Video Capture Registers 3.13.9 Video Capture Channel x Event Count Register (VCxEVTCT) The video capture channel x event count register (VCxEVTCT) is programmed with the number of EDMA events to be generated for each capture field. An event counter tracks how many events have been generated and indicates which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter.
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www.ti.com Video Capture Registers Figure 3-30.
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www.ti.com Video Capture Registers Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) Description (1) Bit field 16 HRST symval (1) Value BT.656 or Y/C Mode OF(value) DEFAULT Raw Data Mode TCI Mode HCOUNT reset method bit. 0 EAV or VCTL1 active edge. Not used. Not used. 1 SAV or VCTL1 inactive edge. Not used. Not used. EAV SAV 15 VCEN OF(value) DEFAULT Video capture enable bit.
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www.ti.com Video Capture Registers Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) Description Bit field (1) CF1 (2) 4 symval (1) Value BT.656 or Y/C Mode OF(value) Raw Data Mode TCI Mode Capture field 1 bit. NONE 0 Do not capture field 1. Not used. Not used. DEFAULT 1 Capture field 1. Not used. Not used. 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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www.ti.com Video Capture Registers Table 3-24. TCI Capture Control Register (TCICTL) Field Descriptions (continued) Description Bit 3 field (1) STEN symval (1) Value BT.656, Y/C Mode, or Raw Data Mode OF(value) TCI Mode System time clock interrupt enable bit. DEFAULT 0 Not used. Setting of the STC bit is disabled. Not used. A valid STC compare sets the STC bit in VPIS. DISABLE SET 2 CTMODE OF(value) Counter mode select bit. DEFAULT 0 Not used.
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www.ti.com Video Capture Registers 3.13.13 TCI Clock Initialization MSB Register (TCICLKINITM) The transport stream interface clock initialization MSB register (TCICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock. . On receiving the first packet containing a program clock reference (PCR) header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit PCR extension into TCICLKINITM. This initializes the counter to the system time clock.
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www.ti.com Video Capture Registers Figure 3-34. TCI System Time Clock LSB Register (TCISTCLKL) 31 0 PCR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-27. TCI System Time Clock LSB Register (TCISTCLKL) Field Descriptions Description (1) Bit field symval 31-0 PCR OF(value) Value DEFAULT (1) BT.656, Y/C Mode, or Raw Data Mode 0-FFFF FFFFh Not used. TCI Mode Contains the 32 LSBs of the program clock reference.
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www.ti.com Video Capture Registers 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) The transport stream interface system time clock compare LSB register (TCISTCMPL) is used to generate an interrupt at some absolute time based on the STC. TCISTCMPL holds the 32 least-significant bits (LSBs) of the absolute time compare (ATC).
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www.ti.com Video Capture Registers Table 3-30. TCI System Time Clock Compare MSB Register (TCISTCMPM) Field Descriptions Description Bit 31-1 0 (1) (1) field symval Value BT.656, Y/C Mode, or Raw Data Mode Reserved - ATC OF(value) 0-1 DEFAULT 0 0 TCI Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Not used. Contains the MSB of the absolute time compare. For CSL implementation, use the notation VP_TCISTCMPM_ATC_symval 3.13.
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www.ti.com Video Capture Registers Figure 3-39. TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) 31 16 Reserved R-0 15 1 0 Reserved ATCM R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-32. TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) Field Descriptions Description Bit 31-1 0 (1) (1) field symval Value BT.656, Y/C Mode, or Raw Data Mode Reserved - ATCM OF(value) 0-1 DEFAULT 0 0 TCI M ode Reserved.
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www.ti.com Video Capture FIFO Registers 3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3-34. These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers. The function of the video capture FIFO mapping registers is listed in Table 3-35. Table 3-34.
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SPRUEM1 – May 2007 Video Display Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TCI) capture port. This chapter discusses the video display port. Topic .................................................................................................. 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 92 Video Display Port Page Video Display Mode Selection .................................................... 93 BT.
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www.ti.com Video Display Mode Selection 4.1 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4-1. The DMODE bits are in the video display control register (VDCTL). The Y/C and 16-bit raw display modes may only be selected if the DCDIS bit in the video port control register (VPCTL) is cleared to 0. Table 4-1. Video Display Mode Selection DMODE Bits Mode Description 000 8-Bit ITU-R BT.
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www.ti.com Video Display Mode Selection Figure 4-2.
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www.ti.com Video Display Mode Selection Figure 4-3. Interlaced Blanking Intervals and Video Areas Field 1 Vertical Blanking Field 1 Image Height Field 1 Field 1 Active Video Field 1 Image Horiz. Offset Frame Horizontal Blanking Field 1 Image Vertical Offset Field 1 Image Width Field 2 Vertical Blanking SPRUEM1 – May 2007 Submit Documentation Feedback Field 2 Field 2 Image Height Field 2 Active Video Field 2 Image Horiz.
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www.ti.com Video Display Mode Selection Figure 4-4. Progressive Blanking Intervals and Video Area Field 1 Vertical Blanking Field 1 Field 1 Image Height Field 1 Image Horizontal Offset Horizontal Blanking Frame Field 1 Image Vertical Offset Field 1 Active Video Field 1 Image Width 4.1.
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www.ti.com Video Display Mode Selection Figure 4-5 shows how the horizontal blanking and horizontal synchronization signals are triggered. (HBLNK and HSYNC are shown active high). Figure 4-5. Horizontal Blanking and Horizontal Sync Timing FPCOUNT 718 719 720 735 736 799 800 857 0 1 HBLNK HSYNC FPCOUNT = HBLNKSTOP FPCOUNT = HSYNCSTOP FPCOUNT = HSYNCSTART FPCOUNT = HBLNKSTART The 12-bit FLCOUNT counts which scan line is being generated.
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www.ti.com BT.656 Video Display Mode 4.1.3 Sync Signal Generation The video display module must generate a number of control signals for both internal and external use. As seen in Section 4.1.2, the HSYNC, HBLNK, VSYNC, VBLNK, and FLD signals are generated directly from the pixel and line counters and comparison registers. Several additional signals are also generated indirectly for use in external control. A composite blank (CBLNK) signal is generated as the logical-OR of the HBLNK and VBLNK signals.
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www.ti.com BT.656 Video Display Mode 4.2.1 Display Timing Reference Codes The end active video (EAV) code and start active video (SAV) code are issued at the start of each video line. EAV and SAV codes have a fixed format. The format is shown in Table 3-2 . The EAV and SAV codes define the end and start of the horizontal-blanking interval, respectively, and they also indicate the current field number and the vertical blanking interval.
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www.ti.com BT.656 Video Display Mode SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h. This combination must be avoided in the video data output by the video port to prevent accidental generation of an invalid sync code. The video display module provides programmable maximum and minimum value clipping on the video data to prevent this possibility. The typical values for H, V, and F on different lines are shown in Table 4-2 and Figure 4-11.
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www.ti.com BT.656 Video Display Mode 4.2.2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples. These values are also output during the active line period of vertical blanking (between SAV and EAV when V = 1).
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www.ti.com Y/C Video Display Mode 4.3 Y/C Video Display Mode The Y/C display mode is similar to the BT.656 display mode but outputs 8-bit data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other luminance sample. The Y samples are read from the Y FIFO and the Cb and Cr samples are read from the Cb and Cr FIFOs and combined on the chroma output.
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www.ti.com Video Output Filtering 4.3.4 Y/C FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the display data pipeline. By default, data is unpacked from right to left. The 8-bit Y/C mode uses three FIFOs for color separation. Samples are unpacked as shown in Figure 4-14. Figure 4-14.
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www.ti.com Video Output Filtering 4.4.2 Chrominance Re-sampling Operation Chrominance re-sampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples. This filter performs the conversion between interspersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must be performed in software.
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www.ti.com Video Output Filtering Figure 4-17.
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www.ti.com Ancillary Data Display Figure 4-20.
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www.ti.com Raw Data Display Mode 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out. This option allows proper tracking of the display pixels when sending out sequential RGB samples. (INCPIX would be set to three in this case, to indicate that a single pixel is represented by three output samples.
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www.ti.com Video Display Field and Frame Operation 4.7 Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals. Depending on the EDMA structure, however, the video port may need to interrupt the DSP on a field or frame basis to allow it to update video port registers or EDMA parameters. To achieve this, the video port provides programmable control over the display process. 4.7.
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www.ti.com Display Line Boundary Conditions Table 4-4. Display Operation (continued) VDCTL Bit CON FRAME DF2 DF1 Operation 0 1 1 1 Single frame display. Display both fields. FRMD is set after field 2 display and causes DCMPx to be set. A DCNA interrupt occurs unless the FRMD bit is cleared. (The DSP has the field 2 to field 1 vertical blanking time to clear FRMD.) 1 0 0 0 Reserved 1 0 0 1 Continuous field 1 display. Display only field 1.
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www.ti.com Display Timing Examples Figure 4-24.
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www.ti.com Display Timing Examples Figure 4-25. BT.
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www.ti.com Display Timing Examples The interlaced BT.656 vertical output timing is shown in Figure 4-26. The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFFn of 3 lines and also results in a non-data line at the end of field 1 due to its extra active line. The VBLNK and VSYNC signals are shown as they would be output for active-low operation.
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www.ti.com Display Timing Examples 525 V F AB VSYNC ILCOUNT FLD EAV FLCOUNT VBLNK AB Figure 4-26. BT.
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www.ti.com Display Timing Examples Figure 4-27.
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www.ti.com Display Timing Examples The vertical output timing for raw mode is shown in Figure 4-28. This example outputs the same 480-line window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case. The active field 1 is 242.5-lines high and active field 2 is 242.5-lines high. This example shows the 480-line image window centered in the screen.
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www.ti.com Display Timing Examples 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 x 720/60 system. The example is for a 1264 x 716 progressive output image. The horizontal output timing is shown in Figure 4-29. This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins.
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www.ti.com Display Timing Examples Figure 4-29.
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www.ti.com Display Timing Examples The vertical output timing is shown in Figure 4-30. SMPTE 296M has a single active field 1 that is 720-lines high. This example shows the 716-line image window with an IMGVOFFn of 3 lines and also results in a non-data line at the end of the field. The VBLNK and VSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally.
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www.ti.com Displaying Video in BT.656 or Y/C Mode 4.10 Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps are needed: 1. To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that the multiplexed pins work as Video Port Pins. Refer to the device-specific data manual for details about PINMUX register. 2. Program the VPx_CTL Register appropriately to use the desired Video Port as a Display Port. 3.
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www.ti.com Displaying Video in Raw Data Mode 22. Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized. 23. Write to VDCTL to clear the BLKDIS bit. 24. Display is enabled at the start of the first frame after BLKDIS = 0 and begins with the first selected field. EDMA events are generated as triggered by VDTHRLD and the DEVTCT counter.
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www.ti.com Displaying Video in Raw Data Mode by total double words per Y EDMA. 20. Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired. 21. Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and the FPCOUNT increment rate (INCPIX bit). 22. Write to VDCTL to: • Set display mode (DMODE =01x for 8-bit output, 11x for 16 bit output). • Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).
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www.ti.com Video Display Registers 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed in Table 4-5. See the device-specific datasheet for the memory address of these registers. Table 4-5. Video Display Control Registers (1) Offset Address (1) Acronym Register Name 200h VDSTAT Video Display Status Register Section 4.12.1 204h VDCTL Video Display Control Register Section 4.12.
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www.ti.com Video Display Registers Figure 4-31. Video Display Status Register (VDSTAT) 31 30 29 28 Reserved FRMD F2D F1D R-0 27 16 VDYPOS R/WC-0 R/WC-0 R/WC-0 15 14 R-0 13 12 Reserved VBLNK VDFLD 11 VDXPOS 0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-6. Video Display Status Register (VDSTAT) Field Descriptions (1) symval (1) Bit field 31 Reserved - 30 FRMD OF(value) DEFAULT Value 0 Description Reserved.
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www.ti.com Video Display Registers The video display is controlled by the video display control register (VDCTL). The video display control register (VDCTL) is shown in Figure 4-32 and described in Table 4-7. Figure 4-32.
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www.ti.com Video Display Registers Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) Description Bit field 23 FXS (1) symval (1) Value BT.656 and Y/C Mode OF(value) DEFAULT Raw Data Mode Field external synchronization enable bit. 0 VCTL3 is an output. 1 VCTL3 is an external field sync input. OUTPUT FSINPUT 22 VXS OF(value) DEFAULT Vertical external synchronization enable bit. 0 VCTL2 is an output. 1 VCTL2 is an external vertical sync input.
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www.ti.com Video Display Registers Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) Description (1) Bit field 11 DVEN symval (1) Value BT.656 and Y/C Mode OF(value) DEFAULT Raw Data Mode Default value enable bit. 0 Blanking value is output during non-sourced active pixels. Not used. 1 Default value is output during non-sourced active pixels. Not used. BLANKING DV 10 RESMPL OF(value) DEFAULT Chroma re-sampling enable bit. 0 DISABLE Not used.
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www.ti.com Video Display Registers 4.12.3 Video Display Frame Size Register (VDFRMSZ) The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT). The FPCOUNT starts at 0 and counts to FRMWIDTH - 1 before restarting. The FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting.
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www.ti.com Video Display Registers Figure 4-34. Video Display Horizontal Blanking Register (VDHBLNK) 31 28 27 16 Reserved HBLNKSTOP R-0 R/W-0 15 14 12 11 0 HBDLA Reserved HBLNKSTART R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-9.
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www.ti.com Video Display Registers Figure 4-35. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 31 28 27 16 Reserved VBLNKYSTART1 R-0 R/W-0 15 12 11 0 Reserved VBLNKXSTART1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-10.
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www.ti.com Video Display Registers Table 4-11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions Description Bit field (1) symval (1) Value 31-28 Reserved - 0 27-16 VBLNKYSTOP1 OF(value) 0-FFFh DEFAULT 0 15-12 Reserved - 0 11-0 OF(value) 0-FFFh DEFAULT 0 (1) VBLNKXSTOP1 BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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www.ti.com Video Display Registers Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions (continued) Description Bit 11-0 field (1) symval VBLNKXSTART2 (1) Value OF(value) 0-FFFh DEFAULT 0 BT.656 and Y/C Mode Raw Data Mode Specifies the pixel (in FPCOUNT) where VBLNK active edge occurs for field 2. Specifies the pixel (in FPCOUNT) where vertical blanking begins (VBLNK active edge) for field 2. 4.12.
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www.ti.com Video Display Registers 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) The video display field 1 image offset register (VDIMGOFF1) defines the field 1 image offset and specifies the starting location of the displayed image relative to the start of the active display. The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP1 + IMGVOFF1). If the NV bit is set, ILCOUNT is reset to 1 when FLCOUNT = VBLNKYSTOP1 - IMGVOFF1.
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www.ti.com Video Display Registers Table 4-14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions (continued) Description Bit 11-0 field (1) symval IMGHOFF1 (1) Value OF(value) 0-FFFh DEFAULT 0 BT.656 and Y/C Mode Raw Data Mode Specifies the display image horizontal Specifies the display image horizontal offset in pixels from the start of each line offset in pixels from the start of each line of active video in field 1. This must be an of active video in field 1.
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www.ti.com Video Display Registers 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display. The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP2 + IMGVOFF2). If the NV bit is set, ILCOUNT is reset to 1 when FLCOUNT = VBLNKYSTOP2 - IMGVOFF2.
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www.ti.com Video Display Registers 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active display. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image. Displayed image pixel output stops when IPCOUNT = IMGHSIZE2.
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www.ti.com Video Display Registers Figure 4-43. Video Display Field 1 Timing Register (VDFLDT1) 31 28 27 16 Reserved FLD1YSTART R-0 R/W-0 15 12 11 0 Reserved FLD1XSTART R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-18.
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www.ti.com Video Display Registers Table 4-19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions (continued) Bit 11-0 field (1) symval FLD2XSTART (1) Value OF(value) 0-FFFh DEFAULT 0 Description Specifies the pixel on the first line of field 2 where the FLD output is asserted. 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO threshold to determine when to load more display data.
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www.ti.com Video Display Registers Table 4-20. Video Display Threshold Register (VDTHRLD) Field Descriptions (continued) Description Bit 11-10 9-0 field (1) symval (1) Value Reserved - 0 VDTHRLD1 OF(value) 0-3FFh DEFAULT 0 BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Field 1 threshold.
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www.ti.com Video Display Registers The video display field 1 vertical synchronization start register (VDVSYNS1) is shown in Figure 4-47 and described in Table 4-22. Figure 4-47. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) 31 28 27 16 Reserved VSYNCYSTART1 R-0 R/W-0 15 12 11 0 Reserved VSYNCXSTART1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-22.
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www.ti.com Video Display Registers Table 4-23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Descriptions (continued) Bit field (1) symval (1) Value 15-12 Reserved - 11-0 OF(value) 0-FFFh DEFAULT 0 VSYNCXSTOP1 0 Description Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Specifies the pixel where VSYNC is de-asserted in field 1. 4.12.
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www.ti.com Video Display Registers Figure 4-50. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) 31 28 27 16 Reserved VSYNCYSTOP2 R-0 R/W-0 15 12 11 0 Reserved VSYNCXSTOP2 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-25.
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www.ti.com Video Display Registers 4.12.22 Video Display Event Register (VDDISPEVT) The video display event register (VDDISPEVT) is programmed with the number of EDMA events to be generated for display field 1 and field 2. The video display event register (VDDISPEVET) is shown in Figure 4-52 and described in Table 4-27. Figure 4-52.
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www.ti.com Video Display Registers Figure 4-53. Video Display Clipping Register (VDCLIP) 31 24 23 16 CLIPCHIGH CLIPCLOW R/W-1111-0000 R/W-0001-0000 15 8 7 0 CLIPYHIGH CLIPYLOW R/W-1110-1011 R/W-0001-0000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-28.
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www.ti.com Video Display Registers Figure 4-54. Video Display Default Display Value Register (VDDEFVAL) 31 24 23 16 CRDEFVAL CBDEFVAL R/W-0 R/W-0 15 8 7 0 Reserved YDEFVAL R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-55. Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode 31 20 19 16 Reserved DEFVAL R/W-0 R/W-0 15 0 DEFVAL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-29.
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www.ti.com Video Display Registers Figure 4-56. Video Display Vertical Interrupt Register (VDVINT) 31 30 28 27 16 VIF2 Reserved VINT2 R/W-0 R-0 R/W-0 15 14 12 11 0 VIF1 Reserved VINT1 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-30. Video Display Vertical Interrupt Register (VDVINT) Field Descriptions Bit field 31 VIF2 (1) symval (1) Value OF(value) DEFAULT Description Vertical interrupt (VINT) in field 2 enable bit.
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www.ti.com Video Display Registers Figure 4-57. Video Display Field Bit Register (VDFBIT) 31 28 27 16 Reserved FBITSET R-0 R/W-0 15 12 11 0 Reserved FBITCLR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-31.
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www.ti.com Video Display Registers Table 4-32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions Description Bit field (1) symval (1) Value 31-28 Reserved - 27-16 VBITCLR1 OF(value) 0-FFFh DEFAULT 0 15-12 Reserved - 0 11-0 VBITSET1 OF(value) 0-FFFh DEFAULT 0 (1) 0 BT.656 and Y/C Mode Raw Data Mode Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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www.ti.com Video Display Registers Recommended Values Table 4-33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions (continued) Description Bit 11-0 field (1) symval VBITSET2 (1) Value OF(value) 0-FFFh DEFAULT 0 BT.656 and Y/C Mode Raw Data Mode Specifies the first line with an EAV of V = Not used. 1 indicating the start of field 2 vertical blanking. 4.
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www.ti.com Video Display FIFO Registers 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4-35. These registers provide EDMA write access to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers. The function of the video display FIFO mapping registers is listed in Table 4-36.
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SPRUEM1 – May 2007 General-Purpose I/O Operation Signals not used for video display or video capture can be used as general-purpose input/output (GPIO) signals. Topic 5.1 150 .................................................................................................. Page GPIO Registers .......................................................................
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www.ti.com GPIO Registers 5.1 GPIO Registers The GPIO register set includes required registers such as peripheral identification and emulation control. The GPIO registers are listed in Table 5-1. See the device-specific datasheet for the memory address of these registers. Table 5-1. Video Port Registers Offset Address (1) (1) Acronym Register Name Section 00h VPPID Video Port Peripheral Identification Register Section 5.1.1 04h PCR Video Port Peripheral Control Register Section 5.1.
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www.ti.com GPIO Registers 5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The video port peripheral identification register (VPPID) is shown in Figure 5-1 and described in Table 5-2. Figure 5-1.
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www.ti.com GPIO Registers 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation during emulation. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend.
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www.ti.com GPIO Registers 5.1.3 Video Port Pin Function Register (PFUNC) The video port pin function register (PFUNC) selects the video port pins as GPIO. Each bit controls either one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO. The GPIO feature should not be used for pins that are used as part of the capture or display operation. For pins that have been muxed out for use by another peripheral, the PFUNC bits will have no effect.
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www.ti.com GPIO Registers Table 5-4. Video Port Pin Function Register (PFUNC) Field Descriptions (continued) (1) Bit field 10 PFUNC10 symval (1) Value Description OF(value) DEFAULT PFUNC10 bit determines if VDATA[19-12] pins function as GPIO. 0 Pins function normally. NORMAL VDATA10TO19 1 Pins function as GPIO pin. 9-1 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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www.ti.com GPIO Registers 5.1.4 Video Port Pin Direction Register (PDIR) The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as an input. The PDIR settings do not affect pins where the corresponding PFUNC bit is not set. The video port pin direction register (PDIR) is shown in Figure 5-4 and described in Table 5-5. Figure 5-4.
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www.ti.com GPIO Registers Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions (continued) (1) Bit field 12 PDIR12 symval (1) Value Description OF(value) DEFAULT PDIR12 bit controls the direction of the VDATA[15–12] pins. 0 Pins function as input. VDATA12TO15IN 11-9 8 VDATA12TO15OUT 1 Pins function as output. Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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www.ti.com GPIO Registers 5.1.5 Video Port Pin Data Input Register (PDIN) PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin's input buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit. The read-only video port pin data input register (PDIN) is shown in Figure 5-5 and described in Table 5-6. Figure 5-5.
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www.ti.com GPIO Registers 5.1.6 Video Port Pin Data Output Register (PDOUT) The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output. Writes do not affect pins not configured as GPIO outputs. The bits in PDOUT are set or cleared by writing to this register directly. A read of PDOUT returns the value of the register not the value at the pin (that might be configured as an input).
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www.ti.com GPIO Registers Table 5-7. Video Port Pin Data Out Register (PDOUT) Field Descriptions (continued) (1) Bit field 20 PDOUT20 symval (1) Value Description OF(value) DEFAULT PDOUT20 bit drives the VCTL1 pin only when the GPIO is configured as output. When reading data, returns the bit value in PDOUT20, does not return input from pin. When writing data, writes to PDOUT20 bit. 0 Pin drives low. 1 Pin drives high.
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www.ti.com GPIO Registers 5.1.7 Video Port Pin Data Set Register (PDSET) PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s. The video port pin data set register (PDSET) is shown in Figure 5-7 and described in Table 5-8. Figure 5-7.
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www.ti.com GPIO Registers 5.1.8 Video Port Pin Data Clear Register (PDCLR) PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT. Writing a 0 has no effect. Register reads return all 0s. The video port pin data clear register (PDCLR) is shown in Figure 5-8 and described in Table 5-9. Figure 5-8.
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www.ti.com GPIO Registers 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The GPIOs can be used to generate DSP interrupts or EDMA events. The PIEN selects which pins may be used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set. Interrupts are enabled on a GPIO pin when the corresponding bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR.
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www.ti.com GPIO Registers 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The PIPOL determines the GPIO pin signal polarity that generates an interrupt. The video port pin interrupt polarity register (PIPOL) is shown in Figure 5-10 and described in Table 5-11. Figure 5-10.
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www.ti.com GPIO Registers 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt. A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt (the corresponding bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR) and the appropriate transition (as selected by the corresponding PIPOL bit) occurs on the pin.
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www.ti.com GPIO Registers 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s. The video port pin interrupt clear register (PICLR) is shown in Figure 5-12 and described in Table 5-13. Figure 5-12.
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SPRUEM1 – May 2007 VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic .................................................................................................. 6.1 6.2 6.3 6.4 6.5 Overview ................................................................................ Interface ................................................................................. Operational Details ...................................................
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www.ti.com Overview 6.1 Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of interpolation is dependent on the resolution needed. When the video port is used in transport stream interface (TCI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream (Figure 6-1).
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www.ti.com Operational Details 6.3 Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems. This is addressed in the MPEG transport packets by transmitting timing information in the adaptation fields of selected data packets. This serves as a reference for timing comparison in the receiving system.
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www.ti.com Enabling VIC Port 6.4 Enabling VIC Port Perform the following steps to enable the VIC port. 1. Clear the GO bit in the VIC control register (VICCTL) to 0. 2. Set the PRECISION bits in VICCTL to the desired precision. 3. Set the VIC clock divider register (VICDIV) bits to appropriate value based on the precision and interpolation frequency. 4. Set the GO bit in VICCTL to 1. 5. The VIC input register (VICIN) is written into every time a new input code is available for interpolation.
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www.ti.com VIC Port Registers 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in Figure 6-3 and described in Table 6-4. Figure 6-3. VIC Control Register (VICCTL) 31 16 Reserved R-0 15 4 3 1 0 Reserved PRECISION GO R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-4.
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www.ti.com VIC Port Registers 6.5.2 VIC Input Register (VICIN) The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1. The VIC module uses the MSBs of VICIN for precision values less than 16. The VIC input register (VICIN) is shown in Figure 6-4 and described in Table 6-5. Figure 6-4.
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www.ti.com VIC Port Registers 6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. The VIC interpolation frequency is obtained by dividing the module clock. The divider value written to VICDIV is: Divider + RoundƪDCLKńR] where DCLK is the CPU clock divided by 2, and R is the desired interpolation frequency. The interpolation frequency depends on precision β.
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