TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide Literature Number: SPRUEQ7C February 2010
SPRUEQ7C – February 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 8 .............................................................................................. 8 .................................................................................................................. 8 1.
www.ti.com List of Figures EMIF Functional Block Diagram 2 EMIF Asynchronous Interface ........................................................................................... 11 3 EMIF to 8-bit and 16-bit Memory Interfaces 4 Timing Waveform of an Asynchronous Read Cycle in Normal Mode .............................................. 15 5 Timing Waveform of an Asynchronous Write Cycle in Normal Mode 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 4 ..........................
www.ti.com List of Tables .................................................................................................................. 1 EMIF Pins 2 Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode..................................... 10 3 Description of the Asynchronous Configuration Register (ACFGn) ................................................. 12 4 Description of the Asynchronous Wait Cycle Configuration Register (AWCCR) ..................................
Preface SPRUEQ7C – February 2010 Read This First About This Manual This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
User's Guide SPRUEQ7C – February 2010 Asynchronous External Memory Interface (EMIF) 1 Introduction This document describes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). 1.
Architecture www.ti.com 1.3 Functional Block Diagram Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins. Section 2.2 contains a description of the entities internal to the device that can send requests to the EMIF, along with their prioritization. Section 2.3 describes the EMIF's external pins and summarizes their purpose when interfacing with SDRAM and asynchronous devices. Figure 1.
Architecture 2.3 www.ti.com Signal Descriptions Table 1 describes the function of each of the EMIF pins. Table 1. EMIF Pins 2.4 Pins(s) I/O Description EM_ A[22:0] O EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is sent to the device. EM_BA[1:0] O EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address that is sent to the device. EM_CS[5:2] O Active-low chip enable pin for asynchronous devices.
Architecture www.ti.com 2.5.1 Interfacing to Asynchronous Memory Figure 2 shows the EMIF's external pins used in interfacing with an asynchronous device. Of special note is the connection between the EMIF and the external device's address bus. The EMIF address pin EM_A[0] always provides the least significant bit of a 32-bit word address.
Architecture 2.5.2 www.ti.com Programmable Asynchronous Parameters The EMIF allows a high degree of programmability for shaping asynchronous accesses. The programmable parameters are: • Setup: The time between the beginning of a memory cycle (address valid) and the activation of the output enable or write enable strobe • Strobe: The time between the activation and deactivation of output enable or write enable strobe.
Architecture www.ti.com Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued) Parameter Description ASIZE Asynchronous Device Bus Width. This field determines the data bus width of the asynchronous interface in the following way: • ASIZE = 0 selects an 8-bit bus • ASIZE = 1 selects a 16-bit bus The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in Section 2.5.1.
Architecture 2.5.4 www.ti.com Read and Write Operations in Normal Mode Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, the EM_CS signal operates as a chip enable signal, active throughout the duration of the memory access. 2.5.4.
Architecture www.ti.com Figure 4.
Architecture 2.5.4.2 www.ti.com Asynchronous Write Operations (Normal Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
Architecture www.ti.com Figure 5.
Architecture 2.5.5 www.ti.com Read and Write Operations in Select Strobe Mode Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is set to 1. In this mode, the EM_CS pin functions as a strobe signal and is therefore only active during the strobe period of an access cycle. 2.5.5.
Architecture www.ti.com Figure 6.
Architecture 2.5.5.2 www.ti.com Asynchronous Write Operations (Select Strobe Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled.
Architecture www.ti.com Figure 7.
Architecture 2.5.6 www.ti.com NAND Flash Mode NAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NAND Flash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register (NANDFCR). Table 11 displays the bit fields present in NANDFCR and briefly describes their use.
Architecture www.ti.com 2.5.6.2 Connecting to NAND Flash Figure 8 shows the EMIF external pins used to interface with a NAND Flash device. EMIF address lines are used to drive the NAND Flash device's command latch enable (CLE) and address latch enable (ALE) signals. NOTE: The EMIF will not control the NAND Flash device's write protect pin. The write protect pin must be controlled outside of the EMIF. Figure 8.
Architecture 2.5.6.4 www.ti.com NAND Read and Program Operations A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles (as described above) must be completed by the EMIF. Software must be used to request the appropriate asynchronous accesses to complete a NAND Flash access cycle.
Architecture www.ti.com 2.5.6.6 ECC Generation If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC calculation for up to 512 bytes for the corresponding chip select care. To perform the ECC calculation, the CS2ECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is independent of each other.
Architecture 2.5.6.7 www.ti.com NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) indicates the raw status of the EM_WAITn pin. The EM_WAITn pin should be connected to the NAND Flash device's R/B signal, so that it indicates whether or not the NAND Flash device is busy. During a read, the R/B signal will transition and remain low while the NAND Flash retrieves the data requested. Once the R/B signal transitions high, the requested data is ready and should be read by the EMIF.
Architecture www.ti.com 2.5.8 Extended Wait Mode and the EM_WAIT Pin The Extended Wait mode is a mode in which the external asynchronous device may assert control over the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the asynchronous configuration register (ACFGn).
Architecture 2.5.11 www.ti.com Interrupt Support The EMIF has a single interrupt source (Table 13) mapped to the ARM interrupt controller. For more information on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). Table 13. EMIF Interrupt ARM Event Acronym Source 60 EMIFAINT EMIF The EMIF supports a single interrupt to the CPU. Section 2.5.11.1 details the generation and internal masking of EMIF interrupts and Section 2.5.11.
Architecture www.ti.com 2.5.11.2 Interrupt Multiplexing The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with another interrupt and is therefore always available. 2.5.12 Program Execution Since the EMIF does not have byte enable or data mask pins, byte accesses to memory are not supported when the data bus width is equal to 16 bits. When performing data accesses on a 16-bit bus, this may be worked around by performing a write modify read back operation.
Use Cases 3 www.ti.com Use Cases The EMIF allows a high degree of programmability for shaping asynchronous accesses. As previously stated, the shape and duration of the asynchronous access is determined by controlling the widths of the SETUP, STROBE, HOLD, and turnaround periods. The widths of these periods are configured by programming the asynchronous configuration register (ACFGn) for the corresponding chip select space. See Section 2.5.3 and Section 4.3 for more information.
Use Cases www.ti.com 3.1.2 Meeting AC Timing Requirements for ASRAM When configuring the EMIF to interface to ASRAM, you must consider the AC timing requirements of the ASRAM as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn). For a read access, Table 15 to Table 17 list the AC timing specifications that must be considered.
Use Cases www.ti.com Figure 12. Timing Waveform of an ASRAM Read Setup Strobe Hold EM_CS tRC(m) EM_A[21:0] EM_BA[1:0] EM_OE tCOD(m) tSU tACC(m) tOH(m) tH EM_D[15:0] For a write access, Table 18 lists the AC timing specifications that must be satisfied. Table 18.
Use Cases www.ti.com Figure 13 shows an asynchronous write access and describes how the EMIF and ASRAM AC timing requirements work together to define values for W_SETUP, W_STROBE, and W_HOLD. From Figure 13, the following equations may be derived. tcyc is the period at which the EMIF operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds.
Use Cases 3.1.3 www.ti.com Taking Into Account PCB Delays The equations described in Section 3.1.2 are for the ideal case, when board design does not contribute delays. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device driver behaves. Signals driven by the EMIF will be delayed when they reach the ASRAM and conversely. Table 19 lists the delays shown in Figure 14 and Figure 15 due to PCB affects.
Use Cases www.ti.com Figure 14. Timing Waveform of an ASRAM Read with PCB Delays Setup 2 1 Hold 4 Strobe 3 EM_CS tCS tCS EM_CS (ASRAM) EM_A[21:0]/ EM_BA[1:0] tEM_A tEM_A tRC(m) EM_A[21:0]/ EM_BA[1:0] (ASRAM) EM_OE tEM_OE tEM_OE EM_OE (ASRAM) tH tSU tEM_D tEM_D EM_D[15:0] tCOD(m) tACC(m) tOH(m) EM_D[15:0] (ASRAM) From Figure 15, the following equations may be derived. tcyc is the period at which the EMIF operates.
Use Cases www.ti.com W_STROBE w W_SETUP ) W_STROBE w max W_HOLD w max ǒ ǒ t WP(m) *1 t cyc Ǔ ǒtEM_A ) tAW(m) * tEM_WEǓ ǒt EM_D ) t DS(m) * t EM_WEǓ , t cyc t cyc Ǔ ǒt EM_WE ) t WR(m) * t EM_AǓ ǒtEM_WE ) t DH(m) * t EM_DǓ t cyc , t cyc W_SETUP ) W_STROBE ) W_HOLD w *1 *1 t WC(m) *3 t cyc Figure 15.
Use Cases www.ti.com 3.1.4 Example Using TC5516100FT-12 This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12 ASRAM with the EMIF. The following assumptions are made: • • ASRAM is connected to chip select space 3 (EM_CS[3]) EMIF clock speed is 100 MHZ (tcyc = 10 nS) Table 20 lists the data sheet specifications for the EMIF and Table 21 lists the data sheet specifications for the ASRAM. Table 20.
Use Cases www.ti.com Inserting these values into the equations defined above allows you to determine the values for SETUP, STROBE, HOLD, and TA. For a read: R_SETUP ) R_STROBE w ǒtEM_A ) tACC(m) ) tSU ) tEM_DǓ t cyc R_SETUP ) R_STROBE ) R_HOLD w R_HOLD w ǒt H * t EM_D * t OH(m) * t EM_AǓ TA w t cyc ǒt EM_CS ) T COD(m) ) t EM_DǓ t cyc *1 w (0.27 ) 12 ) 5 ) 0.45) * 1 w 0.78 10 t RC(m) *3 w t cyc *1 w *1 w ǒ12 Ǔ * 3 w * 1.8 10 (0 * 0.45 * 3 * 0.27) * 1 w * 1.37 10 (0.36 ) 7 ) 0.45) * 1 w *0.
Use Cases www.ti.com Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 23. In this example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle configuration register (AWCCR) does not need to be programmed. Table 23. Configuring A2CR for TC5516100FT-12 Example 3.2 Parameter Setting SS Select Strobe mode. • SS = 0. Places EMIF in Normal Mode.
Use Cases 3.2.2 www.ti.com Meeting AC Timing Requirements for NAND Flash When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn). As described in Section 2.5.
Use Cases www.ti.com From Figure 16, the following equations may be derived. tcyc is the period at which the EMIF operates. The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle.
Use Cases www.ti.com To determine the required EMIF configuration to interface to the NAND Flash for a write operation, Table 27 lists the NAND AC timing parameters for a command latch, address latch, and data input latch that must be considered. Table 27.
Use Cases www.ti.com Figure 17. Timing Waveform of a NAND Flash Command Write Setup Hold Strobe tCH(m) EM_CS tWC(m) tALH(m) ALE_EM_A[1] tCLH(m) CLE_EM_A[2] tWP(m) tCS(m) tALS(m) tCLS(m) EM_WE tDS(m) tDH(m) EM_D[7:0] Figure 18.
Use Cases www.ti.com Figure 19.
Use Cases www.ti.com 3.2.3 Example Using Hynix HY27UA081G1M This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M NAND Flash with the EMIF. The following assumptions are made: • • NAND Flash is connected to chip select space 2 (EM_CS[2]) EMIF clock speed is 100 MHZ (tcyc = 10 nS) Table 28 lists the data sheet specifications for the EMIF and Table 29 lists the data sheet specifications for the NAND Flash. Table 28.
Use Cases www.ti.com Inserting these values into the equations defined above allows you to determine the values for SETUP, STROBE, HOLD, and TA. For a read: R_SETUP w R_STROBE w max t CLR(m) * 1 w 10 * 1 w 0 t cyc 10 ǒ Ǔ ǒ ǒt REA(m) ) t SUǓ t cyc R_SETUP ) R_STROBE w R_HOLD w , Ǔ ǒ Ǔ t RP * 1 w 65 * 1 w 5.
Use Cases www.ti.com Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as in Table 30. In this example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the Extended Wait mode of the EMIF is not used, therefore the asynchronous wait cycle configuration register (AWCCR) does not need to be programmed. Table 30.
Registers 4 www.ti.com Registers The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers (MMRs). Table 32 lists the memory-mapped registers for the EMIF. See the device-specific data manual for the memory address of these registers. All other register offset addresses not listed in Table 32 should be considered as reserved locations and the register contents should not be modified. NOTE: The EMIF MMRs only support word (4 byte) accesses.
Registers www.ti.com 4.1 Revision Code and Status Register (RCSR) The revision code and status register (RCSR) is shown in Figure 20 and described in Table 33. Figure 20. Revision Code and Status Register (RCSR) 31 30 29 16 Reserved MODID R-x R-Fh 15 8 7 0 REVMAJ REVMIN R-2h R-2h LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset Table 33.
Registers 4.2 www.ti.com Asynchronous Wait Cycle Configuration Register (AWCCR) The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for extended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number of extended wait cycles can be configured. the AWCCR is shown in Figure 21 and described in Table 34.
Registers www.ti.com Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued) Bit 17-16 Field CS2_WAIT 15-8 Reserved 7-0 MEWC Value 0-3h Description EM_WAIT[5:2] pin map for chip select 2. By default, the EM_WAIT[2] pin is used for chip select 2. 0 EM_WAIT[2] pin is used. 1h EM_WAIT[3] pin is used. 2h EM_WAIT[4] pin is used. 3h EM_WAIT[5] pin is used.
Registers 4.3 www.ti.com Asynchronous n Configuration Registers (A1CR-A4CR) The asynchronous configuration register (ACFGn) is used to configure the shaping of the address and control signals during an access to asynchronous memory. It is also used to program the width of asynchronous interface and to select from various modes of operation. This register can be written prior to any transfer, and any asynchronous transfer following the write will use the new configuration.
Registers www.ti.com 4.4 EMIF Interrupt Raw Register (EIRR) The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generated interrupts. The bits in EIRR are set when an interrupt condition occurs, regardless of the status of the EMIF interrupt mask set register (EIMSR) and EMIF interrupt mask clear register (EIMCR). Writing a 1 to a bit clears the bit and the corresponding bit in the EMIF interrupt mask register (EIMR).
Registers 4.5 www.ti.com EMIF Interrupt Mask Register (EIMR) Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor and clear the status of the EMIF’s hardware-generated interrupts. The main difference between the two registers is that when the bits in EIMR are set, an active-high pulse is sent to the CPU interrupt controller.
Registers www.ti.com Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued) Bit Field 0 ATM Value Description Asynchronous Timeout Masked.
Registers 4.6 www.ti.com EMIF Interrupt Mask Set Register (EIMSR) The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit in EIMR will always read 0 and no interrupts are generated when the associated interrupt condition occurs.
Registers www.ti.com Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued) Bit 0 Field Value ATMSET Description Asynchronous Timeout Mask Set. This bit enables the asynchronous timeout interrupt. Writing a 1 to this bit sets this bit and the ATMCLR bit in the EMIF interrupt mask clear register (EIMCR), and enables the asynchronous timeout interrupt. To clear this bit, a 1 must be written to the ATMCLR bit in EIMCR.
Registers 4.7 www.ti.com EMIF Interrupt Mask Clear Register (EIMCR) The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs. If a bit is read as 0, the corresponding bit in EIMR will always read 0 and no interrupts are generated when the corresponding interrupt condition occurs.
Registers www.ti.com Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued) Bit 0 Field Value ATMCLR Description Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout interrupt is enabled. Writing a 1 to this bit clears this bit and the ATMSET bit in the EMIF interrupt mask set register (EIMSR), and disables the asynchronous timeout interrupt. To set this bit, a 1 must be written to the ATMSET bit in EIMSR.
Registers 4.8 www.ti.com NAND Flash Control Register (NANDFCR) The NAND Flash control register (NANDFCR) is shown in Figure 27 and described in Table 40. Figure 27. NAND Flash Control Register (NANDFCR) 31 16 Reserved R-0 15 11 10 9 8 Reserved 12 CS5ECC CS4ECC CS3ECC CS2ECC R-0 R/W-0 R/W-0 R/W-0 R/W-0 3 2 1 0 Reserved CS5NAND CS4NAND CS3NAND CS2NAND R-0 R/W-0 R/W-0 R/W-0 R/W-0 7 4 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 40.
Registers www.ti.com 4.9 NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) is shown in Figure 28 and described in Table 41. Figure 28. NAND Flash Status Register (NANDFSR) 31 16 Reserved R-0 15 4 3 0 Reserved WAITST R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 41. NAND Flash Status Register (NANDFSR) Field Descriptions Bit Field Value 31-4 Reserved 0 3-0 WAITST 0-Fh 4.10 Description Reserved Raw status of the EM_WAITn input pin.
Registers www.ti.com Figure 29.
www.ti.com Appendix A Revision History Table 43 lists the changes made since the previous version of this document. Table 43. Document Revision History Reference Additions/Modifications/Deletions Figure 1 Changed figure. Table 1 Changed table. Figure 2 Changed figure. Section 2.5.6.2 Figure 8 Changed paragraph. Changed figure.
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