TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide Literature Number: SPRUE30B September 2006
SPRUE30B – September 2006 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 7 1 Introduction................................................................................................................ 9 2 3 4 1.1 Purpose of the Peripheral ....................................................................................... 9 1.2 Features ..........................................................................................
MMC Command Register (MMCCMD) 4.14 MMC Argument Register (MMCARGHL) .................................................................... 54 4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ...................................................... 55 4.16 MMC Data Response Register (MMCDRSP) ............................................................... 57 4.17 MMC Command Index Register (MMCCIDX) ............................................................... 57 4.
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MMC/SD Card Controller Block Diagram ............................................................................... MMC/SD Controller Interface Diagram .................................................................................. MMC Configuration and SD Configuration Diagram ................................................................... MMC/SD Controller Clocking Diagram .
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A-1 6 MMC/SD Controller Pins Used in Each Mode .......................................................................... MMC/SD Mode Write Sequence ......................................................................................... MMC/SD Mode Read Sequence ......................................................................................... Description of MMC/SD Interrupt Requests .................................
Preface SPRUE30B – September 2006 Read This First About This Manual This manual describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards. The MMC/SD protocol performs the communication between the MMC/SD controller and MMC/SD card(s).
www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC.
User's Guide SPRUE30B – September 2006 Multimedia Card (MMC)/Secure Digital (SD) Card Controller 1 Introduction This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM644x Digital Media System-on-Chip (DMSoC). 1.1 Purpose of the Peripheral A number of applications use the multimedia card (MMC)/secure digital (SD) card to provide removable data storage. The MMC/SD card controller provides an interface to external MMC and SD cards.
www.ti.com Peripheral Architecture Figure 1. MMC/SD Card Controller Block Diagram ARM CPU MMC/SD interface DMA requests Interrupts Status and registers MMC/SD card interface CLK divider FIFO 1.
www.ti.com Peripheral Architecture Figure 2. MMC/SD Controller Interface Diagram MMCs or SD cards ARM MMC/SD controller Native signals CMD Native packets DAT0 or DAT0−3 CLK Memory EDMA Figure 3.
www.ti.com Peripheral Architecture 2.1 Clock Control There are two clocks, the function clock and the memory clock, in the MMC/SD controller (Figure 4). The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD card(s). The MMC/SD controller is capable of operating with a function clock up to 100 MHz. The memory clock appears on the SD_CLK pin of the MMC/SD controller interface.
www.ti.com Peripheral Architecture 2.2 Signal Descriptions Table 1 shows the MMC/SD controller pins that each mode uses. The MMC/SD protocol uses the clock, command (two-way communication between the MMC controller and memory card), and data (DAT0 for MMC card, DAT0-3 for SD card) pins. Table 1.
www.ti.com Peripheral Architecture Figure 5. MMC/SD Mode Write Sequence Timing Diagram CMD Busy low 2 CRC bytes Data Start bit End bit Start bit End bit CLK Table 2. MMC/SD Mode Write Sequence 2.3.2 Portion of the Sequence Description WR CMD Write command: A 6-byte WRITE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a 6-byte response of type R1 to acknowledge the WRITE_BLOCK to the ARM.
www.ti.com Peripheral Architecture Figure 6. MMC/SD Mode Read Sequence Timing Diagram CMD 1 transfer source bit 2 CRC bytes Data Start bit End bit CLK Table 3. MMC/SD Mode Read Sequence 2.4 Portion of the Sequence Description RD CMD Read command: A 6-byte READ_SINGLE_BLOCK command token is sent from the ARM to the card. CMD RSP Command response: The card sends a response of type R1 to acknowledge the READ_SINGLE_BLOCK command to the ARM.
www.ti.com Peripheral Architecture A high-level operational description is as follows: • Data is written to the FIFO through the MMC data transmit register (MMCDXR). Data is read from the FIFO through the MMC data receive register (MMCDRR). This is true for both the CPU and EDMA driven transactions; however, for the EDMA transaction, the EDMA access to the FIFO is transparent.
www.ti.com Peripheral Architecture 2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register (MMCDRR) and write 32 bits at a time to the FIFO by writing to the MMC data transmit register (MMCDXR). However, since the memory card is an 8-bit device, it transmits or receives one byte at a time.
www.ti.com Peripheral Architecture Figure 9.
www.ti.com Peripheral Architecture 2.6 2.6.1 FIFO Operation During Card Read Operation EDMA Reads The FIFO controller manages the activities of reading the data in from the card and issuing EDMA read events. Each time an EDMA read event is issued, an EDMA read request interrupt generates. Figure 10 provides details of the FIFO controllers operation. As data is received from the card, it is read into the FIFO.
www.ti.com Peripheral Architecture Figure 10.
www.ti.com Peripheral Architecture 2.7 2.7.1 FIFO Operation During Card Write Operation EDMA Writes The FIFO controller manages the activities of accepting data from the CPU or EDMA and passing the data to the MMC/SD controller. The FIFO controller issues EDMA write events as appropriate. Each time an EDMA write event is issued, an EDMA write request interrupt generates. Data is written into the FIFO through MMCDXR. Note that the EDMA access to MMCDXR is transparent.
www.ti.com Peripheral Architecture Figure 11.
www.ti.com Peripheral Architecture 2.8 Reset Considerations The MMC/SD peripheral has two reset sources: hardware reset and software reset. 2.8.1 Software Reset Considerations A software reset (such as a reset that the emulator generates) does not cause the MMC/SD controller registers to alter. After a software reset, the MMC/SD controller continues to operate as it was configured prior to the reset. 2.8.
www.ti.com Peripheral Architecture 2.9.3 Initializing the Clock Controller Registers (MMCCLK) A clock divider in the MMC/SD controller divides-down the function clock to produce the memory clock. Load the divide-down value into the CLKRT bits in the MMC memory clock control register (MMCCLK).
www.ti.com Peripheral Architecture 2.9.7 Monitoring Activity in the MMC/SD Mode This section describes registers and specific register bits that you can use to obtain the status of the MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1). 2.9.7.
www.ti.com Peripheral Architecture 2.9.7.8 Determining When Last Data has Been Written to Card (SanDisk SD cards) Some SanDisk brand SD™ cards exhibit a behavior that requires a multiple-block write command to terminate with a STOP (CMD12) command before the data write sequence completes. To enable support of this function, the transfer done interrupt (TRNDNE) is provided. Set the ETRNDNE bit in MMCIM to enable the TRNDNE interrupt.
www.ti.com Peripheral Architecture 2.10 Interrupt Support 2.10.1 Interrupt Events and Requests The MMC/SD controller generates the interrupt requests described in Table 4. When an interrupt event occurs, its flag bit is set in the MMC status register 0 (MMCST0). If the enable bits corresponding to each flag are set in the MMC interrupt mask register (MMCIM), an interrupt request generates. All such requests are multiplexed to a single MMC/SD interrupt request from the MMC/SD peripheral to the ARM CPU.
www.ti.com Peripheral Architecture 2.11 DMA Event Support The MMC/SD controller is capable of generating EDMA events for both read and write operations in order to request service from an EDMA controller. Based on the FIFO threshold setting, the EDMA event signals generate every time 128-bit or 256-bit data is transferred from the FIFO. 2.12 Power Management You can put the MMC/SD peripheral in reduced-power modes to conserve power during periods of low activity.
www.ti.com Procedures for Common Operations 3 Procedures for Common Operations 3.1 Card Identification Operation Before the MMC/SD controller starts data transfers to or from memory cards in the MMC/SD native mode, it must first identify how many cards are present on the bus and configure them. For each card that responds to the ALL_SEND_CID broadcast command, the controller reads that card’s unique card identification address (CID) and then assigns it a relative address (RCA).
www.ti.com Procedures for Common Operations Figure 12. MMC Card Identification Procedure 3.1.2 SD Card Identification Procedure The SD card identification procedure is: 1. Use the MMC command register (MMCCMD) to issue the GO_IDLE_STATE (CMD0) command to the MMC cards. Using MMCMD to issue the CMD0 command puts all cards (MMC and SD) in the idle state and no response from the cards is expected. 2.
www.ti.com Procedures for Common Operations 6. Repeat step 4 and step 5 to identify and retrieve relative addresses from all remaining SD cards until no card responds to the CMD2 command. No card responding within 5 memory clock cycles indicates that all cards have been identified and the MMC card and the identification procedure terminates. The sequence of events in this operation is shown in Figure 13. Figure 13.
www.ti.com Procedures for Common Operations 3.2 MMC/SD Mode Single-Block Write Operation Using CPU To perform a single-block write, the block length must be 512 bytes and the same length needs to be set in both the MMC/SD controller and the memory card. The procedure for this operation is: 1. Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the higher part of the address to MMCARGH and the low part of the address to MMCARGL. 2.
www.ti.com Procedures for Common Operations Figure 14. MMC/SD Mode Single-Block Write Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL.
www.ti.com Procedures for Common Operations 3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA To perform a single-block write, the block length must be 512 bytes and the same length must be set in both the MMC/SD controller and the card. The procedure for this operation is as follows: 1. Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL. 2.
www.ti.com Procedures for Common Operations Figure 15. MMC/SD Mode Single-Block Read Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_SINGLE_BLOCK Is CRCWR = 1? Is DXRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION 3.5 MMC controller register ARG HIGH ARG LOW Select one card with relative card address (RCA) while de−selecting the other cards.
www.ti.com Procedures for Common Operations 3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controller and the card. Note: The procedure in this section uses a STOP_TRANSMISSION command to end the block transfer. This assumes that the value in the MMC number of blocks counter register (MMCNBLK) is 0.
www.ti.com Procedures for Common Operations Figure 16. MMC/SD Multiple-Block Write Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_SINGLE_BLOCK Is CRCWR = 1? Is DXRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION SPRUE30B – September 2006 Submit Documentation Feedback MMC controller register ARG HIGH ARG LOW Select one card with relative card address (RCA) while de−selecting the other cards.
www.ti.com Procedures for Common Operations 3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controller and the card. The procedure for this operation is: 1. Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL. 2. Read card CSD to determine the card's maximum block length. 3.
www.ti.com Procedures for Common Operations Figure 17. MMC/SD Mode Multiple-Block Read Operation MMC controller register content RCA ADDRESS HIGH RCA ADDRESS LOW SEL/DESEL. CARD BLK ADDRESS HIGH BLK ADDRESS LOW SET_BLOCKLEN READ_MULT_BLOCK Is TOUTRD = 1? Is CRCRD = 1? Is DRRDY = 1? NEXT DATA BYTE STOP_TRANSMISSION 3.9 MMC controller register ARG HIGH ARG LOW Select one card with relative card address (RCA) while de−selecting the other cards.
www.ti.com Registers 4 Registers Table 5 lists the memory-mapped registers for the multimedia card/secure digital (MMC/SD) card controller. See the device-specific data manual for the memory address of these registers. Table 5. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers 40 Offset Acronym Register Description Section 00h MMCCTL MMC Control Register Section 4.1 04h MMCCLK MMC Memory Clock Control Register Section 4.2 08h MMCST0 MMC Status Register 0 Section 4.
www.ti.com Registers 4.1 MMC Control Register (MMCCTL) The MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controller. Set or clear the DATRST and CMDRST bits at the same time to reset or enable the MMC controller. The MMC control register (MMCCTL) is shown in Figure 18 and described in Table 6. Figure 18.
www.ti.com Registers 4.2 MMC Memory Clock Control Register (MMCCLK) The MMC memory clock control register (MMCCLK) is used to: • Select whether the CLK pin is enabled or disabled (CLKEN bit). • Select how much the function clock is divided-down to produce the memory clock (CLKRT bits). When the CLK pin is enabled, the MMC controller drives the memory clock on this pin to control the timing of communications with attached memory cards. For more details about clock generation, see Section 2.1.
www.ti.com Registers 4.3 MMC Status Register 0 (MMCST0) The MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1 on each bit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set the corresponding interrupt enable bit in the MMC interrupt mask register (MMCIM). In most cases, when a status bit is read, it is cleared.
www.ti.com Registers Table 8. MMC Status Register 0 (MMCST0) Field Descriptions (continued) Bit 5 4 3 2 1 0 Field Value CRCWR Write-data CRC error. 0 A write-data CRC error has not been detected. 1 A write-data CRC error has been detected. TOUTRS Response time-out event. 0 A response time-out event has not occurred. 1 A time-out event has occurred while the MMC controller was waiting for a response to a command. TOUTRD Read-data time-out event.
www.ti.com Registers 4.4 MMC Status Register 1 (MMCST1) The MMC status register 1 (MMCST1) records specific events or errors. There are no interrupts associated with these events or errors. The MMC status register 1 (MMCST1) is shown in Figure 21 and described in Table 9. Figure 21.
www.ti.com Registers 4.5 MMC Interrupt Mask Register (MMCIM) The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts. If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU. The MMC interrupt mask register (MMCIM) is shown in Figure 22 and described in Table 10. Figure 22.
www.ti.com Registers Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued) Bit 3 2 1 0 4.6 Field Value Description ETOUTRD Read-data time-out event (TOUTRD) interrupt enable. 0 Read-data time-out event interrupt is disabled. 1 Read-data time-out event interrupt is enabled. ERSPDNE Command/response done (RSPDNE) interrupt enable. 0 Command/response done interrupt is disabled. 1 Command/response done interrupt is enabled. EBSYDNE Busy done (BSYDNE) interrupt enable.
www.ti.com Registers 4.7 MMC Data Read Time-Out Register (MMCTOD) The MMC data read time-out register (MMCTOD) defines how long the MMC controller waits for the data from a memory card before recording a time-out condition in the TOUTRD bit of the MMC status register 0 (MMCST0). If the corresponding ETOUTRD bit in the MMC interrupt mask register (MMCIM) is set, an interrupt is generated when the TOUTRD bit is set in MMCST0.
www.ti.com Registers 4.8 MMC Block Length Register (MMCBLEN) The MMC block length register (MMCBLEN) specifies the data block length in bytes. This value must match the block length setting in the memory card. The MMC block length register (MMCBLEN) is shown in Figure 25 and described in Table 13. Figure 25. MMC Block Length Register (MMCBLEN) 31 16 Reserved R-0 15 12 11 0 Reserved BLEN R-0 R/W-200h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13.
www.ti.com Registers 4.9 MMC Number of Blocks Register (MMCNBLK) The MMC number of blocks register (MMCNBLK) specifies the number of blocks for a multiple-block transfer. The MMC number of blocks register (MMCNBLK) is shown in Figure 26 and described in Table 14. Figure 26. MMC Number of Blocks Register (MMCNBLK) 31 16 Reserved R-0 15 0 NBLK R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
www.ti.com Registers 4.11 MMC Data Receive Register (MMCDRR) The MMC data receive register (MMCDRR) is used for storing the received data from the MMC controller. The CPU or the DMA controller can read data from this register. MMCDRR expects the data in little-endian format. The MMC data receive register (MMCDRR) is shown in Figure 28 and described in Table 16. Figure 28. MMC Data Receive Register (MMCDRR) 31 0 DRR R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 16.
www.ti.com Registers 4.13 MMC Command Register (MMCCMD) Note: Writing to the MMC command register (MMCCMD) causes the MMC controller to send the programmed command. Therefore, the MMC argument register (MMCARGHL) must be loaded properly before a write to MMCCMD. The MMC command register (MMCCMD) specifies the type of command to be sent and defines the operation (command, response, additional activity) for the MMC controller.
www.ti.com Registers Table 18. MMC Command Register (MMCCMD) Field Descriptions (continued) Bit Field 12 STRMTP 11 Value Stream enable. 0 If WDATX = 1, the data transfer is a block transfer. The data transfer stops after the movement of the programmed number of bytes (defined by the programmed block size and the programmed number of blocks). 1 If WDATX = 1, the data transfer is a stream transfer.
www.ti.com Registers 4.14 MMC Argument Register (MMCARGHL) Note: Do not modify the MMC argument register (MMCARGHL) while it is being used for an operation. The MMC argument register (MMCARGHL) specifies the arguments to be sent with the command specified in the MMC command register (MMCCMD). Writing to MMCCMD causes the MMC controller to send a command; therefore, MMCARGHL must be configured before writing to MMCCMD.
www.ti.com Registers 4.15 MMC Response Registers (MMCRSP0-MMCRSP7) Each command has a preset response type. When the MMC controller receives a response, it is stored in some or all of the eight MMC response registers (MMCRSP7-MMCRSP0). The response registers are updated as the responses arrive, even if the CPU has not read the previous contents. As shown in Figure 33, Figure 34, Figure 35, and Figure 36 each of the MMC response registers holds up to 16 bits.
www.ti.com Registers Table 21. R1, R3, R4, R5, or R6 Response (48 Bits) Bit Position of Response Register 47-40 MMCCIDX 39-24 MMCRSP7 23-8 MMCRSP6 7-0 MMCRSP5(1) - MMCRSP4-0 (1) Bits 7-0 of the response are stored to bits 7-0 of MMCRSP5. Table 22.
www.ti.com Registers 4.16 MMC Data Response Register (MMCDRSP) After the MMC controller sends a data block to a memory card, the return byte from the memory card is stored in the MMC data response register (MMCDRSP). The MMC data response register (MMCDRSP) is shown in Figure 37 and described in Table 23. Figure 37. MMC Data Response Register (MMCDRSP) 31 16 Reserved R-0 15 8 7 0 Reserved DRSP R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23.
www.ti.com Registers 4.18 MMC FIFO Control Register (MMCFIFOCTL) The MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39 and described in Table 25. Figure 39. MMC FIFO Control Register (MMCFIFOCTL) 31 16 Reserved R-0 15 2 1 0 Reserved 5 4 ACCWD 3 FIFOLEV FIFODIR FIFORST R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25.
www.ti.com Appendix A Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Section 1.2 Changed third bullet. Added seventh bullet. Section 1.3 Added second sentence. Section 1.5 Deleted third bullet. Section 2 Changed second sentence in second paragraph. Figure 3 Changed Figure 3. Section 2.1 Changed first sentence in second paragraph.
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