TMS320DM643x DMP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRU941A April 2007
SPRU941A – April 2007 Submit Documentation Feedback
Contents Preface.............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 2 3 4 5 Purpose of the Peripheral ..................................................................................... 11 ........................................................................................................
5.1 Transmit Identification and Version Register (TXIDVER) ................................................. 71 5.2 Transmit Control Register (TXCONTROL) .................................................................. 71 5.3 Transmit Teardown Register (TXTEARDOWN) ............................................................ 72 5.4 Receive Identification and Version Register (RXIDVER) .................................................. 73 5.5 Receive Control Register (RXCONTROL) 5.
Appendix A Glossary ...................................................................................................... 117 Appendix B Revision History ............................................................................................
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6 EMAC and MDIO Block Diagram ........................................................................................ Typical Ethernet Configuration ........................................................................................... Ethernet Frame Format ....................................................................................
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) .............................................. 93 MAC Control Register (MACCONTROL) ................................................................................ 94 MAC Status Register (MACSTATUS) ................................................................................... 96 Emulation Control Register (EMCONTROL)........................................................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 8 EMAC and MDIO Signals ................................................................................................. Ethernet Frame Description ............................................................................................... Basic Descriptor Description ....................................................................................
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 A-1 B-1 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ......... 92 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ................ 92 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ....................... 93 MAC Control Register (MACCONTROL) Field Descriptions .........................................................
Preface SPRU941A – April 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM643x Digital Media Processor (DMP). Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.
User's Guide SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM643x Digital Media Processor (DMP).
www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts.
www.ti.com Peripheral Architecture 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E). In difference from this standard, the EMAC peripheral does not use the Transmit Coding Error signal MTXER.
www.ti.com Peripheral Architecture Figure 2. Typical Ethernet Configuration MTCLK MTXD(3−0) 2.5 MHz or 25 MHz MTXEN EMAC MCOL System core MCRS MRCLK MRXD(3−0) Physical layer device (PHY) Transformer MRXDV MDIO MRXER RJ−45 MDCLK MDIO Table 1. EMAC and MDIO Signals 14 Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock.
www.ti.com Peripheral Architecture 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document. 2.4.1 Ethernet Frame Format All the Ethernet technologies use the same frame structure.
www.ti.com Peripheral Architecture 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
www.ti.com Peripheral Architecture Table 3. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor Pointer The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field.
www.ti.com Peripheral Architecture 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1. The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
www.ti.com Peripheral Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, using the linked list queue mechanism discussed in Section 2.5.2. The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
www.ti.com Peripheral Architecture 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor (Figure 6) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 6.
www.ti.com Peripheral Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
www.ti.com Peripheral Architecture 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.5.4.
www.ti.com Peripheral Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure. 2.5.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
www.ti.com Peripheral Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; /* Pointer to data buffer */ Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */ Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */ } EMAC_Desc; /* Packet Flags 2.5.5.
www.ti.com Peripheral Architecture 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
www.ti.com Peripheral Architecture 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag This flag is used when a receive queue is being torn down, or aborted, instead of being filled with received data. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. 2.5.5.
www.ti.com Peripheral Architecture 2.5.5.21 No Match (NOMATCH) Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. 2.
www.ti.com Peripheral Architecture 2.6.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to control the interrupt signal to the CPU: • The INTEN bit in the EMAC control module interrupt control register (EWCTL) globally enables and disables the interrupt signal to the CPU.
www.ti.com Peripheral Architecture Figure 9. MDIO Module Block Diagram Peripheral clock EMAC control module USERINT LINKINT Configuration bus 2.7.1.1 MDIO clock generator PHY monitoring MDIO interface MDCLK MDIO PHY polling Control registers and logic MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock (PLL1/6) in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHZ, although typical operation would be 1.
www.ti.com Peripheral Architecture 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
www.ti.com Peripheral Architecture 2.7.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Enable the MDIO module by setting the ENABLE bit in CONTROL. 3.
www.ti.com Peripheral Architecture 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers.
www.ti.com Peripheral Architecture 2.8 EMAC Module This section discusses the architecture and basic function of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 10) interfaces to the outside world through the Media Independent Interface (MII) and interfaces to the system core through the EMAC control module.
www.ti.com Peripheral Architecture 2.8.1.4 Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the CPU through the bus arbiter in the EMAC control module. 2.8.1.5 Transmit FIFO The transmit FIFO consists of three cells of 64–bytes each and associated control logic. The FIFO buffers data in preparation for transmission. 2.8.1.
www.ti.com Peripheral Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is communicated by use of 16-byte descriptors that are placed in an 8K-byte block of RAM in the EMAC control module. For transmit operations, each 16-byte descriptor describes a packet or packet fragment in the system's internal or external memory.
www.ti.com Peripheral Architecture In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation. Receive flow control prevents reception of frames on the EMAC until all of the triggering conditions clear, at which time frames may again be received by the EMAC. Receive flow control is enabled by the RXBUFFERFLOWEN bit in the MAC control register (MACCONTROL). The EMAC is configured for collision or IEEE 802.
www.ti.com Peripheral Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the first 64 bytes have been transmitted), the collision is ignored.
www.ti.com Peripheral Architecture 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
www.ti.com Peripheral Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. • Write the MAC address hash n registers (MACHASH1 and MACHASH2), if multicast addressing is desired.
www.ti.com Peripheral Architecture 2.10.4 Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Encoded Tag Protocol Type. The two octets immediately following the protocol type contain the 16-bit TCI field.
www.ti.com Peripheral Architecture 2.10.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors. Received frames are long frames, if their frame count exceeds the value in RXMAXLEN. The RXMAXLEN reset (default) value is 5EEh (1518 in decimal). Long received frames are either oversized or jabber frames.
www.ti.com Peripheral Architecture Table 4. Receive Frame Treatment Summary 42 Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel. 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel. 0 1 0 1 1 Proper/undersized data and control frames transferred to promiscuous channel.
www.ti.com Peripheral Architecture 2.10.
www.ti.com Peripheral Architecture 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7. 2.11.
www.ti.com Peripheral Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module. 2.
www.ti.com Peripheral Architecture 2.14.2 Hardware Reset Considerations When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initialized before being able to resume its data transmission, as described in Section 2.15. A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors.
www.ti.com Peripheral Architecture Example 4.
www.ti.com Peripheral Architecture 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.
www.ti.com Peripheral Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC module generates 18 interrupt events: • TXPENDn: Transmit packet completion interrupt for transmit channels 0 through 7 • RXPENDn: Receive packet completion interrupt for receive channels 0 through 7 • STATPEND: Statistics interrupt • HOSTPEND: Host error interrupt 2.16.1.
www.ti.com Peripheral Architecture Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue's associated receive completion pointer in the receive DMA state RAM.
www.ti.com Peripheral Architecture 2.16.2 MDIO Module Interrupt Events and Requests The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link • USERINT: Serial interface user command event complete interrupt 2.16.2.
www.ti.com Peripheral Architecture 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management on behalf of all of the peripherals on the device.
www.ti.com EMAC Control Module Registers 3 EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 7. EMAC Control Module Registers Offset 3.1 Acronym Register Description Section 04h EWCTL EMAC Control Module Interrupt Control Register Section 3.1 08h EWINTTCNT EMAC Control Module Interrupt Timer Count Register Section 3.
www.ti.com EMAC Control Module Registers 3.2 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an internal counter every time interrupts are enabled using the INTEN bit in the EMAC control module interrupt control register (EWCTL).
www.ti.com MDIO Registers 4 MDIO Registers Table 10 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 10. Management Data Input/Output (MDIO) Registers 4.1 Offset Acronym Register Description Section 0h VERSION MDIO Version Register Section 4.1 4h CONTROL MDIO Control Register Section 4.2 8h ALIVE PHY Alive Status register Section 4.3 Ch LINK PHY Link Status Register Section 4.
www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 14 and described in Table 12. Figure 14. MDIO Control Register (CONTROL) 31 30 29 20 19 18 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL 28 24 23 Reserved 21 PREAMBLE FAULT FAULTENB 17 Reserved 16 R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W-0 R-0 15 0 CLKDIV R/W-FFh LEGEND: R/W = R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 12.
www.ti.com MDIO Registers 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 15 and described in Table 13. Figure 15. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 13. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field 31-0 ALIVE 4.4 Value Description MDIO Alive bits.
www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 17 and described in Table 15. Figure 17. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 15.
www.ti.com MDIO Registers 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 18 and described in Table 16. Figure 18. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTMASKED R-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 16.
www.ti.com MDIO Registers 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 19 and described in Table 17. Figure 19. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 17.
www.ti.com MDIO Registers 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 20 and described in Table 18. Figure 20. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKED R-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 18.
www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 21 and described in Table 19. Figure 21. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKSET R-0 R/WS-0 LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set; -n = value after reset Table 19.
www.ti.com MDIO Registers 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 22 and described in Table 20. Figure 22. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKCLEAR R-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset Table 20.
www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 23 and described in Table 21. Figure 23. MDIO User Access Register 0 (USERACCESS0) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set; -n = value after reset Table 21.
www.ti.com MDIO Registers 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 24 and described in Table 22. Figure 24. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.
www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 25 and described in Table 23. Figure 25. MDIO User Access Register 1 (USERACCESS1) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set; -n = value after reset Table 23.
www.ti.com MDIO Registers 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 26 and described in Table 24. Figure 26. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5 Ethernet Media Access Controller (EMAC) Registers Table 25 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 25. Ethernet Media Access Controller (EMAC) Registers 68 Offset Acronym Register Description Section 0h TXIDVER Transmit Identification and Version Register Section 5.1 4h TXCONTROL Transmit Control Register Section 5.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 25. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 168h EMCONTROL Emulation Control Register Section 5.30 Section 16Ch FIFOCONTROL FIFO Control Register Section 5.31 170h MACCONFIG MAC Configuration Register Section 5.32 174h SOFTRESET Soft Reset Register Section 5.33 1D0h MACSRCADDRLO MAC Source Address Low Bytes Register Section 5.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 25. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 200h RXGOODFRAMES Good Receive Frames Register Section 5.49.1 204h RXBCASTFRAMES Broadcast Receive Frames Register Section 5.49.2 Section 5.48 Network Statistics Registers 70 208h RXMCASTFRAMES Multicast Receive Frames Register Section 5.49.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 27 and described in Table 26. Figure 27. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-0Ch 15 8 7 0 TXMAJORVER TXMINORVER R-0Ah R-07h LEGEND: R = Read only; -n = value after reset Table 26.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 29 and described in Table 28. Figure 29. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 28.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 30 and described in Table 29. Figure 30. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-0Ch 15 8 7 0 RXMAJORVER RXMINORVER R-0Ah R-07h LEGEND: R = Read only; -n = value after reset Table 29.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 32 and described in Table 31. Figure 32. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 31.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 33 and described in Table 32. Figure 33.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 34 and described in Table 33. Figure 34.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 35 and described in Table 34. Figure 35.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 36 and described in Table 35. Figure 36.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 37 and described in Table 36. Figure 37. MAC Input Vector Register (MACINVECTOR) 31 30 17 16 USERINT LINKINT 29 Reserved 18 HOSTPEND STATPEND R-0 R-0 R-0 R-0 R-0 15 8 7 0 RXPEND TXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 36.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.12 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 38 and described in Table 37. Figure 38.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.13 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 39 and described in Table 38. Figure 39.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.14 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 40 and described in Table 39. Figure 40.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 41 and described in Table 40. Figure 41.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.16 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 42 and described in Table 41. Figure 42. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 41.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.18 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 44 and described in Table 43. Figure 44. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTMASK STATMASK R-0 R/WS-0 R/WS-0 LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set, write of 0 has no effect; -n = value after reset Table 43.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.20 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 46 and described in Table 45. Figure 46.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 45. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 10-8 RXBROADCH 5 4-3 Frames containing errors are filtered. 1 Frames containing errors are transferred to memory. 0 Frames that do not address match are filtered.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 45.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.21 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 47 and described in Table 46. Figure 47.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.22 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 48 and described in Table 47. Figure 48.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.23 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 49 and described in Table 48. Figure 49. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-5EEh LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 48.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.25 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 51 and described in Table 50. Figure 51. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 50.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.27 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 53 and described in Table 52. Figure 53. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 LEGEND: R = Read only; WI = Write to increment; -n = value after reset Table 52.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.28 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 54 and described in Table 53. Figure 54.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 53. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit 3 Field 2 Reserved 1 LOOPBACK 0 Value RXBUFFERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled. Half-duplex mode: no flow control generated collisions are sent. Full-duplex mode: no outgoing pause frames are sent. 1 Receive flow control is enabled.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.29 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 55 and described in Table 54. Figure 55.
www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 54. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 10-8 7-3 2 1 0 Field RXERRCH Value 0-3h Reserved Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.30 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 56 and described in Table 55. Figure 56. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 55.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.32 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 58 and described in Table 57. Figure 58. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYPE MACCFIG R-1 R-1 LEGEND: R = Read only; -n = value after reset Table 57.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.34 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 60 and described in Table 59. Figure 60. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 59.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.36 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.38 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 64 and described in Table 63. Figure 64. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 63.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.40 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 66 and described in Table 65. Figure 66. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 65.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.42 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 68 and described in Table 67. Figure 68. MAC Address Low Bytes Register (MACADDRLO) 31 16 Reserved R-0 15 8 7 0 MACADDR0 MACADDR1 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 67.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.44 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in Figure 70 and described in Table 69. Figure 70. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 3 2 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 69.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.45 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 71 and described in Table 70. Figure 71. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 16 TXnHDP R/W-x 15 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 70.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.47 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 73 and described in Table 72. Figure 73. Transmit Channel n Completion Pointer Register (TXnCP) 31 16 TXnCP R/W-x 15 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 72.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see Figure 75) are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
www.ti.com Ethernet Media Access Controller (EMAC) Registers See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. 5.49.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.49.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.49.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun.
www.ti.com Appendix A Glossary Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor) — A small memory structure that describes a larger block of memory in terms of size, location, and state.
www.ti.com Appendix A Link — The transmission path between any two instances of generic cabling. Multicast MAC Address — A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC looks for only certain multicast addresses on a network to reduce traffic load.
www.ti.com Appendix B Revision History Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Section 2.4.1 Additions/Modifications/Deletions Changed last sentence. Table 2 Changed Data field Bytes and Description. Table 25 Changed Register Description for FRAME1024TUP. Section 5.49.32 Changed subsection. Section 5.49.33 Changed second bulleted item. Section 5.49.34 Changed second bulleted item. Section 5.49.
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