TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide Literature Number: SPRUFI5B March 2009 – Revised December 2010
SPRUFI5B – March 2009 – Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated
Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 13 2 3 4 ............................................................................................. 13 ................................................................................................................. 13 1.
www.ti.com ................................................................................. 70 4.2 MDIO Control Register (CONTROL) ................................................................................ 71 4.3 PHY Acknowledge Status Register (ALIVE) ....................................................................... 72 4.4 PHY Link Status Register (LINK) .................................................................................... 72 4.
www.ti.com .............................................. 115 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 115 5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 116 5.38 MAC Hash Address Register 2 (MACHASH2) ................................................................... 116 5.39 Back Off Test Register (BOFFTEST) ....................................................................
www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 14 2 Ethernet Configuration MII Connections................................................................................ 16 3 Ethernet Frame Format ................................................................................................... 18 4 Basic Descriptor Format ..............................................................................
www.ti.com 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 ........................................................... 92 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 MAC Input Vector Register (MACINVECTOR) ........................................................................ 94 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .............................
www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface............................................................................. 17 2 Ethernet Frame Description .............................................................................................. 18 3 Basic Descriptor Description ............................................................................................. 20 4 Receive Frame Treatment Summary ...................................................................
www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions .................................................. 94 49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions...................................
Preface SPRUFI5B – March 2009 – Revised December 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
Related Documentation From Texas Instruments www.ti.com SPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.
Related Documentation From Texas Instruments www.ti.com SPRUFI5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide This document describes the operation of the ethernet media access controller interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
User's Guide SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
Introduction • • 1.3 www.ti.com Emulation support Loopback mode Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts.
Architecture www.ti.com The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller. See Section 2.17.4 for details of interrupt multiplex logic of the EMAC control module. 1.
Architecture 2.2 www.ti.com Memory Map The EMAC peripheral includes internal memory that is used to hold information about the Ethernet packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention.
Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface 2.4 Signal Type Description EMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The EMAC_TXD and EMAC_TX_EN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation. EMAC_TXD[3-0] O Transmit data (EMAC_TXD).
Architecture 2.5 www.ti.com Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document. 2.5.
Architecture www.ti.com 2.5.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
Architecture www.ti.com Table 3. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor Pointer The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field.
Architecture www.ti.com 2.6.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in Section 2.6.1. The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
Architecture 2.6.3 www.ti.com Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.6.1, using the linked list queue mechanism discussed in Section 2.6.2. The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
Architecture www.ti.com 2.6.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor (Figure 6) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 6.
Architecture 2.6.4.1 www.ti.com Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
Architecture www.ti.com 2.6.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.6.4.
Architecture 2.6.5 www.ti.com Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure. 2.6.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
Architecture www.ti.com Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture 2.6.5.4 www.ti.com Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
Architecture www.ti.com 2.6.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue. 2.6.5.12 Jabber Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is a jabber frame and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
Architecture 2.7 www.ti.com EMAC Control Module The basic functions of the EMAC control module (Figure 8) are to interface the EMAC and MDIO modules to the rest of the system, and to provide for a local memory space to hold EMAC packet buffer descriptors. Local memory is used to help avoid contention to device memory spaces. Other functions include the bus arbiter, and interrupt control and pacing logic control. Figure 8.
Architecture www.ti.com 2.7.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into four separate interrupt signals that are mapped to a CPU interrupt via the CPU interrupt controller. The four separate sources of interrupt can be individually enabled for each channel by the CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN registers. 2.7.3.
Architecture 2.7.3.3 www.ti.com Receive Threshold Pulse Interrupt The EMAC control module receives the eight individual receive threshold interrupts originating from the EMAC module, one for each of the eight channels, and combines them into a single receive threshold pulse interrupt to the CPU. This receive threshold pulse interrupt is not paced.
Architecture www.ti.com 2.8 MDIO Module The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC). The DM36x device supports a single PHY being connected to the EMAC at any given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU. The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system.
Architecture 2.8.1.3 www.ti.com Active PHY Monitoring Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link state by reading the MDIO PHY link status register (LINK). Link change events are stored on the MDIO device and can optionally interrupt the CPU. This allows the system to poll the link status of the PHY device without continuously performing costly MDIO accesses. 2.8.1.
Architecture www.ti.com 2.8.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Enable the MDIO module by setting the ENABLE bit in CONTROL. 3.
Architecture 2.8.2.4 www.ti.com Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers.
Architecture www.ti.com 2.9 EMAC Module This section discusses the architecture and basic function of the EMAC module. 2.9.1 EMAC Module Components The EMAC module (Figure 10) interfaces to the outside world through the Media Independent Interface (MII) and interfaces to the system core through the EMAC control module.
Architecture 2.9.1.3 www.ti.com MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 2.9.1.4 Receive Address This sub-module performs address matching and address filtering based on the incoming packet’s destination address.
Architecture www.ti.com 2.9.2 EMAC Module Operational Overview After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block. The transmit DMA controller then fetches the first packet in the packet chain from memory.
Architecture www.ti.com 2.10 Media Independent Interface (MII) The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. 2.10.1 Data Reception 2.10.1.1 Receive Control Data received from the PHY is interpreted and output to the EMAC receive FIFO.
Architecture www.ti.com 2.10.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the 12-byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3h.
Architecture 2.10.2 www.ti.com Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.10.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the first 64 bytes have been transmitted), the collision is ignored.
Architecture www.ti.com 2.10.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
Architecture www.ti.com 2.11 Packet Receive Operation 2.11.1 Receive DMA Host Configuration To • • • • • • • • • • 2.11.2 configure the receive DMA for operation the host must: Initialize the receive addresses. Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. Write the MAC address hash n registers (MACHASH1 and MACHASH2), if hash matching multicast addressing is desired.
Architecture www.ti.com 2.11.3 Receive Address Matching The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM. A MAC address location in RAM is 53 bits wide and consists of: • • • • 48 bits of the MAC address.
Architecture 2.11.5 www.ti.com Host Free Buffer Tracking The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous), if receive QOS or receive flow control is used. Disabled channel free buffer values are do not cares. During initialization, the host should write the number of free buffers for each enabled channel to the appropriate receive channel n free buffer count registers (RXnFREEBUFFER).
Architecture www.ti.com • 2.11.8 If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last data byte. Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE), nonaddress matching frames that would normally be filtered are transferred to the promiscuous channel.
Architecture www.ti.com Table 4. Receive Frame Treatment Summary (continued) 2.11.9 Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN 1 X 1 1 0 Receive Frame Treatment Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred.
Architecture www.ti.com 2.12 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7. 2.12.
Architecture www.ti.com Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module. 2.
Architecture www.ti.com 2.15.2 Hardware Reset Considerations When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initialized before being able to resume its data transmission, as described in Section 2.16. A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors.
Architecture www.ti.com Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN = 0; EmacControlRegs->CONTROL.C_TX_EN = 0; EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0; EmacControlRegs->CONTROL.
Architecture www.ti.com 2.16.3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE 802.3 standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure the clock divider. To set the clock divider, supply an MDIO clock of 1 MHz.
Architecture 2.16.4 www.ti.com EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.
Architecture www.ti.com 2.17 Interrupt Support 2.17.
Architecture www.ti.com Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding bit in the transmit interrupt mask set register (TXINTMASKSET) to 1. Each of the eight transmit channel interrupts may be individually disabled by clearing the corresponding bit in the transmit interrupt mask clear register (TXINTMASKCLEAR) to 0.
Architecture www.ti.com 2.17.1.4 Statistics Interrupt The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to 8000 0000h, if enabled by setting the STATMASK bit in the MAC interrupt mask set register (MACINTMASKSET) to 1. The statistics interrupt is removed by writing to decrement any statistics value greater than 8000 0000h. As long as the most-significant bit of any statistics value is set, the interrupt remains asserted. 2.17.1.
Architecture 2.17.2 www.ti.com MDIO Module Interrupt Events and Requests The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link • USERINT: Serial interface user command event complete interrupt 2.17.2.
Architecture www.ti.com 2.18 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management on behalf of all of the peripherals on the device.
EMAC Control Module Registers 3 www.ti.com EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 7. EMAC Control Module Registers Slave VBUS Address Acronym 3.1 Register Description Section 0h CMIDVER Identification and Version Register Section 3.1 4h CMSOFTRESET Software Reset Register Section 3.2 8h CMEMCONTROL Emulation Control Register Section 3.
EMAC Control Module Registers www.ti.com 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) The software reset register (CMSOFTRESET) is shown in Figure 13 and described in Table 9. Figure 13. EMAC Control Module Software Reset Register (CMSOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions Bit 31-1 0 3.
EMAC Control Module Registers 3.4 www.ti.com EMAC Control Module Interrupt Control Register (CMINTCTRL) The interrupt control register (CMINTCTRL) is shown in Figure 15 and described in Table 11. Figure 15. EMAC Control Module Interrupt Control Register (CMINTCTRL) 31 30 18 17 16 Reserved Reserved INTPACEEN R/W-0 R-0 R/W-0 15 12 11 0 Reserved INTPRESCALE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11.
EMAC Control Module Registers www.ti.com 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 16 and described in Table 12. Figure 16. EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) 31 16 Reserved R-0 15 8 7 0 Reserved RXTHRESHEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12.
EMAC Control Module Registers 3.7 www.ti.com EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) The transmit interrupt enable register (CMTXINTEN) is shown in Figure 18 and described in Table 14. Figure 18. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
EMAC Control Module Registers www.ti.com 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 19 and described in Table 15. Figure 19.
EMAC Control Module Registers 3.9 www.ti.com EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in Figure 20 and described in Table 16. Figure 20. EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) 31 16 Reserved R-0 15 8 7 0 Reserved RXTHRESHINTTSTAT R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 16.
EMAC Control Module Registers www.ti.com 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 22 and described in Table 18. Figure 22. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEINTTSTAT R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 18.
EMAC Control Module Registers www.ti.com 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) The miscellaneous interrupt status register (EWMISCSTAT) is shown in Figure 23 and described in Table 19. Figure 23. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) 31 16 Reserved R-0 15 3 2 1 0 Reserved 4 STATPENDINTSTAT HOSTPENDINTSTAT LINKINTSTAT USERINTSTAT R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 19.
EMAC Control Module Registers www.ti.com 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) The receive interrupts per millisecond register (CMRXINTMAX) is shown in Figure 24and described in Table 20. Figure 24. EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) 31 16 Reserved R-0 15 6 5 0 Reserved RXIMAX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20.
MDIO Registers 4 www.ti.com MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers 4.1 Offset Acronym Register Description Section 0h VERSION MDIO Version Register Section 4.1 4h CONTROL MDIO Control Register Section 4.2 8h ALIVE PHY Alive Status register Section 4.3 Ch LINK PHY Link Status Register Section 4.
MDIO Registers www.ti.com 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 27 and described in Table 24. Figure 27.
MDIO Registers 4.3 www.ti.com PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 28 and described in Table 25. Figure 28. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/W1C-0 15 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 25. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field Value 31-0 ALIVE 0-FFFF FFFFh 4.4 Description MDIO Alive bits.
MDIO Registers www.ti.com 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 30 and described in Table 27. Figure 30. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 27.
MDIO Registers 4.6 www.ti.com MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 31 and described in Table 28. Figure 31. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTMASKED R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 28.
MDIO Registers www.ti.com 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 32 and described in Table 29. Figure 32. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTRAW R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 29.
MDIO Registers 4.8 www.ti.com MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 33 and described in Table 30. Figure 33. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKED R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 30.
MDIO Registers www.ti.com 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 34 and described in Table 31. Figure 34. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKSET R-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 31.
MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 35 and described in Table 32. Figure 35.
MDIO Registers www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 36 and described in Table 33. Figure 36. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 33.
MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 37 and described in Table 34. Figure 37. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34.
MDIO Registers www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 38 and described in Table 35. Figure 38. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 35.
MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 39 and described in Table 36. Figure 39. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5 Ethernet Media Access Controller (EMAC) Registers Table 37 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description 0h TXIDVER Transmit Identification and Version Register Section 5.1 Section 4h TXCONTROL Transmit Control Register Section 5.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset 84 Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC Configuration Register Section 5.33 174h SOFTRESET Soft Reset Register Section 5.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 200h RXGOODFRAMES Good Receive Frames Register Section 5.50.1 204h RXBCASTFRAMES Broadcast Receive Frames Register Section 5.50.2 208h RXMCASTFRAMES Multicast Receive Frames Register Section 5.50.
Ethernet Media Access Controller (EMAC) Registers 5.1 www.ti.com Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 40 and described in Table 38. Figure 40. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-0Ch 15 8 7 0 TXMAJORVER TXMINORVER R-02h R-0Ch LEGEND: R = Read only; -n = value after reset Table 38.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 42 and described in Table 40. Figure 42. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 40.
Ethernet Media Access Controller (EMAC) Registers 5.4 www.ti.com Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 43 and described in Table 41. Figure 43. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-0Ch 15 8 7 0 RXMAJORVER RXMINORVER R-02h R-0Ch LEGEND: R = Read only; -n = value after reset Table 41.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 44 and described in Table 42. Figure 44. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 42. Receive Control Register (RXCONTROL) Field Descriptions Bit 31-1 0 5.
Ethernet Media Access Controller (EMAC) Registers 5.7 www.ti.com Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 46 and described in Table 44. Figure 46.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 47 and described in Table 45. Figure 47.
Ethernet Media Access Controller (EMAC) Registers 5.9 www.ti.com Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 48 and described in Table 46. Figure 48.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 49 and described in Table 47. Figure 49.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 50 and described in Table 48. Figure 50. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 Reserved STATPEND HOSTPEND LINKINT USERINT R-0 R-0 R-0 R-0 R-0 15 23 16 TXPEND R-0 8 7 0 RXTHRESHPEND RXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 48.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 52 and described in Table 50. Figure 52.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 53 and described in Table 51. Figure 53.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 54 and described in Table 52. Figure 54.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 55 and described in Table 53. Figure 55.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 56 and described in Table 54. Figure 56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 54.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 58 and described in Table 56. Figure 58. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTMASK STATMASK R-0 R/W1S-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 56.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 60 and described in Table 58. Figure 60.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 Reserved Reserved 10-8 RXBROADCH 7-6 5 4-3 102 0 Frames containing errors are filtered. 1 Frames containing errors are transferred to memory. Receive copy all frames enable bit.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 58.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 61 and described in Table 59. Figure 61.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 62 and described in Table 60. Figure 62.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 63 and described in Table 61. Figure 63. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 61.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 65 and described in Table 63. Figure 65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 63.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 67 and described in Table 65. Figure 67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 LEGEND: R = Read only; WI = Write to increment; -n = value after reset Table 65.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 68 and described in Table 66. Figure 68.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 66. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit 4 3 Value TXFLOWEN Reserved 1 LOOPBACK Description Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode, regardless of the TXFLOWEN bit setting. The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 69 and described in Table 67. Figure 69.
Ethernet Media Access Controller (EMAC) Registers www.ti.com Table 67. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 10-8 7-3 2 1 0 112 Field RXERRCH Reserved Value 0-3h Description Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 70 and described in Table 68. Figure 70. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 68.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 72 and described in Table 70. Figure 72. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-18h R-44h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h R-3h LEGEND: R = Read only; -n = value after reset Table 70.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 74 and described in Table 72. Figure 74. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 72.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 78 and described in Table 76. Figure 78. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 76.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 80 and described in Table 78. Figure 80. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 78.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 82 and described in Table 80. Figure 82.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 83 and described in Table 81. Figure 83. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 81.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 85 and described in Table 83. Figure 85. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 16 TXnHDP R/W-x 15 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 83.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 87 and described in Table 85. Figure 87. Transmit Channel n Completion Pointer Register (TXnCP) 31 16 TXnCP R/W-x 15 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 85.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the MII bit in the MACCONTROL register is set, all statistics registers (see Figure 89) are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
Ethernet Media Access Controller (EMAC) Registers 5.50.4 www.ti.com Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC. A jabber frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was greater than RXMAXLEN bytes long • Had a CRC error, alignment error, or code error See Section 2.6.
Ethernet Media Access Controller (EMAC) Registers www.ti.com This may not be an exact count because the receive overruns statistic is independent of the other statistics, so if an overrun occurs at the same time as one of the other discard reasons, then the above sum double-counts that frame. 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) The total number of frames received on the EMAC that were filtered due to receive quality of service (QOS) filtering.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) The total number of IEEE 802.3X pause frames transmitted by the EMAC. Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC, so these error conditions have no effect on this statistic. Pause frames sent by software are not included in this count.
Ethernet Media Access Controller (EMAC) Registers www.ti.com CRC errors have no effect on this statistic. 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) The total number of frames when transmission was abandoned due to excessive collisions.
Ethernet Media Access Controller (EMAC) Registers www.ti.com • Was exactly 64-bytes long. (If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted, then the frame is recorded in this statistic). CRC errors, alignment/code errors, and overruns do not affect the recording of frames in this statistic. 5.50.
Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.33 Network Octet Frames Register (NETOCTETS) The total number of bytes of frame data received and transmitted on the EMAC.
www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor)— A small memory structure that describes a larger block of memory in terms of size, location, and state.
Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC looks for only certain multicast addresses on a network to reduce traffic load. The multicast address list of acceptable packets is specified by the application.
www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Section 1.3 Changed fourth paragraph.
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