TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) Boundary-Scan-Compatible – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory – Device Revision ID Readable by ARM • • • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch 90nm Process Technology 3.3-V and 1.8-V I/O, 1.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1.2 Description The processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1.3 Functional Block Diagram CCDC CCD C CCD/ CMOS Module 10b DAC Enhanced Enhanced DMA 64 channels channels 3PCC /TC (100 MHz er c Composite video Digital RGB/YUV 3A 3A VPFE IPIP IPIPE E LD/CM LD / Buffer Logic Figure 1-1 shows the functional block diagram of the DM355 device.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Contents 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) ................................................... 1 1.1 Features .............................................. 1 1.2 Description ............................................ 3 1.3 Functional Block Diagram ............................ 4 4 5 Device Overview ......................................... 6 5.3 Power Supplies ....
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device, including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc. Table 2-1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.2 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.3 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 2.3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4 Pin Functions The pin functions tables (Table 2-4 through Table 2-22) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL NAME NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions (continued) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-6.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-7.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE (1) OTHER (2) DESCRIPTION PRODUCT PREVIEW NAME NO. VREF J7 A I/O/Z Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not used, the VREF signal should be connected to VSS. IOUT E1 A I/O/Z Video DAC: Pre video buffer DAC output (1000 ohm to VFB).
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION PRODUCT PREVIEW EM_CE0/ GIO037 J16 I/O/Z VDD Async EMIF: Lowest numbered chip select. Can be programmed to be used for standard asynchronous memories (example: flash), OneNAND, or NAND memory. Used for the default boot and ROM boot modes.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-10.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.5 GPIO The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions. Table 2-11. GPIO Terminal Functions TERMINAL PRODUCT PREVIEW TYPE (1) OTHER (2) (3) C16 I/O/Z VDD GIO: GIO[000] Active low during MMC/SD boot (can be used as MMC/SD power control). Can be used as external clock input for Timer 3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) EM_A09 / GIO063 / AECFG[1] EM_A10 / GIO064 / AECFG[2] NO. P17 R18 TYPE (1) OTHER (2) (3) I/O/Z PD VDD Async EMIF: Address Bus bit[09] GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF Configuration AECFG[2:1] sets default for PinMux2.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-11. GPIO Terminal Functions (continued) YIN7 / GIO093 CIN0 / GIO094 CIN1 / GIO095 CIN2 / GIO096 CIN3 / GIO097 CIN4 / GIO098 / SPI2_SDI / SPI2_SDE NA[1] CIN5 / GIO099 / SPI2_SDE NA[0] CIN6 / GIO100 / SPI2_SD O NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol. Table 2-12.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.7 Universal Serial Bus (USB) Interface The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role Host/Slave support. However, no charge pump is included. TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION A7 A I/O/Z VDDA33_USB USB D+ (differential signal pair). When USB is not used, this signal should be connected to VSS_USB.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-14.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-15. UART Terminal Functions (continued) TERMINAL NAME NO. MMCSD1_DA TA0/ GIO019/ UART2_TXD A18 TYPE (1) OTHER (2) (3) I/O/Z VDD DESCRIPTION MMCSD1: DATA0 GIO: GIO019 UART2: TXD 2.4.10 I2C Interface The includes an I2C two-wire serial interface for control of external peripherals. This interface is multiplexed with GIO signals.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-17. SPI Terminal Functions (continued) TERMINAL NAME NO. CIN7/ GIO101/ SPI2_SCLK N3 CIN5/ GIO099/ SPI2_SDENA[0] M3 PRODUCT PREVIEW CIN4/ GIO098/ SPI2_SDI/ SPI2_SDENA[1] L4 CIN6/ GIO100/ SPI2_SDO/ K5 TYPE (1) I/O/Z I/O/Z I/O/Z I/O/Z OTHER (2) (3) DESCRIPTION PD VDD_VIN Standard CCD Analog Front End (AFE): Not used • YCC 16-bit: time multiplexed between chroma.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.4.13 Real Time Output (RTO) Interface The provides Real Time Output (RTO) interface. Table 2-19.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-20.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-21. System/Boot Terminal Functions (continued) TERMINAL NAME NO. EM_A08/ GIO062/ AECFG[0] T19 TYPE (1) I/O/Z OTHER (2) (3) PD VDD DESCRIPTION Async EMIF: Address bus bit 08 GIO: GIO[062] System: AECFG[0] sets default for: • PinMux2.EM_A0_BA1 - AEMIF address width (OneNAND, or NAND) • PinMux2.EM_A13_3 - AEMIF address width (OneNAND, or NAND) 2.4.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.5 Pin List Table 2-23 provides a complete pin description list in pin number order. Table 2-23. DM355 Pin Descriptions Name BGA ID CIN7 / GIO101 / SPI2_SCLK N3 Type Group (1) I/O CCDC / GIO / SPI2 Power Supply (2) VDD_VIN Description (4) PU Reset PD (3) State PD in Mux Control Standard CCD Analog Front End (AFE): NOT USED PINMUX0[1:0].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name CIN3 / GIO097 BGA ID J4 Type Group (1) I/O CCDC / GIO Power Supply (2) VDD_VIN Description (4) PU Reset PD (3) State PD in Mux Control Standard CCD Analog Front End (AFE): raw[11] PINMUX0[8].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name YIN5 / GIO091 BGA ID M5 Type Group (1) I/O CCDC / GIO Power Supply (2) VDD_VIN Description (4) PU Reset PD (3) State PD in Mux Control Standard CCD Analog Front End (AFE): raw[05] PINMUX0[10].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name CAM_HD / GIO085 BGA ID N5 Type Group (1) I/O CCDC / GIO Power Supply (2) VDD_VIN Description (4) PU Reset PD (3) State PD in Mux Control Horizontal synchronization signal that can be PINMUX0[11].CAM_ either an input (slave mode) or an output HD (master mode). Tells the CCDC when a new line starts.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA ID COUT5-G2 / GIO079 / PWM2A / RTO0 C1 Type Group (1) I/O VENC / GIO / PWM2 / RTO Power Supply (2) Description (4) PU Reset PD (3) State VDD_VOUT in Mux Control Digital Video Out: VENC settings determine function PINMUX1[5:4].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA ID FIELD / GIO070 / R2 / PWM3C H4 Type Group (1) I/O VENC / GIO / VENC / PWM3 Power Supply (2) Description (4) PU Reset PD (3) State VDD_VOUT in Mux Control Video Encoder: Field identifier for interlaced display formats PINMUX1[19:18].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name DDR_DQS[0] BGA ID V12 Type Group (1) I/O DDR Power Supply (2) VDD_DDR PU Reset PD (3) State in Description (4) Mux Control Data strobe input/outputs for each byte of the 16 bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Description (4) BGA ID Type Group Power Supply (2) DDR_VREF U10 PWR DDRI O VDD_DDR DDR: Voltage input for the SSTL_18 IO buffers VSSA_DLL R11 GND DDRD LL VDD_DDR DDR: Ground for the DDR DLL VDDA33_DDRDLL R10 PWR DDRD LL VDD_DDR DDR: Power (3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name EM_A09 / GIO063 / AECFG[1] BGA ID P17 Type Group (1) I/O AEMI F/ GIO / syste m Power Supply (2) VDD Description (4) PU Reset PD (3) State PD in L Mux Control Async EMIF: Address Bus bit[09] PINMUX2[0].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name EM_WE / GIO035 BGA ID J15 Type Group (1) I/O AEMI F/ GIO Power Supply (2) Description (4) PU Reset PD (3) State VDD out H Mux Control Async EMIF: Write Enable PINMUX2[8].EM_W E_OE NAND/SM/xD: WE (Write Enable) output GIO: GIO[035] EM_OE / GIO034 F19 I/O AEMI F/ GIO VDD out H Async EMIF: Output Enable PINMUX2[8].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA ID MMCSD1_DAT A3 / GIO022 / UART2_RTS B16 Type Group (1) I/O MMC SD / GIO / UART 2 Power Supply (2) VDD Description (4) PU Reset PD (3) State in MMCSD1: DATA3 Mux Control PINMUX3[9:8].GIO2 2 GIO: GIO[022] UART2: RTS MMCSD1_DAT A2 / GIO021 / UART2_CTS A16 I/O MMC SD / GIO / UART 2 VDD in MMCSD1: DATA2 PINMUX3[11:10].
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name USB_VBUS BGA ID Type Group E5 A I/O USBP HY (1) Power Supply (2) Description (4) PU Reset PD (3) State Mux Control For host or device mode operation, tie the VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) Name BGA ID Type Group (1) Power Supply (2) Description (4) PU Reset PD (3) State Mux Control PRODUCT PREVIEW RSV03 L1 A I/O/Z Reserved. This signal should be left as a No Connect or connected to VSS. RSV04 M1 A I/O/Z Reserved. This signal should be left as a No Connect or connected to VSS. RSV05 N2 A I/O/Z Reserved.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23. DM355 Pin Descriptions (continued) CVDD BGA ID Type Group (1) Power Supply (2) Description (4) PU Reset PD (3) State R8 PWR Core power (1.3 V) CVDD T17 PWR Core power (1.3 V) CVDD W19 PWR Core power (1.3 V) VDD F9 PWR Power for Digital IO (3.3 V) VDD F10 PWR Power for Digital IO (3.3 V) VDD F11 PWR Power for Digital IO (3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2.6 Device Support 2.6.1 Development Tools TI offers an extensive line of development tools for DM355 systems, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz).
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPRUED4 TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide This document describes the serial peripheral interface (SPI) in the TMS320DM35x Digital Media System-on-Chip (DMSoC).
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PRODUCT PREVIEW SPRUEE7 TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC).
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3 Detailed Device Description This section provides a detailed overview of the DM355 device. 3.1 ARM Subsystem Overview The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall DM355 system, including the components of the ARM Subsystem, the peripherals, and the external memories. 3.1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • – Image Pipe (IPIPE) – H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure) Video Processing Back End (VPBE) – On Screen Display (OSD) – Video Encoder Engine (VENC) Figure 3-1 shows the functional block diagram of the DM355 ARM Subsystem.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com 3.2.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.3.2 External Memories The ARM has access to the following External memories: • DDR2 / mDDR Synchronous DRAM • Asynchronous EMIF / OneNAND • NAND Flash • Flash card devices: – MMC/SD – xD – SmartMedia 3.3.3 Peripherals 3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-1.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5 Device Clocking 3.5.1 Overview PRODUCT PREVIEW The DM355 requires one primary reference clock . The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXOI. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2).
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.2 Supported Clocking Configurations for DM355-216 This section describes the only supported device clocking configurations for DM355-216. The DM355 supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. 3.5.2.1 Supported Clocking Configurations for DM355-216 (24 MHz reference) 3.5.2.1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.2.2 Supported Clocking Configurations for DM355-216 (36 MHz reference) 3.5.2.2.1 DM355-216 PLL1 (36 MHz reference) All supported clocking configurations for DM355-216 PLL1 with 36 MHz reference clock are shown in Table 3-4 Table 3-4.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.3 Supported Clocking Configurations for DM355-270 This section describes the only supported device clocking configurations for DM355-270. The DM355 supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. 3.5.3.1 Supported Clocking Configurations for DM355-270 (24 MHz reference) 3.5.3.1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-7. PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference) (continued) PREDIV PLLM POSTDIV PLL2 VCO 8 108 1 324 1 DDR PHY 324 DDR Clock 162 8 102 1 306 1 306 153 8 96 1 288 1 288 144 12 133 1 266 1 266 133 12 100 1 200 1 200 100 15 100 1 160 1 160 80 3.5.3.2 Supported Clocking Configurations for DM355-270 (36 MHz reference) 3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.3.2.2 DM355-270 PLL2 (36 MHz reference) All supported clocking configurations for DM355-270 PLL2 with 36 MHz reference clock are shown in Table 3-5 Table 3-9.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12 MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM355 DMSoC Univeral Serial Bus (USB) Controller User's Guide (SPRUED2) for more information. See the TMS320DM355 DMSoC ARM Subsystem User's Guide for more information on the System Control Module.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.6 PLL Controller (PLLC) This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM355 Digital Media System-on-Chip ARM Subsystem User's Guide for more information on the PLL controllers. 3.6.1 PLL Controller Module The DM355 has two PLL controllers that provide clocks to different components of the chip.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.6.2 PLLC1 PRODUCT PREVIEW PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 3-10, and Figure 3-3 describe the customizations of PLLC1 in the DM355.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 CLKMODE PLLEN CLKIN OSCIN 1 Pre-DIV (/8) PLL Post-DIV (/2 or /1) PLLDIV2 (/4) SYSCLK1 (ARM and MPEG/JPEG Coprocessor) SYSCLK2 (peripherals) PLLDIV3 (/3) SYSCLK3 (VPBE) PLLDIV4 (/4 or /2) SYSCLK4 (VPSS) 1 PLLDIV1 (/2) 0 0 PLLM (programmable) BPDIV (/3) PRODUCT PREVIEW AUXCLK (Peripherals, CLKOUT1) SYSCLKBP (CLKOUT2) Figure 3-3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.6.3 PLLC2 PRODUCT PREVIEW PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the PLLC2 registers. The following list, Table 3-11, and Figure 3-4 describe the customizations of PLLC2 in the DM355.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.7 Power and Sleep Controller (PSC) In the DM355 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of the operations of the PSC are transparent to software, such as power-on-reset operations.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Power management – Deep sleep and fast NAND boot control Bandwidth Management – Bus master DMA priority control For more information on the System Control Module refer to the ARM Subsystem User's Guide. • 3.9 Pin Multiplexing The DM355 makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-14. Reset Types (continued) Type Initiator Effect Module Reset ARM software Resets a specific module. Allows the ARM to independently reset any module. Module reset is intended as a debug tool not as a tool to use in production. 3.11 Default Device Configurations After POR, warm reset, and max reset, the chip is in its default configuration.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.11.2 PLL Configuration After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1 (typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.5 and Section 3.6.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16. Module Configuration (continued) ARM AlwaysOn ON Enable 32 BUS AlwaysOn ON Enable 33 BUS AlwaysOn ON Enable 34 BUS AlwaysOn ON Enable 35 BUS AlwaysOn ON Enable 36 BUS AlwaysOn ON Enable 37 BUS AlwaysOn ON Enable 38 BUS AlwaysOn ON Enable 39 Reserved Reserved Reserved Reserved 40 VPSS DAC Always On ON SyncRst 3.11.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0] = 01, indicating AEMIF (AEMIF/OneNand) boot. See Section 3.11.1 for information on the boot selection pins. 3.12.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • ARM ROM Boot - UART mode – No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART to ARM internal RAM (AIM) and transfers control to the user software. – Support for up to 30KB UBL (32KB - ~2KB for RBL stack) The general boot sequence is shown in Figure 3-6. For more information, refer to the ARM Subsystem User's Guide.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be avoided by removing power completely from a device or subsystem. The DM355 includes several power management features which are briefly described in Table 12-1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.14 64-Bit Crossbar Architecture The DM355 uses a 64-bit crossbar architecture to control access between device processors, subsystems and peripherals. It includes an EDMA Controller consisting of a DMA Transfer Controller (TC) and a DMA Channel Controller (CC). The TC provides two DMA channels for transfer between slave peripherals.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DMA Channels: Can be triggered by: " External events (for example, ASP TX Evt and RX Evt), " Software writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other DMAs. QDMA: The Quick DMA (QDMA) function is contained within the CC. DM355 implements 8 QDMA channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-19.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 4 Device Operating Conditions 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (3) (4) Supply voltage ranges Input voltage ranges All digital 1.8 V supplies -0.5 V to 2.5 V All analog 1.8 V supplies -0.5 V to 1.89 V All 3.3 V supplies -0.5 V to 4.4 V All 1.8 V I/Os -0.5 V to 2.3 V All 3.3 V I/Os -0.5 V to 3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 4.2 Recommended Operating Conditions MIN NOM Supply Voltage PRODUCT PREVIEW Supply Ground Voltage Input High Voltage Input Low DAC (3) Video Buffer (3) USB Temperature (1) (2) (3) (4) 92 MAX UNIT CVDD Supply voltage, Core 1.235 1.3 1.365 V VDDA_PLL1 Supply voltage, PLL1 1.235 1.3 1.365 V VDDA_PLL2 Supply voltage, PLL2 1.235 1.3 1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 4.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF PRODUCT PREVIEW A. 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) The data sheet provides timing at the device pin.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.1.2 Timing Parameters and Board Routing Analysis PRODUCT PREVIEW The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5.3 Power Supplies The power supplies of DM355 are summarized in Table 5-1. Table 5-1. Power Supplies Customer Tolerance Package Board Plane Supply 1.3 V PRODUCT PREVIEW 3.3 V ±5% ±5% 1.3 V 3.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.3.1 Power-Supply Sequencing In order to ensure device reliability, the DM355 requires the following power supply power-on and power-off sequences. See table Table 5-1 for a description of DM355 power supplies. Power-On: 1. Power on 1.3 V: CVDD, VDDA_PLL1/2, VDDD13_USB, VDDA13_USB 2. Power on 1.8 V: VDD_DDR, VDDA18, VDDA18_DAC 3. Power on 3.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.4 Reset 5.4.1 Reset Electrical Data/Timing Table 5-2. Timing Requirements for Reset (1) (2) (see Figure 5-4) DM355 NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.5 Oscillators and Clocks has two oscillator input/output pairs (MXI1/MXO1 and MXI2/MXO2) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 24 MHz (MXI1/MXO1) and 27 MHz (MXI2/MXO2). Optionally, the oscillator inputs are configurable for use with external clock oscillators.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-3. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System Oscillator PARAMETER MIN TYP MAX Start-up time (from power up until oscillating at stable frequency) Oscillation frequency 24 or 36 60 Frequency stability ms MHz ESR 5.5.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 5-5. Timing Requirements for MXI1/CLKIN1 (1) (2) (see Figure 5-7) MIN TYP MAX UNIT 1 tc(MXI1) Cycle time, MXI1/CLKIN1 27.7 (3) 41.6 (3) ns 2 tw(MXI1H) Pulse duration, MXI1/CLKIN1 high 0.45C 0.55C ns 3 tw(MXI1L) Pulse duration, MXI1/CLKIN1 low 0.45C 0.55C ns 4 tt(MXI1) Transition time, MXI1/CLKIN1 0.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 (1) (2) (see Figure 5-9) NO. DM355 PARAMETER MIN TYP MAX UNI T 1 tC(CLKOUT1) Cycle time, CLKOUT1 tc(MXI1) 2 tw(CLKOUT1H) Pulse duration, CLKOUT1 high 0.45P 0.55P ns ns 3 tw(CLKOUT1L) Pulse duration, CLKOUT1 low 0.45P 0.55P ns 4 tt(CLKOUT1) Transition time, CLKOUT1 0.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see Figure 5-11) NO. DM355 PARAMETER MIN TYP MAX UNIT 1 tC(CLKOUT3) Cycle time, CLKOUT3 2 tw(CLKOUT3H) Pulse duration, CLKOUT3 high tc(MXI1) /8 0.45P 0.55P ns 3 tw(CLKOUT3L) Pulse duration, CLKOUT3 low 0.45P 0.55P ns 4 tt(CLKOUT3) Transition time, CLKOUT3 0.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.6 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 2 1 GPIx 4 3 GPOx Figure 5-12. GPIO Port Timing 5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing Table 5-12.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7 External Memory Interface (EMIF) supports several memory and external device interfaces, including: • Asynchronous EMIF (AEMIF) for interfacing to SRAM. • OneNAND flash memories • NAND flash memories 5.7.1 Asynchronous EMIF (AEMIF) PRODUCT PREVIEW The EMIF supports the following features: • SRAM, etc.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7.1.3 AEMIF Electrical Data/Timing Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module (1) (see Figure 5-14 and Figure 5-15) DM355 NO .
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15) (continued) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15) (continued) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 EM_CE[1:0] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[13:0] EM_D[15:0] 11 EM_OE 14 EM_WAIT 2 Asserted 2 Deasserted PRODUCT PREVIEW Figure 5-16. EM_WAIT Read Timing Requirements EM_CE[1:0] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_BA[1:0] EM_A[13:0] EM_D[15:0] 28 25 EM_WE 2 EM_WAIT Asserted 2 Deasserted Figure 5-17.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 33 38 EM_CLK 39 EM_CE[1:0] 34 EM_ADV 35 31 36 37 30 Da EM_D[15:0] Da+n+1 Da+1 Da+2 Da+3 Da+4 Da+5 PRODUCT PREVIEW EM_BA0, EM_A[13:0], EM_BA1 Da+n EM_OE EM_WAIT Figure 5-18.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7.2 DDR2 Memory Controller The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. DDR2 / mDDR SDRAM plays a key role in a DM355-based system.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.8 MMC/SD The MMC/SD Controller has following features: • MultiMediaCard (MMC). • Secure Digital (SD) Memory Card. • MMC/SD protocol support. • SDIO protocol support. • Programmable clock frequency. • 256 bit Read/Write FIFO to lower system overhead. • Slave EDMA transfer capability. The MMC/SD Controller does not support SPI mode. 5.8.1 MMC/SD Electrical Data/Timing Table 5-15.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 10 9 7 SD_CLK 13 13 START SD_CMD 13 XMIT Valid Valid 13 Valid END Figure 5-19. MMC/SD Host Command Timing 9 7 10 SD_CLK 1 2 PRODUCT PREVIEW SD_CMD START XMIT Valid Valid Valid END Figure 5-20. MMC/SD Card Response Timing 10 9 7 SD_CLK 14 14 START SD_DATx 14 D0 D1 14 Dx END Figure 5-21.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9 Video Processing Sub-System (VPSS) Overview In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is tailored for seamlessly integrating the VPSS into an image/video processing system.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • • • • • • • Support for program lens shading correction. Support for 10-bit to 8-bit A-law compression. Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output. Support for generating output to range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area).
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.3 Hardware 3A (H3A) The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various parameters for processing the imaging/video data.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.9.1.4 VPFE Electrical Data/Timing Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23) DM355-216 NO. DM355-270 MIN MAX MIN MAX 18.52 100 14.81 100 UNIT 1 tc(PCLK) Cycle time, PCLK (1) 2 tw(PCLKH) Pulse duration, PCLK high 5.7 5.7 ns 3 tw(PCLKL) Pulse duration, PCLK low 5.7 5.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 8, 10 7, 9 HD/VD 11, 13 C_WE/C_FIELD 5 6 CI[7:0]/YI[7:0]/ CCD[13:0] Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing Table 5-19. Timing Requirements for VPFE (CCD) Master Mode (1) (see Figure 5-25) DM355 NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Mode (see Figure 5-26) NO.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • The following restrictions exist in the OSD module. • If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 720 currently. This is due to the limitation in the size of the line memory. • It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM while another uses ROM. 5.9.2.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • • Internal Color Bar Generation (100%/75%) YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input 5.9.2.3 VPBE Electrical Data/Timing Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27) DM355 NO. MIN MAX 13.33 160 PRODUCT PREVIEW 1 tc(PCLK) Cycle time, PCLK (1) 2 tw(PCLKH) Pulse duration, PCLK high 5.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 VCLKIN(A) (Positive Edge Clocking) VCLKIN(A) (Negative Edge Clocking) 10 9 VCTL(B) Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK (1) (2) (3) (see Figure 5-29) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK (1) (2) (see Figure 5-30) NO. DM355 PARAMETER MIN MAX 13.33 160 UNIT PRODUCT PREVIEW 17 tc(VCLK) Cycle time, VCLK 18 tw(VCLKH) Pulse duration, VCLK high 5.7 ns 19 tw(VCLKL) Pulse duration, VCLK low 5.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Video DAC Buffer VREF IBIAS IOUT CBG 0.1 mF RBIAS 2550W RLOAD VFB TVOUT 499W DAC Digital Input DAC Output Current Iout [mA] PRODUCT PREVIEW DIN <9:0> 1.4 mA MSB LSB 0 Example for External Circuit A. Connect IOUT to a high-impedance video buffer device. B. Place capacitors and resistors as close as possible to the DM355. C.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Video DAC and Buffer VREF IBIAS IOUT VFB TVOUT TV monitor CBG 0.1 mF RBIAS 2550 Ω Rfb = 1000 Ω Rout = 1070 Ω DAC Digital Input Video Buffer Output Voltage DIN <9:0> TVOUT [V] PRODUCT PREVIEW MSB VOH(VIDBUF) VOL(VIDBUF) LSB 0 A. Place capacitors and resistors as close as possible to the DM355. B. You must use the circuit shown in this diagram.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 USB 2.0 DM355 includes a USB Controller Module that is built around the Mentor USB Multi-Point High-Speed Dual Role Controller, endpoint memory, CPPI DMA controller and UTMI+ PHY. The controller conforms to USB 2.0 Specification. The USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) • USB 2.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 USB_DM VCRS USB_DP tper − tjr 90% VOH 10% VOL tf tr Figure 5-33. USB2.0 Integrated Transceiver Interface Timing USB PRODUCT PREVIEW VSS_USB_REF USB_R1 10 K W ±1% Figure 5-34.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Universal Asynchronous Receiver/Transmitter (UART) The contains 3 separate UART modules (1 with hardware flow control). These modules performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the CPU.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3 2 UART_TXDn Start Bit Data Bits 5 4 UART_RXDn Start Bit Data Bits Figure 5-35.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Serial Port Interface (SPI) The contains 3 separate SPI modules. These modules provide a programmable length shift register which allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data Out, and Enable). The SPI supports the following features: • Master mode operation • 2 chip selects for interfacing to multiple slave SPI devices.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPI Master Mode Timings (Clock Phase = 0) Table 5-29. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1) (see Figure 5-37) DM355 NO. MIN MAX UNIT 4 tsu(DIV-CLKL) Setup time, SPI_DI (input) valid before SPI_CLK (output) falling edge Clock Polarity = 0 .5P + 3 ns 5 tsu(DIV-CLKH) Setup time, SPI_DI (in put) valid before SPI_CLK (output) rising edge Clock Polarity = 1 .
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPI Master Mode Timings (Clock Phase = 1) Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38) MIN MAX UNIT 13 tsu(DIV-CLKL) Setup time, SPI_DI (input) valid before SPI_CLK (output) rising edge Clock Polarity = 0 .5P + 3 ns 14 tsu(DIV-CLKH) Setup time, SPI_DI (in put) valid before SPI_CLK (output) falling edge Clock Polarity = 1 .
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DM355 through the I2C module.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13.1 I2C Electrical Data/Timing 5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33. Timing Requirements for I2C Timings (1) (see Figure 5-39) DM355 NO. MIN (2) (3) (4) (5) MAX MIN UNIT MAX tc(SCL) Cycle time, SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-34. Switching Characteristics for I2C Timings (1) (see Figure 5-40) DM355 NO. STANDARD MODE PARAMETER MIN FAST MODE MAX MIN UNIT MAX tc(SCL) Cycle time, SCL 10 2.5 μs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 μs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.
www.ti.com TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DM355 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio interface purposes. The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.14.1 ASP Electrical Data/Timing 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (1) (see Figure 5-41) DM355 NO. MIN PRODUCT PREVIEW ns CLKS ext 19.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP (1) (2) (see Figure 5-41) MAX 38.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-37. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 0 (see Figure 5-42) MASTER NO. MIN M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M31 th(CKXL-DRV) Hold time, DR valid after CLKX low MAX UNIT 11 ns 0 ns Table 5-38. ASP as SPI Switching Characteristics (1) (2) CLKSTP = 10b, CLKXP = 0 (see Figure 5-42) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-39. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 0 MASTER NO. MIN M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M40 th(CKXH-DRV) Hold time, DR valid after CLKX high MAX UNIT 11 ns 1 ns Table 5-40. ASP as SPI Switching Characteristics (1) (2) CLKSTP = 11b, CLKXP = 0 (see Figure 5-43) M42 (1) (2) (3) (4) (5) MASTER PARAMETER tc(CKX) MIN MAX 38.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-41. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 1 (see Figure 5-44) MASTER NO. MIN M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M50 th(CKXH-DRV) Hold time, DR valid after CLKX high MAX UNIT 11 ns 0 ns Table 5-42. ASP as SPI Switching Characteristics (1) (2) CLKSTP = 10b, CLKXP = 1 (see Figure 5-44) NO.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-43. ASP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 1 (see Figure 5-45) MASTER NO. MIN M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M59 th(CKXL-DRV) Hold time, DR valid after CLKX low MAX UNIT 11 ns 0 ns Table 5-44.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.15 Timer PRODUCT PREVIEW The contains four software-programmable timers. Timer 0, Timer 1, and Timer 3 (general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Pulse Width Modulator (PWM) The DM355 contains 4 separate Pulse Width Modulator (PWM) modules. The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some external components.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 VD(CCDC) 4 PWM0 INVALID VALID 4 PWM1 INVALID VALID 4 PWM2 INVALID VALID 4 PWM3 INVALID VALID PRODUCT PREVIEW Figure 5-48.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.17 Real Time Out (RTO) The Real Time Out (RTO) peripheral supports the following features: • Four separate outputs • Trigger on Timer3 event 5.17.1 RTO Electrical/Timing Data Table 5-47.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.18 IEEE 1149.1 JTAG The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.18.1 JTAG Test-Port Electrical Data/Timing Table 5-48.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-51) NO. DM355 PARAMETER MIN MAX UNIT 8 tc(RTCK) Cycle time, RTCK 20 9 tw(RTCKH) Pulse duration, RTCK high 10 10 tw(RTCKL) Pulse duration, RTCK low 10 11 tr(all JTAG outputs) Rise time, all JTAG outputs 1.3 ns 12 tf(all JTAG outputs) Fall time, all JTAG outputs 1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS463 device-specific data sheet to make it an SPRS463A revision. Scope: Updated DM355 Pin Descriptions table, etc. ADDS/CHANGES/DELETES Section 1.1, Features: • Video Processing Subsystem feature: – 14-Bit Parallel AFE (Analog Front End) Interface: Changed speed from 75 MHz to 67.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ADDS/CHANGES/DELETES Updated Section 5.9.1, Video Processing Front-End (VPFE) Updated Section 5.9.1.1, CCD Controller (CCDC) Updated Section 5.9.1.
TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 7 Mechanical Data The following table(s) show the thermal resistance characteristics for the PBGA – ZCE mechanical package. Note that micro-vias are not required. Contact your TI representative for routing recommendations. 7.1 Thermal Data for ZCE The following table shows the thermal resistance characteristics for the PBGA – ZCE mechanical package. NO.
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