TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs 1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 1.2 Description The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727, TMS320C6726, and TMS320C6722 devices. (1) Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes: • Two 32-bit counter/prescaler pairs • Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement) • Four compares with automatic update capability • Digital Watchdog (optional) for enhanced system robustness Clock Generation (PLL and OSC).
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the C672x device.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Contents 1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs ........................................................ 1 1.1 Features .............................................. 1 1.2 Description ............................................ 2 1.2.1 Device Compatibility 1.3 2 6 Device Characteristics ................................ 7 ............................... 8 2.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device, including the capacity of on-chip memory, the peripherals, the execution time, and the package type with pin count. Table 2-1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.2 Enhanced C67x+ CPU The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including an increase in core operating frequency from 225 MHz to 300 MHz (2) while operating at 1.2 V.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU INSTRUCTION FLOATING-POINT OPERATION (1) IMPROVES MPYSPDP SP x DP → DP Faster than MPYDP. Improves high Q biquads (bass management) and FFT. MPYSP2DP SP x SP → DP Faster than MPYDP. Improves Long FIRs (EQ).
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.4 Internal Program/Data ROM and RAM The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized as two 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page with eight 32-bit-wide banks.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.5 Program Cache The C672x DSP executes code directly from a large on-chip 32K-byte program cache.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.6 High-Performance Crossbar Switch The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The five bus masters arbitrate for five different target groups: T1 On-chip memories through the CPU Slave Port (CSP). T2 Memories on the external memory interface (EMIF). T3 Peripheral registers through the peripheral configuration bus. T4 McASP serializers through the dedicated McASP DMA bus. T5 dMAX registers.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a description of the bits. 31 16 Reserved 15 1 Reserved 0 CSPRST R/W, 1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024) Table 2-7.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.7 Memory Map Summary A high-level memory map of the C672x DSP appears in Table 2-8. The base address of each region is listed. Any address past the end address must not be read or written. The table also lists whether the regions are word-addressable or byte- and word-addressable. Table 2-8.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.8 Boot Modes The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits. 31 8 Reserved 7 PINCAP7 6 PINCAP6 5 PINCAP5 4 PINCAP4 3 PINCAP3 2 PINCAP2 1 PINCAP1 0 PINCAP0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000) Table 2-10.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits. 31 8 Reserved 7 PINCAP15 6 PINCAP14 5 PINCAP13 4 PINCAP12 3 PINCAP11 2 PINCAP10 1 PINCAP9 0 PINCAP8 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004) Table 2-11.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.9 Pin Assignments 2.9.1 Pin Maps Figure 2-8 and Figure 2-9 show the pin assignments on the 256-terminal GDH/ZDH package and the 144-pin RFP package, respectively.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.9.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 2-12. Terminal Functions (continued) SIGNAL NAME RFP GDH/ ZDH TYPE (1) PULL (2) GPIO (3) DESCRIPTION Clocks OSCIN 23 J2 I - N 1.2-V Oscillator Input OSCOUT 24 J3 O - N 1.2-V Oscillator Output OSCVDD 25 J4 PWR - N Oscillator 1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.10 Development 2.10.1 Development Support TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 2.10.2.2 Documentation Support Extensive documentation supports the TMS320™ DSP family of devices from product announcement through applications development.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SPRAA69 Using the TMS320C672x Bootloader Application Report. This document describes the design details about the TMS320C672x bootloader. This document also addresses parallel flash and HPI boot to the extent relevant. SPRU301 TMS320C6000 Code Composer Studio Tutorial. This tutorial introduces you to some of the key features of Code Composer Studio.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 3 Device Configurations 3.1 Device Configuration Registers The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1. These registers need to be programmed as part of the device initialization procedure. See Section 3.2. Table 3-1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are additional finer grain options when selecting which McASP controls the particular AXR serial data pins but these options are not listed here and can be made on a pin by pin basis. Table 3-3.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 3-5.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4 Peripheral and Electrical Specifications 4.1 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320C672x DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. 4.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.4 Electrical Characteristics Over Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX DVDD – 0.2 UNIT VOH High Level Output Voltage IO = –100 µA VOL Low Level Output Voltage IO = 100 µA 0.2 V V IOH High-Level Output Current VO = 0.8 DVDD –8 mA IOL Low-Level Output Current VO = 0.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF A. 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) The data sheet provides timing at the device pin.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.6 Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.7 Power Supplies For more information regarding TI’s power management products and suggested devices to power TI DSPs, visit www.ti.com/dsppower. 4.7.1 Power-Supply Sequencing This device does not require specific power-up sequencing between the DVDD and CVDD voltage rails; however, there are some considerations that the system designer should take into account: 1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.8 Reset A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be held low during power-up.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.9 Dual Data Movement Accelerator (dMAX) 4.9.1 dMAX Device-Specific Information The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSP.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller. Table 4-2. dMAX Peripheral Event Input Assignments EVENT NUMBER 42 EVENT ACRONYM EVENT DESCRIPTION 0 DETR[0] The CPU triggers the event by creating appropriate transition (edge) on bit0 in DETR register.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.9.2 dMAX Peripheral Registers Description(s) Table 4-3 is a list of the dMAX registers. Table 4-3.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.10 External Interrupts The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in combination with a McASP AMUTEIN signal to provide external interrupt capability.
www.ti.com TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11 External Memory Interface (EMIF) 4.11.1 EMIF Device-Specific Information The C672x DSP includes an external memory interface (EMIF) for optional SDRAM, NOR FLASH, NAND FLASH, or SRAM.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11.2 EMIF Peripheral Registers Description(s) Table 4-4 is a list of the EMIF registers. For more information about these registers, see the TMS320C672x DSP External Memory Interface (EMIF) User's Guide (literature number SPRU711). Table 4-4.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.11.3 EMIF Electrical Data/Timing Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13). Table 4-5. EMIF SDRAM Interface Timing Requirements NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-7. EMIF Asynchronous Interface Timing Requirements (1) (2) NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 1 BASIC SDRAM WRITE OPERATION 2 2 EM_CLK 3 4 EM_CS[0] 5 6 EM_WE_DQM[3:0] 7 8 7 8 EM_BA[1:0] EM_A[12:0] 9 EM_D[31:0] 11 12 EM_RAS 13 14 15 16 EM_CAS EM_WE Figure 4-7.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SETUP ASYNCHRONOUS READ WE STROBE MODE STROBE HOLD TA EM_CLK 21 21 22 22 23 23 EM_CS[2] EM_WE_DQM[3:0] EM_BA[1:0] ADDRESS 23 23 EM_A[12:0] ADDRESS 17 READ DATA 28 29 EM_D[31:0] 25 25 18 EM_OE EM_WE EM_RW Figure 4-9.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SETUP ASYNCHRONOUS WRITE WE STROBE MODE STROBE HOLD EM_CLK 21 21 EM_CS[2] 22 22 EM_WE_DQM[3:0] 22 22 BYTE WRITE STROBES 23 23 EM_BA[1:0] ADDRESS 23 23 EM_A[12:0] ADDRESS 24 27 EM_D[31:0] WRITE DATA EM_OE 32 32 EM_WE 26 26 EM_RW Figure 4-11.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 SETUP STROBE EXTENDED WAIT STATES STROBE HOLD 35 34 EM_CLK 30 31 ASSERTED EM_WAIT 33 DEASSERTED 33 Figure 4-13.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12 Universal Host-Port Interface (UHPI) [C6727 Only] 4.12.1 UHPI Device-Specific Information The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the host-port interface on the C671x DSP. The UHPI on the C672x DSP supports three major operating modes listed in Table 4-9. Table 4-9.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0' during the first half of access and '1' during the second half.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-16 illustrates the Multiplexed Host Address/Data Fullword Mode hookup between the C672x DSP and an external host microcontroller. In this mode, all 32 bits of UHPI_HD[31:0] are used and the host can access HPIA, HPID, and HPIC in a single bus cycle.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode, the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This mode allows the host to randomly access a 64K-byte page in the C672x address space.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.2 UHPI Peripheral Registers Description(s) Table 4-11 is a list of the UHPI registers. Table 4-11.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18, Figure 4-19, and Figure 4-20 show the bit layout of these registers. Table 4-12, Table 4-13, and Table 4-14 contain a description of the bits in these registers.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 31 8 Reserved 7 0 HPIAMSB R/W, 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C) Table 4-13. CFGHPIAMSB Register Bit Field Description (0x4000 000C) BIT NO. NAME RESET VALUE READ WRITE DESCRIPTION 31:8 Reserved N/A N/A Reads are indeterminate. Only 0s should be written to these bits.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.12.3 UHPI Electrical Data/Timing 4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing Table 4-15 and Table 4-16 assume testing over recommended operating conditions (see Figure 4-21 through Figure 4-24). Table 4-15. UHPI Read and Write Timing Requirements (1) (2) NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-16. UHPI Read and Write Switching Characteristics (1) (2) NO. PARAMETER Case 1. HPIC or HPIA read 1 td(DSL-HDV) Delay time, DS low to HD valid MIN MAX 1 15 Case 2. HPID read with no auto-increment 9 * 2H + 20 (3) Case 3. HPID read with auto-increment and read FIFO initially empty 9 * 2H + 20 (3) Case 4.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Read Write UHPI_HCS 37 37 14 13 13 UHPI_HDSx 15 15 16 16 UHPI_HRW UHPI_HA[15:0] Valid Valid 1 2 3 UHPI_HD[31:0] (Read) Read data 18 17 UHPI_HD[31:0] (Write) Write data 4 34 7 6 5 UHPI_HRDY A. Depending on the type of write or read operation (HPID or HPIC), transitions on UHPI_HRDY may or may not occur. Figure 4-21.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS 12 11 12 11 UHPI_HCNTL[1:0] 12 11 12 11 12 11 12 11 UHPI_HRW UHPI_HHWIL 10 9 10 9 37 13 37 13 14 HSTROBE(A) 1 3 2 1 3 2 UHPI_HD[15:0] 7 36 6 38 UHPI_HRDY A. See Figure 4-14. B.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL 13 16 16 15 15 37 37 14 13 HSTROBE(A) 3 3 1 2 1 2 UHPI_HD[15:0] 38 4 7 6 UHPI_HRDY A. See Figure 4-14. B.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 UHPI_HCS UHPI_HAS UHPI_HCNTL[1:0] UHPI_HRW UHPI_HHWIL 16 13 16 15 37 15 37 13 14 HSTROBE(A) 18 18 17 17 UHPI_HD[15:0] 4 35 38 34 5 34 5 UHPI_HRDY A. See Figure 4-14. B.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) The McASP serial port is specifically designed for multichannel audio applications.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The three McASPs on C672x have different configurations (see Table 4-17). NOTE: McASP2 is not available on the C6722. Table 4-17. McASP Configurations on C672x DSP McASP DIT CLOCK PINS DATA PINS COMMENTS McASP0 No AHCLKX0/AHCLKX2, ACLKX0, AFSX0 AHCLKR0/AHCLKR1, ACLKR0, AFSR0 Up to 16 AHCLKX0/AHCLKX2 share pin. AHCLKR0/AHCLKR1 share pin.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13.1 McASP Peripheral Registers Description(s) Table 4-18 is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU878). Table 4-18.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-18.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the bits. 31 8 Reserved 7 3 2 Reserved 0 AMUTEIN0 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-26. CFGMCASP0 Register Bit Layout (0x4000 0018) Table 4-19. CFGMCASP0 Register Bit Field Description (0x4000 0018) BIT NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-27 shows the bit layout of the CFGMCASP1 register and Table 4-20 contains a description of the bits. 31 8 Reserved 7 3 2 Reserved 0 AMUTEIN1 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-27. CFGMCASP1 Register Bit Layout (0x4000 001C) Table 4-20. CFGMCASP1 Register Bit Field Description (0x4000 001C) BIT NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-21 contains a description of the bits. 31 8 Reserved 7 3 2 Reserved 0 AMUTEIN2 R/W, 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-28. CFGMCASP2 Register Bit Layout (0x4000 0020) Table 4-21. CFGMCASP2 Register Bit Field Description (0x4000 0020) (1) BIT NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.13.2 McASP Electrical Data/Timing 4.13.2.1 Multichannel Audio Serial Port (McASP) Timing Table 4-22 and Table 4-23 assume testing over recommended operating conditions (see Figure 4-29 and Figure 4-30). Table 4-22. McASP Timing Requirements (1) (2) NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-23. McASP Switching Characteristics (1) NO. 9 PARAMETER tc(AHCKRX) Cycle time, AHCLKR internal, AHCLKR output 20 Cycle time, AHCLKR external, AHCLKR output 20 Cycle time, AHCLKX internal, AHCLKX output 20 Cycle time, AHCLKX external, AHCLKX output 10 11 12 tw(AHCKRX) tc(ACKRX) tw(ACKRX) MIN (AHR/2) – 2.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14 Serial Peripheral Interface Ports (SPI0, SPI1) 4.14.1 SPI Device-Specific Information Figure 4-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Optional − Slave Chip Select SPIx_SCS SPIx_SCS Optional Enable (Ready) SPIx_ENA SPIx_ENA SPIx_CLK SPIx_CLK SPIx_SOMI SPIx_SOMI SPIx_SIMO SPIx_SIMO MASTER SPI SLAVE SPI Figure 4-32.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.2 SPI Peripheral Registers Description(s) Table 4-24 is a list of the SPI registers. Table 4-24.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.14.3 SPI Electrical Data/Timing 4.14.3.1 Serial Peripheral Interface (SPI) Timing Table 4-25 through Table 4-32 assume testing over recommended operating conditions (see Figure 4-33 through Figure 4-36). Table 4-25. General Timing Requirements for SPIx Master Modes (1) NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-26. General Timing Requirements for SPIx Slave Modes (1) NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-27. Additional (1) SPI Master Timings, 4-Pin Enable Option (2) (3) NO. 17 td(ENA_SPC)M 18 (1) (2) (3) (4) (5) MIN td(SPC_ENA)M Delay from slave assertion of SPIx_ENA active to first SPIx_CLK from master. (4) Max delay for slave to deassert SPIx_ENA after final SPIx_CLK edge to ensure master does not begin the next transfer.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-29. Additional (1) SPI Master Timings, 5-Pin Option (2) (3) NO. 18 20 21 22 23 MIN td(SPC_ENA)M td(SPC_SCS)M td(SCSL_ENAL)M td(SCS_SPC)M td(ENA_SPC)M Max delay for slave to deassert SPIx_ENA after final SPIx_CLK edge to ensure master does not begin the next transfer.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-30. Additional (1) SPI Slave Timings, 4-Pin Enable Option (2) (3) NO. 24 (1) (2) (3) MIN td(SPC_ENAH)S Delay from final SPIx_CLK edge to slave deasserting SPIx_ENA. MAX UNIT Polarity = 0, Phase = 0, from SPIx_CLK falling P – 10 3P + 15 Polarity = 0, Phase = 1, from SPIx_CLK falling 0.5tc(SPC)M + P – 10 0.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-32. Additional (1) SPI Slave Timings, 5-Pin Option (2) (3) NO. 25 26 88 td(SCSL_SPC)S td(SPC_SCSH)S Required delay from SPIx_SCS asserted at slave to first SPIx_CLK edge at slave. Required delay from final SPIx_CLK edge before SPIx_SCS is deasserted. MAX P Polarity = 0, Phase = 0, from SPIx_CLK falling 0.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) 4.15.1 I2C Device-Specific Information Having two I2C modules on the C672x simplifies system architecture, since one module may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.2 I2C Peripheral Registers Description(s) Table 4-33 is a list of the I2C registers. Table 4-33.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.15.3 I2C Electrical Data/Timing 4.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 4-34 and Table 4-35 assume testing over recommended operating conditions (see Figure 4-38 and Figure 4-39). Table 4-34. I2C Input Timing Requirements NO.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-35. I2C Switching Characteristics (continued) NO. PARAMETER MIN Standard Mode 4.7 Fast Mode 1.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog 4.16.1 RTI/Digital Watchdog Device-Specific Information C672x includes an RTI timer module which is used to generate periodic interrupts. This module also includes an optional digital watchdog feature. Figure 4-40 contains a block diagram of the RTI module.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A followed by 0xA35C in two separate writes) must be continually written to the key register before the watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to provide an added measure of robustness against a software failure.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-36. RTI Registers (continued) BYTE ADDRESS REGISTER NAME DESCRIPTION 0x4200 0088 RTIINTFLAG Interrupt Flags. Interrupt pending bits. 0x4200 0090 RTIDWDCTRL Digital Watchdog Control. Enables the Digital Watchdog. 0x4200 0094 RTIDWDPRLD Digital Watchdog Preload. Sets the experation time of the Digital Watchdog. 0x4200 0098 RTIWDSTATUS Watchdog Status.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.17 External Clock Input From Oscillator or CLKIN Pin The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 4-42. • Figure 4-42 (a) illustrates the option that uses an on-chip 1.2-V oscillator with external crystal circuit.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.17.1 Clock Electrical Data/Timing Table 4-39 assumes testing over recommended operating conditions. Table 4-39. CLKIN Timing Requirements NO. MIN MAX UNIT 1 fosc Oscillator frequency range (OSCIN/OSCOUT) 12 25 MHz 2 tc(CLKIN) Cycle time, external clock driven on CLKIN 20 ns 3 tw(CLKINH) Pulse width, CLKIN high 0.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.18 Phase-Locked Loop (PLL) 4.18.1 PLL Device-Specific Information The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL. The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs four clocks that have programmable divider options.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 Table 4-40. Allowed PLL Operating Conditions PARAMETER DEFAULT VALUE ALLOWED SETTING OR RANGE MIN 1 PLLRST = 1 assertion time during initialization N/A 125 ns 2 Lock time before setting PLLEN = 1. After changing D0, PLLM, or input clock. N/A 187.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 4.18.2 PLL Registers Description(s) Table 4-41 is a list of the PLL registers. For more information about these registers, see the TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU879). Table 4-41.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 5 Application Example Figure 5-1 illustrates a high-level block diagram of the device and other devices to which it may typically connect. See Section 1.2 for an overview of each major block.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS268D device-specific data sheet to make it an SPRS268E revision. Scope: Corrected addresses of the XGBLCTL register in Table 4-18, McASP Registers Accessed Through Peripheral Configuration Bus.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7 Mechanical Data 7.1 Package Thermal Resistance Characteristics Table 7-1 and Table 7-2 provide the thermal characteristics for the recommended package types used on the TMS320C672x DSP. Table 7-1. Thermal Characteristics for GDH/ZDH Package NO. °C/W AIR FLOW (m/s) 25 0 Two-Signal, Two-Plane, 101.5 x 114.5 x 1.6 mm , 2-oz Cu.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7.2 Supplementary Information About the 144-Pin RFP PowerPAD™ Package 7.2.1 Standoff Height This section highlights a few important details about the 144-pin RFP PowerPAD™ package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) should be consulted before designing a PCB for this device.
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E – MAY 2005 – REVISED JANUARY 2007 7.2.2 PowerPAD™ PCB Footprint Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) should be consulted when creating a PCB footprint for this device. In general, for proper thermal performance, the thermal pad under the package body should be as large as possible.
PACKAGE OPTION ADDENDUM www.ti.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.