SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Low-Price/High-Performance Floating-Point D D D D D Digital Signal Processor (DSP): TMS320C6712D − Eight 32-Bit Instructions/Cycle − 150-MHz Clock Rate − 6.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GDP and ZDP BGA package (bottom view) . . . . . . . . . . . . . 5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device compatibility . . . . . . . . . . . . . . . .
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 REVISION HISTORY The TMS320C6712D device-specific documentation has been split from TMS320C6712, TMS320C6712C, TMS320C6712D Floating−Point Digital Signal Processors, literature number SPRS148L, into a separate Data Sheet, literature number SPRS293.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PAGE(S) NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 GDP and ZDP BGA package (bottom view) GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) Y W V U T R P N M L K J H G F E D C B A 3 1 2 5 4 7 6 9 8 POST OFFICE BOX 1443 11 13 15 17 19 10 12 14 16 18 20 • HOUSTON, TEXAS 77251−1443 5
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 description The TMS320C67x DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices†) are members of the floating-point DSP family in the TMS320C6000 DSP platform.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device characteristics Table 1 provides an overview of the DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000 DSP device part numbers and part numbering, see Figure 5. Table 1.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device compatibility The TMS320C6712 and C6211/C6711 devices are pin-compatible; thus, making new system designs easier and providing faster time to market.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 functional block and CPU (DSP core) diagram Digital Signal Processor SDRAM SBSRAM SRAM 16 External Memory Interface (EMIF) L1P Cache Direct Mapped 4K Bytes Total ROM/FLASH I/O Devices Timer 0 C67x CPU (DSP Core) Timer 1 Framing Chips: H.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description (continued) ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ src1 .L1† src2 dst long dst long src LD1 32 MSB ST1 long src long dst dst .S1† src1 Data Path A 8 8 32 32 8 8 Á Á Á Á src2 dst src1 † .
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 memory map summary Table 2 shows the memory map address ranges of the device. Internal memory is always located at address 0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the device begin at the address location 0x8000 0000. Table 2.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions Table 3 through Table 13 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 5.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 10.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 12. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE TIMER 0 TIMER 1 0194 0000 0198 0000 ACRONYM CTLx REGISTER NAME COMMENTS Timer x control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description CLKIN CLKOUT3 Reset and Interrupts CLKOUT2† Clock/PLL RESET NMI EXT_INT7‡ EXT_INT6‡ EXT_INT5‡ EXT_INT4‡ CLKMODE0 PLLHV BIG/LITTLE ENDIAN TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 LENDIAN EMIFBE§ RSV RSV IEEE Standard 1149.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) TOUT1 Timer 1 TOUT0 Timer 0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1† Receive Receive CLKR0 FSR0 DR0 CLKS1† Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) GPIO GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) CLKOUT2/GP[2] General-Purpose Input/Output (GPIO) Port † For
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS On the device, bootmode and certain device configurations/peripheral selections are determined at device reset. Other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 14. Device Configurations Pins at Device Reset (LENDIAN, EMIFBE, BOOTMODE[1:0], and CLKMODE0) CONFIGURATION PIN GDP/ZDP FUNCTIONAL DESCRIPTION EMIF Big Endian mode correctness (EMIFBE) EMIFBE C15 When Big Endian mode is selected (LENDIAN = 0), for proper device operation the EMIFBE pin must be externally pulled low.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description The device configuration register (DEVCFG) allows the user control of the EMIF input clock source. For more detailed information on the DEVCFG register control bits, see Table 15 and Table 16. Table 15.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, see the Device Configurations section of this data sheet.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions SIGNAL NAME PIN NO. GDP/ ZDP TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CLKIN A3 I IPU Clock Input The CLKOUT2 pin is multiplexed with the GP[2] pin. Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] (I/O/Z).
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† IPD/ IPU‡ DESCRIPTION JTAG EMULATION (CONTINUED) EMU1 EMU0 B9 D9 I/O/Z IPU Emulation [1:0] pins. • Select the device functional mode of operation EMU[1:0] Operation 00 Boundary Scan/Functional Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Functional Mode [default] (see the IEEE 1149.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† IPD/ IPU‡ DESCRIPTION RESETS AND INTERRUPTS RESET NMI A13 C13 EXT_INT7 E3 EXT_INT6 D2 EXT_INT5 C1 EXT_INT4 C2 −− Device reset. When using Boundary Scan mode on the device, drive the EMU[1:0] and RESET pins low. This pin does not have an IPU.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† IPD/ IPU IPU RSV A5 O RSV N2 O RSV N1 DESCRIPTION Reserved (leave unconnected, do not connect to power or ground) Reserved. For proper device operation, this pin must be externally pulled up with a 10-kΩ resistor. Reserved. For proper device operation, this pin must be externally pulled up with a 10-kΩ resistor.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† DESCRIPTION SUPPLY VOLTAGE PINS A17 B3 B8 B13 C10 D1 D16 D19 F3 H18 J2 M18 R1 DVDD R18 S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet) S 1.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) D11 D14 D15 F4 F17 K1 K4 K17 L4 L17 L20 CVDD R4 S 1.20-V supply voltage [See Note] (see the power-supply decoupling portion of this data sheet) R17 U6 U10 U11 U14 U15 V3 V18 W2 Note: This value is compatible with existing 1.26-V designs.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. GDP/ ZDP TYPE† DESCRIPTION GROUND PINS (CONTINUED) D17 E2 E4 E17 F19 G4 G17 H4 H17 J4 J9 J10 J11 J12 K2 K9 K10 K11 K12 VSS K20 L9 GND Ground pins|| The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as both electrical grounds and thermal relief (thermal dissipation).
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device support device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. (e.g., TMS320C6712DGDP150). Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = C 6712D GDP ( ) 150 Experimental device Prototype device Qualified device MIL-PRF-38535, QML High Rel (non-38535) DEVICE SPEED RANGE 150 MHz TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = −40°C to 105°C, extended temperature DEVICE FAMILY 32 or 320 = TMS320 DSP
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU CSR register description The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 6 and Table 17 identify the bit fields in the CPU CSR register.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU CSR register description (continued) Table 17. CPU CSR Register Bit Field Description BIT # NAME 31:24 CPU ID 23:16 REVISION ID DESCRIPTION CPU ID + REV ID. Read only. Identifies which CPU is used and defines the silicon revision of the CPU. CPU ID + REVISION ID (31:16) are combined for a value of: 0x0203 Control power-down modes. The values are always read as zero.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 cache configuration (CCFG) register description The device includes an enhancement to the cache configuration (CCFG) register. A “P” bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the L2 memory.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 interrupt sources and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 19. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 19.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA for this device also supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. On this device, the user, through the EDMA selector registers, can control the EDMA channels servicing peripheral devices.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA module and EDMA selector (continued) Table 23.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller The TMS320C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other peripherals).
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time value, see Table 25.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 27. PLL Clock Frequency Ranges†‡ GDP 150and ZDP 150 CLOCK SIGNAL UNIT MIN MAX PLLREF (PLLEN = 1) 12 100 MHz PLLOUT 140 600 MHz SYSCLK1 − Device Speed (DSP Core) MHz SYSCLK3 (EKSRC = 0) − 100 MHz † SYSCLK2 rate must be exactly half of SYSCLK1.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) PLLCSR Register (0x01B7 C100) 28 31 27 24 23 20 19 16 Reserved R−0 15 12 11 8 7 6 5 4 3 2 1 0 Reserved STABLE Reserved PLLRST Reserved PLLPWRDN PLLEN R−0 R−x R−0 RW−1 R/W−0 R/W−0b RW−0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 28. PLL Control/Status Register (PLLCSR) BIT # NAME 31:7 Reserved Reserved.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) PLLM Register (0x01B7 C110) 24 23 28 27 31 20 19 16 Reserved R−0 15 12 11 8 7 6 5 4 3 2 Reserved PLLM R−0 R/W−0 0111 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 29. PLL Multiplier Control Register (PLLM) BIT # NAME 31:5 Reserved 4:0 PLLM DESCRIPTION Reserved. Read-only, writes have no effect.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) 28 31 24 27 23 20 19 16 Reserved R−0 14 15 12 11 8 7 5 4 3 2 DxEN Reserved PLLDIVx R/W−1 R−0 R/W−x xxxx† 1 0 Legend: R = Read only, R/W = Read/Write; -n = value after reset † Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) OSCDIV1 Register (0x01B7 C124) 24 23 28 27 31 20 19 16 Reserved R−0 15 14 12 11 8 7 5 4 3 2 OD1EN Reserved OSCDIV1 R/W−1 R−0 R/W−0 0111 1 0 Legend: R = Read only, R/W = Read/Write; -n = value after reset The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through the PLL path. Table 31.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 general-purpose input/output (GPIO) To use the GP[7:4, 2] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 power-down mode logic Figure 11 shows the power-down mode logic. CLKOUT2 Internal Clock Tree Clock Distribution and Dividers PD1 PD2 PowerDown Logic Clock PLL IFR Internal Peripherals IER PWRD CSR CPU PD3 TMS320C6712D CLKIN RESET † External input clocks, with the exception of CLKOUT3 and CLKIN, are not gated by the power-down mode logic. Figure 11.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 31 16 15 14 13 12 11 10 Reserved Enable or Non-Enabled Interrupt Wake Enabled Interrupt Wake PD3 PD2 PD1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 9 8 0 Legend: R/W−x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 32.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 I/O Supply DVDD Schottky Diode C6000 DSP Core Supply CVDD VSS GND Figure 13. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 IEEE 1149.1 JTAG compatibility statement The DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected after TRST is asserted.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EMIF device speed The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839).
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EMIF big endian mode correctness The device Endian mode pin (LENDIAN) selects the endian mode of operation (little endian or big endian) for the device. Little endian is the default setting. When Big Endian mode is selected (LENDIAN = 0), the EMIF Big Endian mode correctness pin (EMIFBE) must to be pulled low. Figure 14 shows the mapping of 16-bit and 8-bit data for the device with EMIF endianness correction.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 2): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V Supply voltage range, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Input voltage ranges: . . . . . . . . . .
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 electrical characteristics over recommended ranges of supply voltage and operating case temperature† (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage II Input current TEST CONDITIONS All signals except CLKS1 and DR1 All signals except CLKS1 and DR1 DVDD = MIN, IOH = MAX MIN TYP 2.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics 42 Ω Data Sheet Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF Device Pin (see note) 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications Figure 18 and Figure 19 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet. t = 0.3 tc (max)† VOS (max) Minimum Risetime VIH (min) Waveform Valid Region Ground Figure 18.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) Table 34. Board-Level Timings Example (see Figure 20) NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN†‡§ (see Figure 21) −150 PLL MODE (PLLEN = 1) NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low BYPASS MODE (PLLEN = 0) UNIT MIN MAX MIN 6.7 83.3 6.7 ns 0.4C 0.4C ns 0.4C 0.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT3†‡ (see Figure 23) −150 NO. 1 2 3 4 PARAMETER MIN UNIT MAX tc(CKO3) tw(CKO3H) Cycle time, CLKOUT3 C3 − 0.9 C3 + 0.9 ns Pulse duration, CLKOUT3 high (C3/2) − 0.9 (C3/2) + 0.9 ns tw(CKO3L) tt(CKO3) Pulse duration, CLKOUT3 low (C3/2) − 0.9 (C3/2) + 0.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for ECLKOUT†‡§ (see Figure 25) −150 NO. 1 2 3 4 5 PARAMETER MIN MAX UNIT tc(EKO) tw(EKOH) Cycle time, ECLKOUT E − 0.9 E + 0.9 ns Pulse duration, ECLKOUT high EH − 0.9 EH + 0.9 ns tw(EKOL) tt(EKO) Pulse duration, ECLKOUT low EL − 0.9 EL + 0.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles†‡ (see Figure 26−Figure 27) −150 NO. 3 4 6 7 MIN tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high tsu(ARDY-EKOH) th(EKOH-ARDY) UNIT MAX 6.5 ns Hold time, EDx valid after ARE high 1 ns Setup time, ARDY valid before ECLKOUT high 3 ns Hold time, ARDY valid after ECLKOUT high 2.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 ECLKOUT 1 2 CE[3:0] 1 2 BE[1:0] BE 1 2 EA[21:2] Address 3 4 ED[15:0] 1 2 Read Data AOE/SDRAS/SSOE† 5 5 ARE/SDCAS/SSADS† AWE/SDWE/SSWE† 7 6 7 6 ARDY † AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 Not Ready ECLKOUT 8 9 CEx 8 9 BE[3:0] BE 8 9 EA[21:2] Address 11 9 ED[31:0] Write Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† 10 10 AWE/SDWE/SSWE† 7 6 7 6 ARDY † AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles† (see Figure 28) −150 NO. 6 7 MIN tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high 1.5 Hold time, read EDx valid after ECLKOUT high 2.5 MAX UNIT ns ns † The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) ECLKOUT 1 1 CE[3:0] BE[1:0] 2 BE1 3 BE2 BE3 4 BE4 5 EA[21:2] EA 6 ED[15:0] 7 Q1 Q2 Q3 Q4 8 8 ARE/SDCAS/SSADS† 9 9 AOE/SDRAS/SSOE† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 28.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles† (see Figure 30) -150 NO. 6 MIN tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high MAX 1.5 UNIT ns 7 Hold time, read EDx valid after ECLKOUT high 2.5 ns † The SDRAM interface takes advantage of the internal burst counter in the SDRAM.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUT 1 1 CE[3:0] 2 BE1 BE[1:0] EA[21:13] EA[11:2] 4 Bank 5 4 Column 5 4 3 BE2 BE3 BE4 5 EA12 6 D1 ED[15:0] 7 D2 D3 D4 AOE/SDRAS/SSOE† 8 8 ARE/SDCAS/SSADS† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 30.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) WRITE ECLKOUT 1 2 CE[3:0] 2 3 4 BE[1:0] BE1 4 BE2 BE3 BE4 D2 D3 D4 5 Bank EA[21:13] 5 4 Column EA[11:2] 4 5 EA12 9 ED[15:0] 10 9 D1 AOE/SDRAS/SSOE† 8 8 11 11 ARE/SDCAS/SSADS† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 31.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV ECLKOUT 1 1 CE[3:0] BE[1:0] 4 Bank Activate 5 EA[21:13] 4 Row Address 5 EA[11:2] 4 Row Address 5 EA12 ED[15:0] 12 12 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 32.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) DEAC ECLKOUT 1 1 CE[3:0] BE[1:0] 4 5 Bank EA[21:13] EA[11:2] 4 5 12 12 11 11 EA12 ED[15:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 34.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUT 1 1 4 MRS value 5 12 12 8 8 11 11 CE[3:0] BE[1:0] EA[21:2] ED[15:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 36.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 37) −150 NO. MIN 3 th(HOLDAL-HOLDL) † E = ECLKIN period in ns Hold time, HOLD low after HOLDA low MAX E UNIT ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 37) −150 NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 38) −150 NO. 1 PARAMETER td(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid ECLKOUT 1 1 BUSREQ Figure 38. BUSREQ Timing 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MIN MAX 1.5 7.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 RESET TIMING Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor. timing requirements for reset†‡ (see Figure 39) −150 NO.
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 RESET TIMING (CONTINUED) Phase 1 Phase 2 Phase 3 CLKIN ECLKIN 1 RESET 2 Internal Reset Internal SYSCLK1 Internal SYSCLK2 Internal SYSCLK3 3 4 5 6 7 8 ECLKOUT CLKOUT2 CLKOUT3 9 2 10 2 11 2 EMIF Z Group† EMIF Low Group† Z Group† Boot and Device Configuration Pins‡ 12 13 † EMIF Z group consists of: EA[21:2], ED[15:0], CE[3:0], BE[1:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and HOLDA EMIF l
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts† (see Figure 40) −150 NO. MIN 1 tw(ILOW) 2 tw(IHIGH) MAX UNIT Width of the NMI interrupt pulse low 2P ns Width of the EXT_INT interrupt pulse low 4P ns Width of the NMI interrupt pulse high 2P ns Width of the EXT_INT interrupt pulse high 4P ns † P = 1/CPU clock frequency in ns.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 41) −150 NO.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 41) −150 NO. PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input MAX 1.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 13 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) Figure 41.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 42) −150 NO. 1 2 MIN tsu(FRH-CKSH) th(CKSH-FRH) MAX UNIT Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 42.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 43) −150 NO.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 44) −150 NO.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 45) −150 MASTER NO. MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high SLAVE MAX MIN UNIT MAX 12 2 − 6P ns 4 5 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
SPRS293 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 8 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 46) −150 MASTER NO.
SPRS293 − OCTOBER 2005 CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 46.
SPRS293 − OCTOBER 2005 TIMER TIMING timing requirements for timer inputs† (see Figure 47) −150 NO. 1 MIN tw(TINPH) tw(TINPL) Pulse duration, TINP high 2 Pulse duration, TINP low † P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 10 ns. MAX UNIT 2P ns 2P ns switching characteristics over recommended operating conditions for timer outputs† (see Figure 47) −150 NO.
SPRS293 − OCTOBER 2005 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs†‡ (see Figure 48) −150 NO. 1 MIN tw(GPIH) tw(GPIL) Pulse duration, GPIx high MAX 4P UNIT ns 2 Pulse duration, GPIx low 4P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. ‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event.
SPRS293 − OCTOBER 2005 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49) −150 NO. 1 MIN MAX UNIT Cycle time, TCK 35 ns 3 tc(TCK) tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 7 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 49) −150 NO.
SPRS293 − OCTOBER 2005 MECHANICAL DATA package thermal resistance characteristics The following tables show the thermal resistance characteristics for the GDP and ZDP mechanical packages. thermal resistance characteristics (S-PBGA package) for GDP NO °C/W Air Flow (m/s)† Two Signals, Two Planes (4-Layer Board) 1 RΘJC Junction-to-case 9.7 N/A 2 PsiJT Junction-to-package top 1.5 0.
PACKAGE OPTION ADDENDUM www.ti.com 10-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMS320C6712DGDP150 ACTIVE BGA GDP 272 40 TBD SNPB Level-3-220C-168HR TMS320C6712DZDP150 ACTIVE BGA ZDP 272 40 Pb-Free (RoHS) SNAGCU Level-3-260C-168HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
MECHANICAL DATA MPBG274 – MAY 2002 GDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,20 SQ 23,80 24,13 TYP 1,27 0,635 Y W V U T R P N M L K J H G F E D C B A A1 Corner 1,27 0,635 3 1 2 1,22 1,12 5 4 7 6 9 8 11 13 15 17 19 10 12 14 16 18 20 Bottom View 2,57 MAX Seating Plane 0,65 0,57 0,90 0,60 0,10 0,70 0,50 0,15 4204396/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
MECHANICAL DATA MPBG276 – MAY 2002 ZDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,20 SQ 23,80 24,13 TYP 1,27 0,635 Y W V U T R P N M L K J H G F E D C B A A1 Corner 1,27 0,635 3 1 2 1,22 1,12 5 4 7 6 9 8 11 13 15 17 19 10 12 14 16 18 20 Bottom View 2,57 MAX Seating Plane 0,65 0,57 0,90 0,60 0,10 0,70 0,50 0,15 4204398/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 D.
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