TMS320C6472/TMS320TCI648x DSP 64-Bit Timer User's Guide Literature Number: SPRU818B December 2005 – Revised September 2010
SPRU818B – December 2005 – Revised September 2010 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Preface ....................................................................................................................................... 5 1 Introduction to the Timer ...................................................................................................... 6 2 Timer Modes ....................................................................................................................... 8 ................................................................................................
www.ti.com List of Figures 1 Timer Block Diagram ....................................................................................................... 7 2 Generation of the Internal Timer Clock 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 .................................................................................. 64-Bit Timer Mode Block Diagram ........................................................................................ Dual 32-Bit Timers Chained Mode Block Diagram .............
Preface SPRU818B – December 2005 – Revised September 2010 Read This First About This Manual This document provides an overview of the 64-bit timer in the TMS320TCI648x/TMS320C6472 DSP. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other.
User's Guide SPRU818B – December 2005 – Revised September 2010 C6472/TCI648x 64-Bit Timer 1 Introduction to the Timer The timer can be configured in one of three modes using the timer mode (TIMMODE) bits in the timer global control register (TGCR): a 64-bit general-purpose (GP) timer, dual 32-bit timers (TIMLO and TIMHI), or a watchdog timer. When configured as dual 32-bit timers, each half can operate dependently (chain mode) or independently (unchained mode) of each other.
Introduction to the Timer www.ti.com Figure 1.
Timer Modes www.ti.com 2 Timer Modes 2.1 64-Bit Timer Mode The timer can be configured as a 64-bit general-purpose (GP) timer, using the TIMMODE bits in TGCR register. At reset, the timer is in 64-bit GP timer mode. In this mode, the timer operates as a 64-bit up-counter, as shown in Figure 3. The counter registers (CNTLO, CNTHI) and the period registers (PRDLO, PRDHI) form a 64-bit timer counter register and a 64-bit timer period register, respectively. When the timer is enabled (see Section 3.
Timer Modes www.ti.com 2.2.1 Chained Mode In the chained mode, shown in Figure 4, one 32-bit timer (TIMHI) is used as a 32-bit prescaler to a second timer (TIMLO). The 32-bit prescaler (TIMHI) uses the counter register (CNTHI) and the period register (PRDHI) to form a 32-bit prescale counter register and a 32-bit prescale period register, respectively. When the timer is enabled, the prescale counter starts incrementing by 1 at every timer input clock cycle.
Timer Modes www.ti.com Figure 5. Dual 32-Bit Timers Chained Mode Example 32-bit prescaler settings: count = CNTHI = 200; period = PRDHI = 202 32-bit timer settings: count = CNTLO = 3; period = PRDLO= 4 Prescale counter (CNTHI) 200 201 202 0 1 2 Prescale counter reset Timer counter incremented Timer counter (CNTLO) 2.2.2 3 4 Unchained Mode In the unchained mode, shown in Figure 6, the timer can operate as two independent 32-bit timers.
Timer Modes www.ti.com 2.2.2.1 32-Bit Timer With a 4-Bit Prescaler (TIMHI) In the unchained mode, the 4-bit prescaler must be clocked by the internal clock; an external clock source cannot be used for TIMHI (except for C6472/TCI6486 devices). The 4-bit prescaler uses the timer divide-down ratio bits (TDDRHI) and the prescale counter bits (PSCHI) in TCR to form a 4-bit prescale counter register and a 4-bit prescale period register, respectively.
Timer Modes 2.3 www.ti.com Counter and Period Registers Used in GP Timer Modes Table 1 summarizes the counter registers (CNTLO and CNTHI) and period registers (PRDLO and PRDHI) used in each GP timer mode. Table 1.
Timer Operation www.ti.com 3 Timer Operation The following sections describe the overall timer operation. For specific details on the watchdog timer operation, see Section 4. 3.1 Timer Mode Selection The timer can be configured as a 64-bit general-purpose timer or dual 32-bit timers (chained or unchained), or a watchdog timer using the timer mode (TIMMODE) bits in timer global control register (TGCR) (see Table 2). At reset, the timer is configured as a 64-bit GP timer as default.
Timer Operation 3.3 www.ti.com Timer Clock Source Selection As shown in Table 4 and Figure 8, the timer clock source for TIMLO is selected using the clock source (CLKSRC) bit and timer input enable (TIEN_LO) bit in timer control register (TCR). The input clock source for TIMHI is always the internal clock(except C6472/TCI6486 devices). For C6472/TCI6486 devices, bit 24 and bit 25 are used to select the clock source to be internal or external for TIMHI.
Timer Operation www.ti.com 3.5 Timer Counting The timer counter runs at the timer clock rate specified by the clock source bit (CLKSRC) in the timer control register (TCR). Counting is enabled by setting the enabling mode (ENAMODE) bits in TCR to 01b or 10b. When enabled, the timer counter starts incrementing until the counter reaches a value equal to the value in the timer period register.
Timer Operation 3.8 www.ti.com Timer Emulation Modes The timer has an emulation management and clock speed register (EMUMGT_CLKSPD). As shown in Table 5, the FREE and SOFT bits of EMUMGT_CLKSPD determine how the timer responds to an emulation suspend event. An emulation suspend event corresponds to any type of emulator access to the DSP, such as a hardware or software breakpoint, a probe point, or a printf instruction. Table 5.
Timer Operation www.ti.com 3.9.3 Timer Count = 0, Timer Period = 0, Prescale Count = 0, and Prescale Period = 0 Consider a timer that has a prescaler: • The combination timer in the 32-bit dual timers chained mode. • TIMHI in the 32-bit dual timer configuration (unchained mode). In the special case when timer count = 0, timer period = 0, prescale count = 0, and prescale period = 0, the timer operates in the same manner as a non-prescaled timer with timer count = 0 and timer period = 0 (see Section 3.9.
Timer Operation www.ti.com 3.10 Initializing the Timer After a hardware reset, the enabling mode (ENAMODE) bits in the timer control register (TCR) are cleared to 0 and the timer is disabled. The timer counter and period registers are cleared to 0. The timer can be configured to the desired mode by programming the control registers, TCR and (in the case of the watchdog timer mode) WDTCR. Figure 10 shows a typical timer initialization: 1.
Watchdog Timer Mode www.ti.com 4 Watchdog Timer Mode The timer can also be configured as a 64-bit watchdog timer. As a watchdog timer, it can be used to prevent system lockup when the software becomes trapped in loops with no controlled exit. After a hardware reset, the timer is configured as a 64-bit GP timer and the watchdog mode is disabled.
Watchdog Timer Mode www.ti.com Figure 11.
Watchdog Timer Mode www.ti.com Figure 12.
Watchdog Timer Mode www.ti.com The PRDHI, PRDLO, TCR, and WDTCR registers must be configured before the watchdog timer enters the active state. The WDEN bit must be set to 1 before writing DA7Eh to the WDKEY bits in the pre-active state. Every time the watchdog timer is serviced by the correct WDKEY sequence, the watchdog timer counter is automatically reset. NOTE: Before the watchdog timer enters the active state, the timer output signal is never asserted.
Timer Registers www.ti.com 5 Timer Registers The timer contains a set of registers as indicated in Table 8. All timer register bits are read-write unless otherwise specified. For specific address locations, see the device-specific data manual. Table 8. Timer Registers Offset 0004 Acronym Name EMUMGT_CLKSPD Emulation management and clock speed register See Section 5.1 0010 CNTLO Counter register low Section 5.2 0014 CNTHI Counter register high Section 5.
Timer Registers 5.1 www.ti.com Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) The EMUMGT_CLKSPD register contains the FREE and SOFT bits that determine how the timer responds to an emulation suspend event (see Figure 13 and Table 9). An emulation suspend event corresponds to any type of emulator access to the DSP, such as a hardware or software breakpoint, a probepoint, or a printf instruction. For additional emulation information, see Section 3.8.
Timer Registers www.ti.com 5.2 Timer Counter Registers (CNTHI and CNTLO) The timer counter registers (CNTLO and CNTHI) are 32-bit wide registers that can be used in conjunction to form a 64-bit counter, or separately as 32-bit counters. The use of these registers depends on the configuration of the timer. In the 64-bit general-purpose timer mode and watchdog mode, the two registers work as a single 64-bit counter (see Figure 14). The 64-bit counter increments when the timer is enabled to count.
Timer Registers 5.3 www.ti.com Timer Period Registers (PRDHI and PRDLO) The timer period registers (PRDLO and PRDHI) are 32-bit wide registers which can be used in conjunction to form a single 64-bit period register (Figure 16) or separately as 32-bit period registers. These two registers have the field shown in Figure 17 and described in Table 11 and are accessed via a separate address.
Timer Registers www.ti.com 5.4 Timer Control Register (TCR) The timer control register (TCR) is shown in Figure 18 and described in Table 12. The lower 16 bits of TCR determine the operating mode and monitor the status of TIMLO, as well as control the function of TINPL and TOUTL. The upper 16 bits determine the operating mode and monitor the status of TIMHI. The upper 16 bits of TCR are used only when the timer is configured in dual 32-bit timers unchained mode (TIMMODE = 01b in TGCR). Figure 18.
Timer Registers www.ti.com Table 12. Timer Control Register (TCR) Field Descriptions (continued) Bit Field 19 CP_HI Value Description Clock/pulse mode bit for TIMHI. In the watchdog timer mode (TIMMODE = 10b), the pulse mode is selected automatically and the CP_HI bit is a don’t care. 0 Pulse mode. When the timer counter reaches the timer period, the timer output appears as a pulse with the width defined by the PWID_HI bits and the polarity defined by the INVOUTP_HI bits. 1 Clock mode.
Timer Registers www.ti.com Table 12. Timer Control Register (TCR) Field Descriptions (continued) Bit 0 Field Value TSTAT_LO Description Timer status bit. This is a read-only bit that shows the value of the timer output. TSTAT_LO drives the timer pin (TOUTL) when the pin is used as a timer output pin and may be inverted by setting INVOUTP_LO = 1. 0 Timer output is low. 1 Timer output is high.
Timer Registers 5.5 www.ti.com Timer Global Control Register (TGCR) The timer global control register (TGCR) is shown in Figure 19 and described in Table 13. This register contains a field for selecting the operating mode of the timer (TIMMODE), timer reset bits (TIMHIRS and TIMLORS), and counters for TIMHI in the dual 32-bit timers unchained mode (TDDRHI and PSCHI). Figure 19.
Timer Registers www.ti.com 5.6 Watchdog Timer Control Register (WDTCR) The watchdog timer control register (WDTCR) is shown in Figure 20 and described in Table 14. This register determines the state of the watchdog timer and monitors the watchdog timer status. Figure 20. Watchdog Timer Control Register (WDTCR) 31 16 WDKEY R/W-0 15 14 WDFLAG WDEN 13 WDKEY 12 11 Reserved 0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 14.
www.ti.com Appendix A Revision History This revision history highlights the technical changes made to the document in this revision. Table 15. TCI648x/C6472 Timer Revision History See Additions/Modifications/Deletions Section 1 Modified third paragraph and fifth paragraph Figure 1 Modified Timer Block Diagram Section 2.2.2.1 Modified first paragraph Section 3.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
