TMS320C645x DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) User's Guide Literature Number: SPRU975B August 2006
SPRU975B – August 2006 Submit Documentation Feedback
Contents Preface.............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 2 3 4 Purpose of the Peripheral ..................................................................................... 11 .........................................................................................................
.................................................... 80 EMAC Port Registers ................................................................................................. 81 5.1 Introduction ...................................................................................................... 81 5.2 Transmit Identification and Version Register (TXIDVER) ................................................. 85 5.3 Transmit Control Register (TXCONTROL) ..........................................................
.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) ........................................... 135 5.50 Network Statistics Registers ................................................................................. 136 Appendix A Glossary ...................................................................................................... 145 Appendix B Revision History .............
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6 EMAC and MDIO Block Diagram ........................................................................................ 12 Ethernet Configuration with MII Interface ............................................................................... 16 Ethernet Configuration with RMII Interface ..........................................................
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) ..................................... Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ............................................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 8 Interface Selection Pins ................................................................................................... 16 EMAC and MDIO Signals for MII Interface ............................................................................. 17 EMAC and MDIO Signals for RMII Interface ..................................................................
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 A-1 B-1 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions.............................
Preface SPRU975B – August 2006 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
User's Guide SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x (C645x) devices.
www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts.
www.ti.com Introduction 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC has also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E). In difference from this standard, the EMAC peripheral integrated with the C645x devices does not use the transmit coding error signal MTXER.
www.ti.com EMAC Functional Architecture 2 EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown below: • 2.5 Mhz at 10 Mbps • 25 Mhz at 100 Mbps • 125 MHz at 1000 Mbps The C645x device uses two PLL controllers to generate all of the clocks that the DSP needs.
www.ti.com EMAC Functional Architecture For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to GMTCLK. 2.1.4 RGMII Clocking When the RGMII interface is selected by setting MACSEL to 11b, you must configure the internal clock (SYSCLK1) to a 125 MHz frequency by setting the divider for the secondary PLL controller to /5.
www.ti.com EMAC Functional Architecture 2.3 System Level Connections The C645x device supports four different interfaces to a physical layer device. You can only transfer data on one interface at a given time. Each of these interfaces is selected in hardware via the configuration pins (MACSEL[1:0]). Table 1 shows the possible settings for these configuration pins. Table 1. Interface Selection Pins 2.3.
www.ti.com EMAC Functional Architecture Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC inversion is used to negate the validity of the transmitted frame. Table 2. EMAC and MDIO Signals for MII Interface Signal Name I/O MTCLK I Transmit clock (MTCLK).
www.ti.com EMAC Functional Architecture 2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection. This interface is only available in 10 Mbps and 100 Mbps modes. The RMII interface is only supported in full-duplex mode for the C645x family of devices. Figure 3.
www.ti.com EMAC Functional Architecture The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. Table 3 summarizes the individual EMAC and MDIO signals for the RMII interface. The RMII interface does not include an MCOL signal.
www.ti.com EMAC Functional Architecture 2.3.3 Gigabit Media Independent Interface (GMII) Connections Figure 4 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. Figure 4. Ethernet Configuration with GMII Interface MTCLK GMTCLK 2.
www.ti.com EMAC Functional Architecture Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface. Table 4. EMAC and MDIO Signals for GMII Interface Signal Name I/O MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clock when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.
www.ti.com EMAC Functional Architecture 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections Figure 5 shows a device with integrated EMAC and MDIO interfaced via a RGMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. Figure 5. Ethernet Configuration with RGMII Interface TXC TXD[3−0] 2.
www.ti.com EMAC Functional Architecture Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface. Table 5. EMAC and MDIO Signals for RGMII Interface Signal Name I/O TXC O Transmit clock (TXC). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The TXD and TXCTL signals are tied to this clock. The clock is driven by the EMAC and is 2.5 MHz at 10 Mbps operation, 25 MHz at 100 Mbps operation, and 125 MHz at 1000 Mbps operation.
www.ti.com EMAC Functional Architecture 2.4 Ethernet Protocol Overview Ethernet provides an unreliable, connectionless service to a networking application. A brief overview of the ethernet protocol follows. For more information on the carrier sense multiple access with collision detection (CSMA/CD) access method (ethernet’s multiple access protocol), see the IEEE 802.3 standard document. 2.4.1 Ethernet Frame Format All the ethernet technologies use the same frame structure.
www.ti.com EMAC Functional Architecture 2.4.2 Multiple Access Protocol Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
www.ti.com EMAC Functional Architecture 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor format is shown in Figure 7 and described in Table 7. Figure 7.
www.ti.com EMAC Functional Architecture For example, consider three packets to be transmitted, Packet A is a single fragment (60 bytes), Packet B is fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes). Figure 8 shows the linked list of descriptors to describe these three packets. Figure 8.
www.ti.com EMAC Functional Architecture 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains (Section 2.5.1). The lists controlled by the EMAC are maintained by the application software via the head descriptor pointer (HDP) registers. Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
www.ti.com EMAC Functional Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains (Section 2.5.1), using the linked list queue mechanism (Section 2.5.2). The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The interrupts are controlled by the application by using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
www.ti.com EMAC Functional Architecture 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor (Figure 9) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 9.
www.ti.com EMAC Functional Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. The pointer is not altered by the EMAC.
www.ti.com EMAC Functional Architecture 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.5.4.
www.ti.com EMAC Functional Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 10) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure. Figure 10.
www.ti.com EMAC Functional Architecture 2.5.5.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors. If the value of the pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active receive list. This pointer is not altered by the EMAC.
www.ti.com EMAC Functional Architecture 2.5.5.6 Start of Packet (SOP) Flag When set, this flag indicates that the descriptor points to the starting packet buffer of a new packet. For a single fragment packet, both the SOP and end of packet (EOP) flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet has the EOP flag set. The software application initially clears this flag before adding the descriptor to the receive queue. The EMAC sets this bit on SOP descriptors. 2.
www.ti.com EMAC Functional Architecture 2.5.5.14 Fragment Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is only a packet fragment and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE register. 2.5.5.15 Undersized Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is undersized and was not discarded because the RXCSFEN bit was set in the RXMBPENABLE register. 2.5.5.
www.ti.com EMAC Functional Architecture 2.6 EMAC Control Module The EMAC control module (Figure 11) interfaces the EMAC and MDIO modules to the rest of the system, and provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to avoid contention to device memory spaces. Other functions include the bus arbiter, and interrupt logic control. Figure 11.
www.ti.com EMAC Functional Architecture 2.6.3 Interrupt Control The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to control the interrupt signal to the CPU. First, the INTEN bit in the EWCTL register globally enables and disables the interrupt signal to the CPU.
www.ti.com EMAC Functional Architecture Figure 12. MDIO Module Block Diagram Peripheral clock EMAC control module MDIO clock generator USERINT LINKINT PHY monitoring Configuration bus 2.7.1.1 MDIO interface MDCLK MDIO PHY polling Control registers and logic MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock (CPUclk/6) in the EMAC control module. The MDIO clock is specified to run up to 2.
www.ti.com EMAC Functional Architecture 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
www.ti.com EMAC Functional Architecture 2.7.2.2 Writing Data to a PHY Register The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in the USERACCESSn register is cleared. 2. Write to the GO, WRITE, REGADR, PHYADR, and DATA bits in USERACCESSn corresponding to the desired PHY and PHY register. 3. The write operation to the PHY is scheduled and completed by the MDIO module.
www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.7.2.3. As the ALIVE register initially selects a PHY, it is assumed that the PHY is acknowledging read operations.
www.ti.com EMAC Functional Architecture 2.8 EMAC Module Section 2.8 discusses the architecture and basic functions of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 13) interfaces to PHY components through one of the four Media Independent Interfaces(MII, RMII, GMII, or RGMII), and interfaces to the system core through the EMAC control module.
www.ti.com EMAC Functional Architecture 2.8.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and places them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 2.8.1.4 Receive Address This sub-module performs address matching and address filtering based on the incoming packet’s destination address.
www.ti.com EMAC Functional Architecture 2.8.1.12 Clock and Reset Logic The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral. 2.8.2 EMAC Module Operational Overview After reset, initialization, and configuration of the EMAC, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block.
www.ti.com EMAC Functional Architecture 2.9 Media Independent Interfaces The EMAC supports four physical interfaces to external devices: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII). The physical interface used depends on the MACSEL pins. The basic operation of all four interfaces is the same, with some minor differences.
www.ti.com EMAC Functional Architecture 2.9.1.4 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the twelve byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3 in hexadecimal.
www.ti.com EMAC Functional Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the first 64 bytes have been transmitted), the collision is ignored.
www.ti.com EMAC Functional Architecture 2.9.2.6 Transmit Flow Control When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MACCONTROL register are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
www.ti.com EMAC Functional Architecture 2.10 Packet Receive Operation 2.10.
www.ti.com EMAC Functional Architecture 2.10.3 Receive Channel Addressing The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM.
www.ti.com EMAC Functional Architecture 2.10.5 Host Free Buffer Tracking The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous) if receive QOS or receive flow control is used. Disabled channel free buffer values are don’t cares. During initialization, the host should write the number of free buffers for each enabled channel to the appropriate RXnFREEBUFFER register.
www.ti.com EMAC Functional Architecture 2.10.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are transferred to the address match channel when RXCAFEN and RXCEFEN bits are set.
www.ti.com EMAC Functional Architecture Table 8. Receive Frame Treatment Summary (continued) RXMBPENABLE Bits ADDRESS MATCH RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame treatment 1 X 1 0 1 Proper/oversize/jabber/fragment/undersized/cod e/align/CRC data frames transferred to address match channel. No control frames are transferred. 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred.
www.ti.com EMAC Functional Architecture 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round robin as selected by the TXPTYPE bit in the MACCONTROL register. If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round robin priority proceeds from channel 0 to channel 7. 2.11.
www.ti.com EMAC Functional Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register in the C645x devices. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module. 2.
www.ti.com EMAC Functional Architecture 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero. The interface to be used (MII, RMII, GMII, or RGMII) is automatically selected at power-on reset, based on the state of the MACSEL configuration pins.
www.ti.com EMAC Functional Architecture Example 4.
www.ti.com EMAC Functional Architecture 2.15.4 EMAC Module Initialization The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit and receive descriptor queues. The EMAC module configuration must also be kept current based on the PHY negotiation results returned from the MDIO module. Programming this module is the most time-consuming aspect of developing an application or device driver for Ethernet.
www.ti.com EMAC Functional Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC/MDIO generates 18 interrupt events, as follows: • TXPENDn: Transmit packet completion interrupt for transmit channels 7 through 0 • RXPENDn: Receive packet completion interrupt for receive channels 7 through 0 • STATPEND: Statistics interrupt • HOSTPEND: Host error interrupt 2.16.1.
www.ti.com EMAC Functional Architecture 2.16.1.2 Receive Packet Completion Interrupts The receive DMA engine has eight channels, and each channel has a corresponding interrupt (RXPENDn). The receive interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight receive channel interrupts may be individually enabled by setting the appropriate bit in the RXINTMASKSET register.
www.ti.com EMAC Functional Architecture 2.16.1.4 Host Error Interrupt The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling of buffer descriptors detected during transmit or receive DMA transactions. The failure of the software application to supply properly formatted buffer descriptors results in this error. The error bit can only be cleared by resetting the EMAC module in hardware.
www.ti.com EMAC Functional Architecture 2.16.3 Proper Interrupt Processing All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant. However, the CPU core requires edge-triggered interrupts. To properly convert the level-driven interrupt signal to an edge-triggered signal, the application software must use the interrupt control logic of the EMAC control module. Section 2.6.3 discusses interrupt control in the EMAC control module.
www.ti.com EMAC Control Module Registers 3 EMAC Control Module Registers 3.1 Introduction Table 11 lists the memory-mapped registers for the EMAC Control Module. See the device-specific data manual for the memory address of these registers. Table 11. EMAC Control Module Registers Offset 3.2 Acronym Register Description 4h EWCTL EMAC Control Module Interrupt Control Register Section 3.2 Section 8h EWINTTCNT EMAC Control Module Interrupt Timer Count Register Section 3.
www.ti.com EMAC Control Module Registers 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an internal counter every time interrupts are enabled using EWCTL. A second interrupt cannot be generated until this count reaches 0.
www.ti.com MDIO Registers 4 MDIO Registers 4.1 Introduction Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers. Table 14. Management Data Input/Output (MDIO) Registers 66 Offset Acronym Register Description Section 0h VERSION MDIO Version Register Section 4.2 4h CONTROL MDIO Control Register Section 4.3 8h ALIVE PHY Alive Status register Section 4.
www.ti.com MDIO Registers 4.2 MDIO Version Register (VERSION) The MDIO version register (VERSION) is shown in Figure 16 and described in Table 15. Figure 16. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 15.
www.ti.com MDIO Registers 4.3 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16. Figure 17. MDIO Control Register (CONTROL) 31 30 29 20 19 18 IDLE ENABLE Reserved 28 HIGHEST_USER_CHANNEL 24 23 Reserved 21 PREAMBLE FAULT FAULT ENB Reserved 17 R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W-0 R-0 15 16 0 CLKDIV R/W-255 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16.
www.ti.com MDIO Registers 4.4 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 18 and described in Table 17. Figure 18. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 17.
www.ti.com MDIO Registers 4.5 PHY Link Status Register (LINK) The PHY link status register (LINK) is shown in Figure 19 and described in Table 18. Figure 19. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; -n = value after reset Table 18. PHY Link Status Register (LINK) Field Descriptions 70 Bit Field 31-0 LINK Value Description MDIO Link state bits. This register is updated after a read of the Generic Status Register of a PHY.
www.ti.com MDIO Registers 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 20 and described in Table 19. Figure 20. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 19.
www.ti.com MDIO Registers 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 21 and described in Table 20. Figure 21. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINT MASKED R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 20.
www.ti.com MDIO Registers 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 22 and described in Table 21. Figure 22. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTRAW R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 21.
www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (Masked) register (USERINTMASKED) is shown in Figure 23 and described in Table 22. Figure 23. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERINT MASKED R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 22.
www.ti.com MDIO Registers 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 24 and described in Table 23. Figure 24. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved USERINT MASKSET R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 23.
www.ti.com MDIO Registers 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 25 and described in Table 24. Figure 25. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASK CLEAR R-0 R/WC-0 LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 24.
www.ti.com MDIO Registers 4.12 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 26 and described in Table 25. Figure 26. MDIO User Access Register 0 (USERACCESS0) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 25.
www.ti.com MDIO Registers 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27 and described in Table 26. Figure 27. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Reserved 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 26.
www.ti.com MDIO Registers 4.14 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 28 and described in Table 27. Figure 28. MDIO User Access Register 1 (USERACCESS1) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 27.
www.ti.com MDIO Registers 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29 and described in Table 28. Figure 29. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Reserved 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28.
www.ti.com EMAC Port Registers 5 EMAC Port Registers 5.1 Introduction Table 29 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). See the device-specific data manual for the memory address of these registers. Table 29. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h TXIDVER Transmit Identification and Version Register Section 5.2 4h TXCONTROL Transmit Control Register Section 5.
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) 82 Offset Acronym Register Description 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 Section 160h MACCONTROL MAC Control Register Section 5.29 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 658h TX6CP Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register Section 5.48 Section 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register Section 5.48 660h RX0CP Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register Section 5.
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset 84 Acronym Register Description 270h FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register Section 5.50.29 274h FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register Section 5.50.30 278h FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register Section 5.50.
www.ti.com EMAC Port Registers 5.2 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 30 and described in Table 30. Figure 30. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-12 15 8 7 0 TXMAJORVER TXMINORVER R-10 R-7 LEGEND: R = Read only; -n = value after reset Table 30.
www.ti.com EMAC Port Registers 5.3 Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure 31 and described in Table 31. Figure 31. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31.
www.ti.com EMAC Port Registers 5.4 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 32 and described in Table 32. Figure 32. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32.
www.ti.com EMAC Port Registers 5.5 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 33 and described in Table 33. Figure 33. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-12 15 8 7 0 RXMAJORVER RXMINORVER R-10 R-7 LEGEND: R = Read only; -n = value after reset Table 33.
www.ti.com EMAC Port Registers 5.6 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 34 and described in Table 34. Figure 34. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34.
www.ti.com EMAC Port Registers 5.7 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 35 and described in Table 35. Figure 35. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35.
www.ti.com EMAC Port Registers 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 36 and described in Table 36. Figure 36.
www.ti.com EMAC Port Registers 5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (Masked) register (TXINTSTATMASKED) is shown in Figure 37 and described in Table 37. Figure 37.
www.ti.com EMAC Port Registers 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 38 and described in Table 38. Figure 38.
www.ti.com EMAC Port Registers 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 39 and described in Table 39. Figure 39.
www.ti.com EMAC Port Registers 5.12 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 40 and described in Table 40. Figure 40. MAC Input Vector Register (MACINVECTOR) 31 30 17 16 USER INT LINK INT 29 Reserved 18 HOST PEND STAT PEND R-0 R-0 R-0 R-0 R-0 15 0 RXPEND TXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 40.
www.ti.com EMAC Port Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (Unmasked) register (RXINTSTATRAW) is shown in Figure 41 and described in Table 41. Figure 41.
www.ti.com EMAC Port Registers 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (Masked) register (RXINTSTATMASKED) is shown in Figure 42 and described in Table 42. Figure 42.
www.ti.com EMAC Port Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 43 and described in Table 43. Figure 43.
www.ti.com EMAC Port Registers 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in Table 44. Figure 44.
www.ti.com EMAC Port Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 45 and described in Table 45. Figure 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 HOST PEND STAT PEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 45.
www.ti.com EMAC Port Registers 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 46 and described in Table 46. Figure 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 31 16 Reserved R-0 15 1 0 Reserved 2 HOST PEND STAT PEND R-0 R-0 R-0 LEGEND: R/W = R = Read only; -n = value after reset Table 46.
www.ti.com EMAC Port Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 47 and described in Table 47. Figure 47. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 1 0 Reserved 2 HOST MASK STAT MASK R-0 R/WS-0 R/WS-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 47.
www.ti.com EMAC Port Registers 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in Table 48. Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 16 Reserved R-0 15 1 0 Reserved 2 HOST MASK STAT MASK R-0 R/WC-0 R/WC-0 LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 48.
www.ti.com EMAC Port Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 49 and described in Table 49. Figure 49.
www.ti.com EMAC Port Registers Table 49.
www.ti.com EMAC Port Registers Table 49.
www.ti.com EMAC Port Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 51 and described in Table 51. Figure 51.
www.ti.com EMAC Port Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 52 and described in Table 52. Figure 52. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 52.
www.ti.com EMAC Port Registers 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 53 and described in Table 53. Figure 53. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 53.
www.ti.com EMAC Port Registers 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 54 and described in Table 54. Figure 54. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 54.
www.ti.com EMAC Port Registers 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in Figure 55 and described in Table 55. Figure 55. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXnFLOWTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 55.
www.ti.com EMAC Port Registers 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and described in Table 56. Figure 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n = value after reset Table 56.
www.ti.com EMAC Port Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57. Figure 57.
www.ti.com EMAC Port Registers Table 57.
www.ti.com EMAC Port Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 58 and described in Table 58. Figure 58.
www.ti.com EMAC Port Registers Table 58. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 15-12 11 10-8 Field Value RXERRCODE Reserved RXERRCH Description Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require hardware reset in order to recover.
www.ti.com EMAC Port Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 59 and described in Table 59. Figure 59. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 59.
www.ti.com EMAC Port Registers 5.32 FIFO Control Register (FIFOCONTROL) The FIFO control register (FIFOCONTROL) is shown in Figure 60 and described in Table 60. Figure 60. FIFO Control Register (FIFOCONTROL) 31 23 22 16 Reserved RXFIFOFLOWTHRESH R-0 R/W-2 15 5 4 0 Reserved TXCELLTHRESH R-0 R/W-24 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 60.
www.ti.com EMAC Port Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 61 and described in Table 61. Figure 61. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-24 R-68 15 8 7 0 ADDRESSTYPE MACCFIG R-2 R-3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 61.
www.ti.com EMAC Port Registers 5.34 Soft Reset Register (SOFTRESET) The Soft Reset Register (SOFTRESET) is shown in Figure 62 and described in Table 62. Figure 62. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 62. Soft Reset Register (SOFTRESET) Field Descriptions Bit 31-1 0 120 Field Reserved Value 0 SOFTRESET Description Reserved Software reset.
www.ti.com EMAC Port Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 63 and described in Table 63. Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 63.
www.ti.com EMAC Port Registers 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) The MAC Source Address High Bytes Register (MACSRCADDRHI) is shown in Figure 64 and described in Table 64. Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI) 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R/W-0 R/W-0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 64.
www.ti.com EMAC Port Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
www.ti.com EMAC Port Registers 5.38 MAC Hash Address Register 2 (MACHASH2) The MAC hash address register 2 (MACHASH2) is shown in Figure 66 and described in Table 66. Figure 66. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 66.
www.ti.com EMAC Port Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 67 and described in Table 67. Figure 67. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 67.
www.ti.com EMAC Port Registers 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in Figure 68 and described in Table 68. Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST) 31 16 Reserved R-0 15 5 4 0 Reserved PACEVAL R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 68.
www.ti.com EMAC Port Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 69 and described in Table 69. Figure 69. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 69.
www.ti.com EMAC Port Registers 5.42 Transmit Pause Timer Register (TXPAUSE) The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and described in Table 70. Figure 70. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 70. Transmit Pause Timer Register (TXPAUSE) Field Descriptions Bit Field 31-16 Reserved 15-0 PAUSETIMER 128 Value 0 Description Reserved Transmit pause timer value.
www.ti.com EMAC Port Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register (MACADDRLO) is shown in Figure 71 and described in Table 71. Figure 71. MAC Address Low Bytes Register (MACADDRLO) 31 20 19 Reserved 21 VALID MATCH FILT CHANNEL R-0 R/W-x R/W-x R/W-x 15 8 18 16 7 0 MACADDR0 MACADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 71.
www.ti.com EMAC Port Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 72 and described in Table 72. Figure 72. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 72.
www.ti.com EMAC Port Registers 5.45 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in Figure 73 and described in Table 73. Figure 73. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 73.
www.ti.com EMAC Port Registers 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 74 and described in Table 74. Figure 74. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 16 TXnHDP R/W-x 15 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 74.
www.ti.com EMAC Port Registers 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 75 and described in Table 75. Figure 75. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) 31 16 RXnHDP R/W-x 15 0 RXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 75.
www.ti.com EMAC Port Registers 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The Transmit Channel 0-7 Completion Pointer Register (TXnCP) is shown in Figure 76 and described in Table 76. Figure 76. Transmit Channel n Completion Pointer Register (TXnCP) 31 16 TXnCP R/W-x 15 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 76.
www.ti.com EMAC Port Registers 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 77 and described in Table 77. Figure 77. Receive Channel n Completion Pointer Register (RXnCP) 31 16 RXnCP R/W-x 15 0 RXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset Table 77.
www.ti.com EMAC Port Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
www.ti.com EMAC Port Registers 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) The total number of good multicast frames received on the EMAC. A good multicast frame is defined as having all of the following: • Any data or MAC control frame that was destined for any multicast address other than FF-FF-FF-FF-FF-FFh • Was of length 64 to RXMAXLEN bytes inclusive • Had no CRC error, alignment error, or code error See Section 2.5.5 for alignment/code/CRC error definitions.
www.ti.com EMAC Port Registers 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was greater than RXMAXLEN in bytes • Had no CRC error, alignment error, or code error See Section 2.5.5 for definitions of alignment, code/CRC errors.
www.ti.com EMAC Port Registers 5.50.11 Filtered Receive Frames Register (RXFILTERED) The total number of frames received on the EMAC that the EMAC address matching process indicated should be discarded.
www.ti.com EMAC Port Registers 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.50.
www.ti.com EMAC Port Registers 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late.
www.ti.com EMAC Port Registers 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not re-transmitted) CRC errors and underrun have no effect on this statistic. 5.
www.ti.com EMAC Port Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
www.ti.com EMAC Port Registers 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun.
www.ti.com Appendix A Appendix A Glossary Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor) — A small memory structure that describes a larger block of memory in terms of size, location, and state.
www.ti.com Appendix A Jumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length. The PHY that you use can place additional limits on to the length of the packets that you can transfer in a system. Link — The transmission path between any two instances of generic cabling.
www.ti.com Appendix B Appendix B Revision History Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.1 Changed Section 2.1. Section 2.1.2 Changed Section 2.1.2. Section 2.15.4 Changed Step 19. Figure 3 Changed Figure 3. Table 3 Changed Table 3 and the paragraph directly above Table 3. Figure 6 Changed Figure 6. Chapter A Added the term jumbo packets.
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