TMS320C6455/C6454 DSP DDR2 Memory Controller User's Guide Literature Number: SPRU970G December 2005 – Revised June 2011
SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Contents Preface ....................................................................................................................................... 7 1 Introduction ........................................................................................................................ 9 .............................................................................................. 9 .................................................................................................................. 9 1.
www.ti.com List of Figures 4 1 Device Block Diagram .................................................................................................... 10 2 DDR2 Memory Controller Signals ....................................................................................... 12 3 DDR2 MRS and EMRS Command ...................................................................................... 14 4 Refresh Command ......................................................................................
www.ti.com List of Tables 1 DDR2 Memory Controller Signal Descriptions ......................................................................... 12 2 DDR2 SDRAM Commands 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 .............................................................................................. Truth Table for DDR2 SDRAM Commands ............................................................................ Addressable Memory Ranges ........................................
List of Tables SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Preface SPRU970G – December 2005 – Revised June 2011 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal processors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
Read This First SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
User's Guide SPRU970G – December 2005 – Revised June 2011 C6455/C6454 DDR2 Memory Controller 1 Introduction 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79-2B standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage. 1.
Introduction www.ti.com Figure 1.
Peripheral Architecture www.ti.com 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
Peripheral Architecture www.ti.com Figure 2. DDR2 Memory Controller Signals DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DDR2 Memory Controller DSDDQM[3:0] DSDDQS[3:0] DSDDQS[3:0] DBA[2:0] DEA[13:0] DED[31:0] DEODT[1:0] DSDDQGATE[3:0] VREFSSTL DDRSLRATE Table 1. DDR2 Memory Controller Signal Descriptions 12 Pin Description DED[31:0] Bidirectional data bus. Input for data reads and output for data writes. DEA[13:0] External address output.
Peripheral Architecture www.ti.com 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set.
Peripheral Architecture 2.4.1 www.ti.com Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands.
Peripheral Architecture www.ti.com 2.4.2 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC).
Peripheral Architecture 2.4.3 www.ti.com Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DBA[2:0] selects the bank and the value of A[12:0] selects the row. When the DDR2 memory controller issues an ACTV command, a delay of tRCD is incurred before a read or write command is issued.
Peripheral Architecture www.ti.com 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command. Figure 6.
Peripheral Architecture www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows the timings diagram for a DEAC command. Figure 7.
Peripheral Architecture www.ti.com 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DSDCAS drives low, DSDWE and DSDRAS remain high, the column address is driven on DEA[12:0], and the bank address is driven on DBA[2:0]. The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or 5.
Peripheral Architecture 2.4.6 www.ti.com Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DSDDQM outputs allows byte and halfword writes to be executed. Figure 9 shows the timing for a write on the DDR2 memory controller.
Peripheral Architecture www.ti.com Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus. Figure 10. Byte Alignment DDR2 memory controller data bus DED[31:24] (Byte Lane 3) DED[23:16] (Byte Lane 2) DED[15:8] (Byte Lane 1) DED[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device The DDR2 memory controller supports both little endian and big endian formats.
Peripheral Architecture www.ti.com Figure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip select bits all combinations of IBANK and PAGESIZE values. Note that the upper three bits of the logical address cannot be used for memory addressing, as the DDR2 memory controller has a maximum addressable memory range of 512M bytes.
Peripheral Architecture www.ti.com Ending the current access is not a condition that forces the active DDR2 SDRAM row/page to be closed. The DDR2 memory controller leaves the active row open until it becomes necessary to close it. This decreases the deactivate-reactivate overhead. Figure 13. Logical Address-to-DDR2 SDRAM Address Map Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col.
Peripheral Architecture www.ti.com Figure 14. DDR2 SDRAM Column, Row, and Bank Access Bank 0 C C C o o o l l l 0 1 2 3 Row 0 Row 1 Row 2 C o l M Bank 1 C C C o o o l l l 0 1 2 3 Row 0 Row 1 Row 2 C o l M Bank 2 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank P Row 0 Row 1 Row N C C C o o o l l l 0 1 2 3 C o l M Row 2 Row N Row N Row N A 2.
Peripheral Architecture www.ti.com Figure 15. DDR2 Memory Controller FIFO Block Diagram Command FIFO Command/Data Scheduler Command to Memory EDMA BUS Write FIFO Write Data to Memory Read FIFO Read Data from Memory Registers Command Data 2.7.1 Command Ordering and Scheduling, Advanced Concept The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput.
Peripheral Architecture www.ti.com Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering: • Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open. • Selects the highest priority command from pending reads and writes to open rows. If multiple commands have the highest priority, then the DDR2 memory controller selects the oldest command.
Peripheral Architecture www.ti.com 2.7.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes, when master B attempts to read the software message it may read stale data and therefore receive an incorrect message.
Peripheral Architecture 2.9 www.ti.com Self-Refresh Mode Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power.
Peripheral Architecture www.ti.com • Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); see Section 2.11.3. At the end of the initialization sequence, the DDR2 memory controller performs an auto-refresh cycle, leaving the DDR2 memory controller in an idle state with all banks deactivated. When the initialization section is started automatically after a hard or soft reset, commands and data stored in the DDR2 memory controller FIFOs are lost.
Peripheral Architecture 2.11.2 www.ti.com DDR2 SDRAM Initialization After Reset After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence. The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device(s).
Using the DDR2 Memory Controller www.ti.com 3 Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices. The steps required to configure the DDR2 memory controller for external memory access are also described. 3.
Using the DDR2 Memory Controller www.ti.com Figure 16.
Using the DDR2 Memory Controller www.ti.com Figure 17.
Using the DDR2 Memory Controller www.ti.com Figure 18.
Using the DDR2 Memory Controller www.ti.com 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices.
Using the DDR2 Memory Controller www.ti.com Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value tREF Average Periodic Refresh Interval 7.8 μs Therefore, the value for the REFRESH-RATE can be calculated as follows: REFRESH_RATE = 250 MHz × 7.8 μs = 1950 = 79Eh Table 13 shows the resulting SDRFC configuration. Table 13. SDRFC Configuration Field Value SR 0 REFRESH_RATE 3.2.
Using the DDR2 Memory Controller www.ti.com Table 15. SDTIM2 Configuration 3.2.4 Register Field Name DDR2 SDRAM Data Sheet Parameter Name Description Data Sheet Value Formula (Register Field Must Be ≥) Field Value T_ODT tAOND tAOND specifies the ODT turn-on delay 2 (tCK cycles) tAOND 2 T_XSNR tXSNR Exit self refresh to a non-read command 137.
DDR2 Memory Controller Registers 4 www.ti.com DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller. For the memory address of these registers, see the device-specific data manual. Table 17. DDR2 Memory Controller Registers Offset 38 Acronym 00h MIDR 04h DMCSTAT 08h Register Description Section Module ID and Revision Register Section 4.1 DDR2 Memory Controller Status Register Section 4.2 SDCFG SDRAM Configuration Register Section 4.
DDR2 Memory Controller Registers www.ti.com 4.1 Module ID and Revision Register (MIDR) The Module ID and Revision register (MIDR) is shown in Figure 19 and described in Table 18. Figure 19. Module ID and Revision Register (MIDR) 31 30 29 16 Reserved MOD_ID R-0x0 R-0x0031 15 8 7 0 MJ_REV MN_REV R-0x03 R-0x0F LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18.
DDR2 Memory Controller Registers 4.2 www.ti.com DDR2 Memory Controller Status Register (DMCSTAT) The DDR2 memory controller status register (DMCSTAT) is shown in Figure 20 Figure 20. DDR2 Memory Controller Status Register (DMCSTAT) 31 30 29 16 BE Rsvd Reserved R-0x0 R-0x1 R-0x0 15 3 2 1 0 Reserved IFRDY Reserved R-0x0 R-0x0 R-0x0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19.
DDR2 Memory Controller Registers www.ti.com 4.3 SDRAM Configuration Register (SDCFG) The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the external DDR2 memory. Bits 0-14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 (unlocked).
DDR2 Memory Controller Registers www.ti.com Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued) Bit 11-9 Value CL Description CAS latency. The value of this field defines the CAS latency, to be used when accessing connected SDRAM devices. A write to this field will cause the DDR2 Memory Controller to start the SDRAM initialization sequence. This field is writeable only when the TIMUNLOCK bit is unlocked. Values 0, 1, 6, and 7 are reserved for this field. 2 CAS latency of 2.
DDR2 Memory Controller Registers www.ti.com 4.4 SDRAM Refresh Control Register (SDRFC) The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands. The SDRFC is shown in Figure 22 and described in Table 21. Figure 22.
DDR2 Memory Controller Registers 4.5 www.ti.com SDRAM Timing 1 Register (SDTIM1) The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of the DDR2CLKOUT signal. For information on the appropriate values to program each field, see the DDR2 memory section of the device-specific data manual.
DDR2 Memory Controller Registers www.ti.com Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued) Bit Field 5-3 T_RRD Value Description These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an activate command in a different bank, minus 1. The value for these bits can be derived from the trrd AC timing parameter in the DDR2 memory section of the device-specific data manual.
DDR2 Memory Controller Registers 4.6 www.ti.com SDRAM Timing 2 Register (SDTIM2) Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. For information on the appropriate values to program each field, see the DDR2 memory section of the device-specific data manual.
DDR2 Memory Controller Registers www.ti.com 4.7 Burst Priority Register (BPRIO) The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command.
DDR2 Memory Controller Registers 4.8 www.ti.com DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 26 and described in Table 25. Figure 26.
Revision History www.ti.com Revision History This revision history highlights the technical changes made to the document in this revision. See Additions/Modifications/Deletions Table 1 Modified Description for DEODT[1:0] Pins Table 10 Modified Descriptions for Bits 6 and 2 Figure 16 Modified ODT pins in figure Figure 17 Modified ODT pins in figure Figure 18 Modified ODT pins in figure NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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