TMS320C642x DSP Inter-Integrated Circuit (I2C) Peripheral User's Guide Literature Number: SPRUEN0D March 2011
SPRUEN0D – March 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated
Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 7 .............................................................................................. 7 .................................................................................................................. 7 1.
www.ti.com List of Figures 1 I2C Peripheral Block Diagram ............................................................................................. 8 2 Multiple I2C Modules Connected ......................................................................................... 9 3 Clocking Diagram for the I2C Peripheral ............................................................................... 10 4 Synchronization of Two I2C Clock Generators During Arbitration ...................................
www.ti.com List of Tables ................................................................................ 1 Operating Modes of the I2C Peripheral 2 Ways to Generate a NACK Bit........................................................................................... 16 3 Descriptions of the I2C Interrupt Events................................................................................ 21 4 Inter-Integrated Circuit (I2C) Registers ...............................................................
Preface SPRUEN0D – March 2011 Read This First About This Manual This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. The scope of this document assumes that you are familiar with the I2C-bus specification.
User's Guide SPRUEN0D – March 2011 Inter-Integrated Circuit (I2C) Peripheral 1 Introduction This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. 1.
Introduction 1.3 www.ti.com Functional Block Diagram A block diagram of the I2C peripheral is shown in Figure 1. Refer to Section 2 for detailed information about the architecture of the I2C peripheral. Figure 1. I2C Peripheral Block Diagram I2C peripheral Peripheral data bus ICXSR ICDXR ICRSR ICDRR SDA SCL CPU Clock synchronizer Control/status registers EDMA Prescaler Noise filters Arbitrator 1.
Peripheral Architecture www.ti.
Peripheral Architecture 2.2 www.ti.com Clock Generation As shown in Figure 3, PLL1 receives a signal from an external clock source and produces an I2C input clock. A programmable prescaler (IPSC bit in ICPSC) in the I2C module divides down the I2C input clock to produce a prescaled module clock. The prescaled module clock must be operated within the range of 6.7 to 13.3 MHz.
Peripheral Architecture www.ti.com The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state (IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICMDR is changed to 1. Changing the IPSC bit in ICPSC while IRS = 1 in ICMDR has no effect. Likewise, you must configure the I2C clock dividers (ICCH bit in ICCLKH and ICCL bit in ICCLKL) while the I2C module is still in reset (IRS = 0 in ICMDR). 2.
Peripheral Architecture 2.4.2 www.ti.com Data Validity The data on SDA must be stable during the high period of the clock (see Figure 5). The high or low state of the data line, SDA, can change only when the clock signal on SCL is low. Figure 5. Bit Transfer on the I2C-Bus Data line stable data SDA SCL Change of data allowed 2.
Peripheral Architecture www.ti.com 2.6 Serial Data Formats Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 1-bit to 8-bit data values. Figure 7 is shown in an 8-bit data format (BC = 000 in ICMDR). Each bit put on the SDA line is equivalent to one pulse on the SCL line. The data is always transferred with the most-significant bit (MSB) first.
Peripheral Architecture 2.6.2 www.ti.com 10-Bit Addressing Format The 10-bit addressing format (Figure 9) is like the 7-bit addressing format, but the master sends the slave address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of the 10-bit slave address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave address. The slave must send acknowledgment (ACK) after each of the two byte transfers.
Peripheral Architecture www.ti.com 2.7 Endianness Considerations When the device is configured for big-endian mode, in order for the data to be placed in the right side of the register being accessed, access to the I2C registers must be performed as follows: • 8-bit accesses: An offset of 3h must be added to the address of the register being accessed. For example, the offset address of ICDRR becomes 1Bh (18h + 3h). • 16-bit accesses: Not supported for the I2C peripheral.
Peripheral Architecture 2.9 www.ti.com NACK Bit Generation When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK bit. Table 2.
Peripheral Architecture www.ti.com 2.10 Arbitration If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration procedure is invoked. The arbitration procedure uses the data presented on the serial data bus (SDA) by the competing transmitters. Figure 12 illustrates the arbitration procedure between two devices. The first master-transmitter, which drives SDA high, is overruled by another master-transmitter that drives SDA low.
Peripheral Architecture www.ti.com 2.11 Reset Considerations The I2C peripheral has two reset sources: software reset and hardware reset. 2.11.1 Software Reset Considerations To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status bits in the I2C interrupt status register (ICSTR) are forced to their default values, and the I2C peripheral remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high-impedance state. NOTE: 2.11.
Peripheral Architecture www.ti.com 2.12.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU The following initialization procedure is for the I2C controller configured in Master Receiver mode. The CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the CPU). 1. Enable I2C clock from the Power and Sleep Controller (see the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8)). 2.
Peripheral Architecture www.ti.com 4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMR to enable the particular Interrupt. • AAS = 1; Expect an interrupt when Master's Address matches yours (ICOAR programmed value). • ICRRDY = 1; Expect a receive interrupt when a byte worth data sent from the master is ready to be read.
Peripheral Architecture www.ti.com 2.13 Interrupt Support The is capable of interrupting the DSP CPU. The CPU can determine which I2C events caused the interrupt by reading the I2C interrupt vector register (ICIVR). ICIVR contains a binary-coded interrupt vector type to indicate which interrupt has occurred. Reading ICIVR clears the interrupt flag; if other interrupts are pending, a new interrupt is generated.
Registers www.ti.com 2.16 Emulation Considerations The response of the I2C events to emulation suspend events (such as halts and breakpoints) is controlled by the FREE bit in the I2C mode register (ICMDR). The I2C peripheral either stops exchanging data (FREE = 0) or continues to run (FREE = 1) when an emulation suspend event occurs. How the I2C peripheral terminates data transactions is affected by whether the I2C peripheral is acting as a master or a slave.
Registers www.ti.com 3.1 I2C Own Address Register (ICOAR) The I2C own address register (ICOAR) is used to specify its own slave address, which distinguishes it from other slaves connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in ICMDR), only bits 6-0 are used; bits 9-7 are ignored. The I2C own address register (ICOAR) is shown in Figure 13 and described in Table 5. Figure 13.
Registers 3.2 www.ti.com I2C Interrupt Mask Register (ICIMR) The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interrupt requests. The I2C interrupt mask register (ICIMR) is shown in Figure 14 and described Table 6. Figure 14.
Registers www.ti.com 3.3 I2C Interrupt Status Register (ICSTR) The I2C interrupt status register (ICSTR) is used to determine which interrupt has occurred and to read status information. The I2C interrupt status register (ICSTR) is shown in Figure 15 and described in Table 7. Figure 15.
Registers www.ti.com Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued) Bit Field 10 XSMT Value Description Transmit shift register empty bit. XSMT indicates that the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty but the data transmit register (ICDXR) has not been loaded since the last ICDXR-to-ICXSR transfer. The next ICDXR-to-ICXSR transfer will not occur until new data is in ICDXR.
Registers www.ti.com Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued) Bit Field 1 NACK Value Description No-acknowledgment interrupt flag bit. NACK applies when the I2C is a transmitter (master or slave). NACK indicates whether the I2C has detected an acknowledge bit (ACK) or a no-acknowledge bit (NACK) from the receiver. The CPU can poll NACK or use the NACK interrupt request. 0 ACK received/NACK is not received.
Registers 3.4 www.ti.com I2C Clock Divider Registers (ICCLKL and ICCLKH) When the I2C is a master, the prescaled module clock is divided down for use as the I2C serial clock on the SCL pin. The shape of the I2C serial clock depends on two divide-down values, ICCL and ICCH. For detailed information on how these values are programmed, see Section 2.2. 3.4.1 I2C Clock Low-Time Divider Register (ICCLKL) For each I2C serial clock cycle, ICCL determines the amount of time the signal is low.
Registers www.ti.com 3.5 I2C Data Count Register (ICCNT) The I2C data count register (ICCNT) is used to indicate how many data words to transfer when the I2C is configured as a master-transmitter-receiver (MST = 1 and TRX = 1/0 in ICMDR) and the repeat mode is off (RM = 0 in ICMDR). In the repeat mode (RM = 1), ICCNT is not used. The value written to ICCNT is copied to an internal data counter. The internal data counter is decremented by 1 for each data word transferred (ICCNT remains unchanged).
Registers 3.6 www.ti.com I2C Data Receive Register (ICDRR) The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a data value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D bits are undefined. The number of data bits is selected by the bit count bits (BC) of ICMDR. The I2C receive shift register (ICRSR) shifts in the received data from the SDA pin.
Registers www.ti.com 3.8 I2C Data Transmit Register (ICDXR) The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accept a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must be right-aligned in the D bits. The number of data bits is selected by the bit count bits (BC) of ICMDR. Once data is written to ICDXR, the I2C copies the contents of ICDXR into the I2C transmit shift register (ICXSR).
Registers 3.9 www.ti.com I2C Mode Register (ICMDR) The I2C mode register (ICMDR) contains the control bits of the I2C. The I2C mode register (ICMDR) is shown in shown in Figure 22 and described in Table 14. Figure 22.
Registers www.ti.com Table 14. I2C Mode Register (ICMDR) Field Descriptions (continued) Bit Field 10 MST 9 8 7 6 Value Description Master mode bit. MST determines whether the I2C is in the slave mode or the master mode. MST is automatically changed from 1 to 0 when the I2C master generates a STOP condition. See Table 16. 0 Slave mode. The I2C is a slave and receives the serial clock from the master. 1 Master mode. The I2C is a master and generates the serial clock on the SCL pin.
Registers www.ti.com Table 14. I2C Mode Register (ICMDR) Field Descriptions (continued) Bit Field 2-0 BC Value 0-7h Description Bit count bits. BC defines the number of bits (1 to 8) in the next data word that is to be received or transmitted by the I2C. The number of bits selected with BC must match the data size of the other device. Note that when BC = 0, a data word has 8 bits.
Registers www.ti.com Table 16. How the MST and FDF Bits Affect the Role of TRX Bit ICMDR Bit MST FDF 0 0 I2C State In slave mode but not free data format TRX is a don't care. Depending on the command from the master, the I2C mode responds as a receiver or a transmitter. Function of TRX Bit 0 1 In slave mode and free data format mode The free data format mode requires that the transmitter and receiver be fixed. TRX identifies the role of the I2C: TRX = 0: The I2C is a receiver.
Registers www.ti.com 3.10 I2C Interrupt Vector Register (ICIVR) The I2C interrupt vector register (ICIVR) is used by the CPU to determine which event generated the I2C interrupt. Reading ICIVR clears the interrupt flag; if other interrupts are pending, a new interrupt is generated. If there are more than one interrupt flag, reading ICIVR clears the highest priority interrupt flag.
Registers www.ti.com 3.11 I2C Extended Mode Register (ICEMDR) The I2C extended mode register (ICEMDR) is used to indicate which condition generates a transmit data ready interrupt. The I2C extended mode register (ICEMDR) is shown in Figure 25 and described in Table 18. Figure 25. I2C Extended Mode Register (ICEMDR) 31 16 Reserved R-0 15 1 0 Reserved IGNACK BCM R-0 R/W-0 R/W-1 LEGEND: R/W = Read/Write; R= Read only; -n = value after reset Table 18.
Registers www.ti.com 3.12 I2C Prescaler Register (ICPSC) The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the desired prescaled module clock for the operation of the I2C. The IPSC bits must be initialized while the I2C is in reset (IRS = 0 in ICMDR). The prescaled frequency takes effect only when the IRS bit is changed to 1. Changing the IPSC value while IRS = 1 has no effect. The I2C prescaler register (ICPSC) is shown in Figure 26 and described in Table 19.
Registers www.ti.com 3.13 I2C Peripheral Identification Register (ICPID1) The I2C peripheral identification registers (ICPID1) contain identification data (class, revision, and type) for the peripheral. The I2C peripheral identification register (ICPID1) is shown in Figure 27 and described in Table 20. Figure 27. I2C Peripheral Identification Register 1 (ICPID1) 31 16 Reserved R-0 15 8 7 0 Class Revision R-1h R-6h LEGEND: R = Read only; -n = value after reset Table 20.
www.ti.com Appendix A Revision History Table 22 lists the changes made since the previous version of this document. Table 22. Document Revision History Reference Additions/Modifications/Deletions Section 1.2 Changed second bullet point. Section 3.5 Changed first sentence in first paragraph. Table 14 Changed Description of RM bit. Table 17 Changed Description of INTCODE bit, value = 1h. Changed Description of INTCODE bit, value = 7h.
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