SLVP089 Synchronous Buck Converter Evaluation Module User’s Guide 1998 Mixed-Signal Linear Products
Printed in U.S.A.
SLVP089 Synchronous Buck Converter Evaluation Module User’s Guide Literature Number: SLVU001A July 1998 Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Related Documentation From Texas Instruments Preface Read This First About This Manual This user’s guide is a reference manual for the SLVP089 Synchronous Buck Converter Evaluation Module used to evaluate the performance of the TL5001 PWM Controller. This document provides information to assist managers and hardware engineers in application development. How to Use This Manual This manual provides the information and instructions necessary to design, construct, operate, and understand the SLVP089.
If You Need Assistance If You Need Assistance . . . If you want to . . . Contact Texas Instruments at . . . Visit TI online World Wide Web: http://www.ti.com Request more information about Texas Instruments Mixed Signal Products (MSP) World Wide Web: http://www.ti.com/sc/docs/pic/home.htm Call the Product Information Center (PIC) hotline: (972) 644–5580 Send a fax: (972) 480–7800 Write to: Texas Instruments Incorporated Product Information Center, MS 3123 P.O.
Running Title—Attribute Reference Contents 1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
Running Title—Attribute Reference Figures 1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 2–1 2–2 2–3 2–4 Typical Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Board Layout . .
Chapter 1 Hardware The SLVP089 Synchronous Buck Converter Evaluation Module (SLVP089) provides a method for evaluating the performance of the TL5001 pulse-widthmodulation (PWM) controller. The device contains all of the circuitry necessary to control a switch-mode power supply in a voltage-mode configuration. This manual explains how to construct basic power conversion circuits including the design of the control chip functions and the basic loop.
Introduction 1.1 Introduction Synchronous buck converters provide the smaller size and higher efficiency required by electronic equipment, particularly portable battery-operated equipment. The synchronous buck converter reduces power losses associated with a standard buck converter by substituting a power MOSFET for the commutating diode. This reduces the typical 0.5-V to 1-V diode drop to 0.3 V or less and increases system efficiency by up to 10 percent.
1.2 Schematic Figure 1–2. Schematic Diagram J1 1 2 3 4 VI VI GND GND 5.5 V to 12 V + + C10 100 µ F C5 100 µ F C11 0.47 µ F R5 10 kΩ Q1 IRF7406 PMOS C14 0.1 µ F C15 1.0 µ F R6 15 Ω R10 1 kΩ CR3 BAS16ZX 0.22 µ F V DD 6 U1 TL5001 3 R2 0.033 µ F 4 1.6 kΩ 7 R9 1.00 kΩ Note: R12 10 kΩ DTC C2 C3 0.0022 µ F REG V CC R9 90.9 kΩ R11 30 kΩ COMP FB OUT RT SCP GND 8 2 4 1IN 1OUT 2IN 2OUT GND 1 CR2 BAS16ZX 5 + C1 1µ F R7 3.
Input/Output Connections 1.3 Input/Output Connections Figure 1–3 shows the input/output connections to the SLVP089. Figure 1–3. Input/Output Connections Power Supply – + C5 Q1 Q2 R5 C11 C10 U2 J1 1 L1 R7 R12 R13 C6 CR1 CR3 C14 R11CR2 TEXAS INSTRUMENTS J2 R6 R10 JMP1 C12 R4 R3 C4 TL5001 C3 +3.3V, 3 AMP SYNC. RECT BUCK R2 C2 1 C15 U1 R1 C13 C8 R9 SLVP089 R8 EVAL BOARD REV2 C9 C1 – LOAD + Notes: 1) Source power should be able to supply a minimum of 2.5 A at 5.5-V input and/or 1.
Board Layout 1.4 Board Layout Figure 1–4 shows the SLVP089 board layout. Figure 1–4. Board Layout C5 Q1 Q2 R5 C10 C11 L1 R7 U2 R13 C6 CR1 J1 1 R12 CR3 C14 1 R6 R10 JMP1 R11 CR2 TEXAS INSTRUMENTS C12 R4 R3 C15 U1 C4 TL5001 +3.3V, 3 AMP SYNC.
Bill of Materials 1.5 Bill of Materials Table 1–1 lists materials required for the SLVP089. Table 1–1. Bill of Materials Qty Reference Part Number Mfr Description 1 C1 ECS-T1CY105R Panasonic Capacitor, Tant, 1 F, 20%, A Case 1 C11 Standard 1 C13 C3225Y5V1C106Z 1 C14 Standard 1 C2 Standard 1 C3 Standard 1 C4 Standard 4 C5, C7, C10, C12 TPSD107M010R0100 1 C6 Standard m m Capacitor, Cer, 0.47 F, 10%, X7R, 1210 TDK AVX m Capacitor, Cer, 0.
Test Results 1.6 Test Results Tables 1–2 and 1–3, along with Figures 1–5 through 1–8, show the test results for the SLVP089. Table 1–2. Line/Load Regulation, 3.3-V (Total Variation) Line/Load 0.3 A 0.9 A 1.5 A 3.0 A 5.0 A Load Reg. 5.5 V Vo(V) 3.330 3.329 3.328 3.324 3.320 0.18% 6.0 V Vo(V) 3.330 3.329 3.328 3.324 3.320 0.18% 7.0 V Vo(V) 3.330 3.328 3.328 3.325 3.321 0.15% 8.0 V Vo(V) 3.330 3.329 3.328 3.325 3.321 0.15% 9.0 V Vo(V) 3.331 3.330 3.328 3.325 3.
Test Results Figure 1–6. Power Switch Turn-On and Delay from Q2 Off VCC = 12 V IO = 1.5 A Q1 DRAIN 5 V/DIV 1 Q2 GATE 5 V/DIV 2 20 ns/Div Figure 1–7. Power Switch Turn-Off and Delay to Q2 On VCC = 12 V IO = 1.
Test Results Figure 1–8. Inductor and Output Ripple VCC = 12 V IO = 1.
1-10
Chapter 2 Design Procedure There are many possible ways to proceed when designing power supplies. This chapter shows the procedure used in the design of the SLVP089. The chapter includes the following topics: Topic Page 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Design Procedures . . . . . . . . . . . . . . . . . . . . . . .
Introduction 2.1 Introduction The SLVP089 is a dc-dc synchronous buck converter module that provides a 3.3-V output at up to 3 A with an input voltage range of 5.5 V to 12 V. The PWM controller is a TL5001 operating at a nominal frequency of 100 kHz. The TL5001 is configured for a maximum duty cycle of 100 percent and has shortcircuit protection built in. The synchronous power stage consists of a PMOS switch and an NMOS synchronous rectifier.
Operating Specifications 2.2 Operating Specifications Table 2–1 lists the operating specifications for the SLVP089. Table 2–1. Operating Specifications Specification Input Voltage Range Min Typ Max 5.5 Output Voltage Range 3.10 Output Current Range 0 Operating Frequency 3.30 12 V 3.
Design Procedures 2.3 Design Procedures Detailed steps in the design of a buck-mode converter may be found in Designing With the TL5001C PWM Controller (literature number SLVA034) from TI. This section shows the basic steps involved in this design. 2.3.1 Duty Cycle Estimate The duty cycle for a continuous-mode step-down converter is approximately: D + VVO–)V Vd I SAT Assuming the diode or synchronous switch forward voltage Vd = 0.12 V and the power-switch-on voltage VSAT = 0.
Design Procedures The power dissipation (conduction + switching losses) can be approximated as: + PD ǒ I2 O r DS(ON) D Ǔ)ǒ 0.5 VI ) IO tr f f Ǔ Assuming total switching time, tr+f, = 100 ns, a 55°C maximum ambient temperature, and rDS(ON) adjustment factor = 1.6, then: PD + ) ƪ ƪ 32 (0.04 0.5 5.5 1.6) 3 ǒ ƫ Ǔ ǒ 0.64 10 –6 0.1 Ǔƫ + 10 3 100 0.45 W The thermal impedance for Q1 RqJA = 90°C/W for FR-4 with 2-oz. copper and a one-inch-square pattern, thus: + TA ) TJ 2.3.
Design Procedures 2.3.6 Controller Functions The controller functions, oscillator frequency, soft-start, dead-time-control, short-circuit protection, and sense-divider-network are discussed in this section. The oscillator frequency is set by selecting the resistance value from the graph in figure 6 of the TL5001 data sheet. For 100 kHz, a value of 90.9 kW is selected. Dead-time control provides a minimum off-time for the power switch in each cycle.
Design Procedures Calculating the pulse-width-modulator gain as the change in output voltage divided by the change in PWM input voltage gives: A PWM 0 + DVDVO + 1.39 –– 0.65 + 13.85 å 22.8 db COMP The LC filter has a double pole at: Ǹ + 2p Ǹ21.6 mH1 1 2p LC mF 168 + 2.64 kHz (worst case values) and rolls off at 40-dB per decade after that until the ESR zero is reached at: 1 2pRC 1 + 2p(0.025)ǒ210 Ǔ+ 10 –6 38 kHz This information is enough to calculate the required compensation values.
Design Procedures Figure 2–2. Compensation Network C3 R4 R2 C2 C4 R3 _ VI Vref + VO The transfer function for this circuit is: VO VI sR2(C2 ) C3)] [1 ) sC4(R3 ) R4)] + [1 )sC2R4 +ǒ [1 ) sC3R2] [1 ) sC4R3] ǒ Ǔǒ Ǔ Ǔǒ Ǔǒ Ǔ f Z1 f Z2 f P1 f P2 f P3 The desired output regulation is ±6 percent total deviation. The PWM controller tolerance is ±5 percent, and the divider resistors are 1 percent; therefore, the control loop must be very precise. A minimum dc gain of 1000 (60 dB) gives a 0.
Design Procedures Figure 2–3 shows the bode plot for the compensation network. 45 90 40 70 35 50 30 30 25 10 20 –10 15 –30 10 –50 5 –70 0 10 102 103 Frequency – Hz 104 Phase – Degrees (Dashed) Gain – dB (Solid) Figure 2–3. Bode Plot –90 105 Note from the output response shown in Figure 2–4 that the minimum phase margin is 40 degrees and the bandwidth is 18 kHz under nominal operating conditions. Figure 2–4.
2-10
