User’s Guide TPS40055-Based Design Converts 12-V Bus to 1.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 VDC to 14 VDC. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
SLUU186 − March 2004 TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070) Mark Dennis System Power Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Schematic . . . . . . . . . . . . . . . . . . . . . .
SLUU186 − March 2004 + Schematic + 3 Figure 1. TPS40055EVM−001 (HPA070) Schematic TPS40055-Based Design Converts 12-V Bus to 1.
SLUU186 − March 2004 4 Component Selection 4.1 TPS40055 Device Selection The TPS4005x family of parts offers a range of output current configurations including source only (TPS40054), source/sink (TPS40055), or source/sink with VOUT prebias (TPS40057). In this converter the TPS40055 with source/sink capability is selected.
SLUU186 − March 2004 4.3 UVLO Circuitry The user programmable UVLO built into the TPS4005x provides hysteresis for transients shorter than a total count of seven cycles. If the input voltage to the converter can be slowly rising around the minimum VIN range, external hysteresis can be incorporated to prevent multiple on/off cycles during startup or shutdown.
SLUU186 − March 2004 4.6 Output Capacitor Selection Selection of the output capacitor is based on many application variables, including function, cost, size, and availability. The minimum allowable output capacitance is determined by the amount of inductor ripple current and the allowable output ripple, as given in equation (7). C OUT(min) + I RIPPLE + 8 f V RIPPLE 8 3A 300 kHz 15 mV + 83 mF (7) In this design, COUT(min) is 83 µF with VRIPPLE=15 mV to allow for some margin.
SLUU186 − March 2004 4.8 Short Circuit Protection The TPS40055 implements short circuit protection by comparing the voltage across the topside MOSFET while it is ON to a voltage developed across RLIM due to an internal current source of 10 µA inside pin 16. Both of these voltages are negative with respect to VIN. From the datasheet equation, RLIM is defined as: R LIM + R9 + I OC R DS(on) (max) 1.
SLUU186 − March 2004 5 Test Setup Figure 2 illustrates the basic test setup needed to evaluate the TPS40055EVM−001. 5.1 DC Input Source The input voltage source should be capable of supplying between 10 VDC and 14 VDC and rated for at least 4 A of current. For best results the input leads should be made with a wire of 18AWG or larger. 5.2 Output Load The output load can be either an electronic load or a resistive load configured to draw between 0 A and 15 A.
SLUU186 − March 2004 6 Test Results / Performance Data 6.1 Efficiency and Power Loss Figure 3 shows the efficiency as the load is varied from 1 A to over 15 A. The typical efficiency remains over 90% as the load ranges from 3 A to 12 A.
SLUU186 − March 2004 6.3 Output Ripple and Transient Response Figure 6 shows the typical output voltage ripple with IOUT=15 A to be less than 20 mVpp. The transient response is shown in Figure 7 as the load is stepped from 5 A to 15 A. The voltage deviation is less than 60 mV. OUTPUT VOLTAGE RIPPLE TRANSIENT RESPONSE VOUT = 50 mV/div IOUT = 15 A VRIPPLE (10 mV/div) IOUT 5 A/div t − Time − 1 µs/div Figure 7 Figure 6 7 EVM Assembly Drawing and PCB Layout Figure 8.
SLUU186 − March 2004 Figure 9. Top Side Copper Figure 10. Internal Layer 1 Copper TPS40055-Based Design Converts 12-V Bus to 1.
SLUU186 − March 2004 Figure 11. Internal Layer 2 Copper Figure 12. Bottom Layer Copper 14 TPS40055-Based Design Converts 12-V Bus to 1.
SLUU186 − March 2004 8 List of Materials Table 1 lists the parts values of the evaluation board. These values can be modified to meet the application requirements. Table 1. TPS40055EVM−001 (HPA070) List of Materials REFERENCE DESIGNATOR QTY DESCRIPTION SIZE MFR PART NUMBER C1, C4 2 Capacitor, ceramic, 470 pF, 50 V, X7R, 10% 805 Vishay VJ0805Y471KXAAT C12, C14 2 Capacitor, ceramic, 22 µF, 16 V, X5R, 20% 1812 TDK C4532X5R1C226MT C15 1 Capacitor, ceramic, 47 µF, 6.
SLUU186 − March 2004 9 References 1. Data Sheet, TPS40055 Wide-Input Synchronous Buck Controller (SLUS593). 2. Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). 16 TPS40055-Based Design Converts 12-V Bus to 1.
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