TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide Literature Number: SPRUES0B December 2007
SPRUES0B – December 2007 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 5 1 Device Clocking .......................................................................................................... 6 .......................................................................................................... 6 ................................................................................................... 6 2 PLL Controller..........
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Overall Clocking Diagram................................................................................................... 7 PLL1 Structure in the TMS320C642x DSP ............................................................................. 12 PLL2 Structure in the TMS320C642x DSP ............................................................................. 16 Peripheral ID Register (PID) ......................................................
Preface SPRUES0B – December 2007 Read This First About This Manual Describes the operation of the phase-locked loop controller (PLLC) in the TMS320C642x Digital Signal Processor (DSP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
User's Guide SPRUES0B – December 2007 Phase-Locked Loop Controller (PLLC) 1 Device Clocking 1.1 Overview The C642x DSP requires one primary reference clock. The primary reference clock can be either crystal input or driven by external oscillators. A 15 to 30 MHZ crystal at the MXI/CLKIN pin is recommended for the system PLLs, which generate the clocks for the DSP, peripherals, and DMA. For detailed specifications on clock frequency and voltage requirements, see the device-specific data manual.
www.ti.com Device Clocking Modules in the CLKDIV6 domain (for example, CLKDIV6 domain peripherals) must run at 1/6 the DSP frequency. Modules in the CLKIN domain (for example, UART, Timer, I2C, PWM) run at the MXI/CLKIN frequency, asynchronous to the DSP. There is no fixed ratio requirement between these peripherals frequencies and the DSP frequency. Refer to device-specific data manual for the core clock domain for each peripheral. Figure 1.
www.ti.com Device Clocking 1.2.2 Core Frequency Flexibility The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following frequency ranges and multiplier/divider ratios in the data manual must be adhered to: • Input clock frequency range (MXI/CLKIN) • PLL1 multiplier (PLLM) range • PLL1 output (PLLOUT) frequency range based on the core voltage (1.
www.ti.com Device Clocking 1.2.3 DDR2/EMIF Clock The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the core clock rates to save power while maintaining the required minimum clock rate (125 MHZ) for DDR2. PLL2 must be configured to output a 2× clock to the DDR2 PHY interface.
www.ti.com Device Clocking 1.2.4 I/O Domains The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In many cases, there are frequency requirements for a peripheral pin interface that are set by an outside standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to the core frequency domain by definition.
www.ti.com PLL Controller 2 PLL Controller 2.1 PLL Module The C642x DSP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1 provides clocks (though various dividers) to most of the components of the C642x DSP. PLL2 is dedicated to the DDR2 port. The reference clock is the 15 to 30 MHZ crystal or 1.8V LVCMOS-compatible clock input, as mentioned in the data manual.
www.ti.com PLL Controller 2.2 PLL1 Control PLL1 supplies the primary C642x DSP system clock. Software controls the PLL1 operation through the system PLL controller 1 (PLLC1) registers. The registers used in PLLC1 are listed in Section 2.4. Figure 2 shows the customization of PLL1 in the C642x DSP. The domain clocks are distributed to the core clock domains (discussed in Section 1.2.
www.ti.com PLL Controller 2.2.1 Device Clock Generation PLLC1 generates several clocks from the PLL1 output clock for use by the various processors and modules. These are summarized in Table 6. SYSCLK1, SYSCLK2, and SYSCLK3 must maintain a fixed frequency ratio requirement, no matter what reference clock (PLL or bypass) or PLL frequency is used. Table 6. System PLLC1 Output Clocks 2.2.
www.ti.com PLL Controller 9. If necessary, program PLLDIV1, PLLDIV2, and PLLDIV3 registers to change the SYSCLK1, SYSCLK2, and SYSCLK3 divide values: a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress. b. Program the RATIO field in PLLDIV1, PLLDIV2, and PLLDIV3 with the desired divide factors. Note that the dividers must maintain a 1:3:6 ratio to satisfy the CLKDIV1, CLKDIV3, CLKDIV6 clock domain requirements.
www.ti.com PLL Controller 2.2.2.3 Changing SYSCLK Dividers This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. The recommendation is to stop all peripheral operation before changing the SYSCLK dividers, with the exception of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to program the PLL controller.
www.ti.com PLL Controller 2.3 PLL2 Control PLL2 provides the clock from which the DDR2 memory controller clocks are derived. The DDR PLL controller 2 (PLLC2) controls PLL2, which accepts the clock from the oscillator and also generates the various frequency clocks needed. Figure 3 shows the customization of PLL2 in the C642x DSP. The PLL2 clocks are distributed to the device as follows: • SYSCLK1: DDR2 PHY • SYSCLKBP: DDR2 VTP PLL2 supplies the DDR2 memory controller clock.
www.ti.com PLL Controller 2.3.1 Device Clock Generation PLLC2 generates clocks from the PLL2 output clock for use by the DDR2 memory controller. These are summarized in Table 7. Table 7. DDR PLLC2 Output Clocks Output Clock Used by Default Divider SYSCLK1 DDR Phy /2 SYSCLKBP DDR VTP Controller /2 The SYSCLK1 output clock divider value defaults to /2. Assuming a 25 MHZ MXI/CLKIN and the PLL2 default multiplier of ×20, this results in a 250 MHZ DDR Phy clock (125 MHZ DDR2).
www.ti.com PLL Controller Example 2. PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset This example discusses the steps to change the PLL2 frequency when the DDR2 memory controller is in reset. Note that the DDR2 memory controller is in reset after these device-level global resets: power-on reset, warm reset, max reset. 1. Leave the DDR2 memory controller in reset. 2. Program the PLL2 clocks by following the steps in the appropriate section: Section 2.3.2.2, Section 2.3.2.
www.ti.com PLL Controller 8. Program the required multiplier value in PLLM. 9. If necessary, program PLLDIV1 register to change the SYSCLK1 divide value: a. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress. b. Program the RATIO field in PLLDIV1 with the desired divide factor. In this step make sure you leave the PLLDIV1.D1EN bit set (default). c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
www.ti.com PLL Controller 2.3.2.4 Changing SYSCLK Dividers This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. 1. Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress. 2. Program the RATIO field in PLLDIV1 with the desired divide factor.
www.ti.com PLL Controller 2.4 PLL Controller Registers Table 8 lists the base address and end address for the PLL controllers. Table 9 lists the memory-mapped registers for the PLL and reset controller. See the device-specific data manual for the memory address of these registers. Table 8. PLL and Reset Controller List PLL and Reset Controller Base Address End Address Size PLLC1 1C4 0800h 1C4 0BFFh 400h PLLC2 1C4 0C00h 1C4 0FFFh 400h Table 9.
www.ti.com PLL Controller 2.4.1 Peripheral ID Register (PID) The peripheral ID register (PID) is shown in Figure 4 and described in Table 10. Figure 4. Peripheral ID Register (PID) 31 24 23 16 Reserved TYPE R-0 R-1h 15 8 7 0 CLASS REV R-8h R-Dh LEGEND: R = Read only; -n = value after reset Table 10. Peripheral ID Register (PID) Field Descriptions Bit Field 31-24 Reserved 23-16 TYPE Value 0 CLASS 7-0 REV PLLC Peripheral class 8h Current class Peripheral revision Dh 2.4.
www.ti.com PLL Controller 2.4.3 PLL Control Register (PLLCTL) The PLL control register (PLLCTL) is shown in Figure 6 and described in Table 12. Figure 6. PLL Control Register (PLLCTL) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved 9 CLKMODE 8 Reserved 7 6 PLLENSRC PLLDIS PLLRST Rsvd PLLPWRDN PLLEN R-0 R/W-0 R-1h R/W-1 R/W-1 R/W-0 R-0 R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12.
www.ti.com PLL Controller 2.4.4 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 7 and described in Table 13. Figure 7. PLL Multiplier Control Register (PLLM) 31 16 Reserved R-0 15 5 4 0 Reserved PLLM R-0 R/W-10h or 13h (1) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) For PLLC1, PLLM defaults to 10h (PLL multiply by 17); For PLLC2, PLLM defaults to 13h (PLL multiply by 20). Table 13.
www.ti.com PLL Controller 2.4.6 PLL Controller Divider 2 Register (PLLDIV2) The PLL controller divider 2 register (PLLDIV2) is shown in Figure 9 and described in Table 15. Divider 2 controls divider for SYSCLK2. PLLDIV2 is not used on PLLC2. Figure 9. PLL Controller Divider 2 Register (PLLDIV2) 31 16 Reserved R-0 15 14 5 4 0 D2EN Reserved RATIO R/W-1 R-0 R/W-2h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15.
www.ti.com PLL Controller 2.4.8 Oscillator Divider 1 Register (OSCDIV1) The oscillator divider 1 register (OSCDIV1) is shown in Figure 11 and described in Table 17. The oscillator divider 1 controls divider for OBSCLK, dividing down from the MXI/CLKIN clock. For PLLC1, the OBSCLK is connected to CLKOUT0 pin. OSCDIV1 only applies to PLLC1, and should not be used on PLLC2. Figure 11.
www.ti.com PLL Controller 2.4.9 Bypass Divider Register (BPDIV) The bypass divider register (BPDIV) is shown in Figure 12 and described in Table 18. Bypass divider controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock. BPDIV is not used for PLLC1. Figure 12. Bypass Divider Register (BPDIV) 31 16 Reserved R-0 15 14 5 4 0 BPDEN Reserved RATIO R/W-1 R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18.
www.ti.com PLL Controller 2.4.10 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) is shown in Figure 13 and described in Table 19. PLLCMD contains the command bit for the GO operation. Writes of 1 initiate command. Writes of 0 clear the bit, but have no effect. Figure 13. PLL Controller Command Register (PLLCMD) 31 16 Reserved R-0 15 1 0 Reserved GOSET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19.
www.ti.com PLL Controller 2.4.12 PLL Controller Clock Align Control Register (ALNCTL) The PLL controller clock align control register (ALNCTL) is shown in Figure 15 and described in Table 21. ALNCTL indicates which SYSCLKs need to be aligned for proper device operation. You should not modify ALNCTL from its default settings. Figure 15.
www.ti.com PLL Controller 2.4.13 PLLDIV Ratio Change Status Register (DCHANGE) The PLLDIV ratio change status register (DCHANGE) is shown in Figure 16 and described in Table 22. DCHANGE indicates if the SYSCLK divide ratio has been modified. Figure 16. PLLDIV Ratio Change Status Register (DCHANGE) 31 16 Reserved R-0 15 2 1 0 Reserved 3 SYS3 SYS2 SYS1 R-0 R-0 (1) R-0 R-0 LEGEND: R = Read only; -n = value after reset (1) For PLLC2, SYS3 is reserved and defaults to 0. Table 22.
www.ti.com PLL Controller 2.4.14 Clock Enable Control Register (CKEN) The clock enable control register (CKEN) is shown in Figure 17 and described in Table 23. CKEN provides clock enable control for miscellaneous output clocks. CKEN is only applicable to PLLC1, not PLLC2. Figure 17. Clock Enable Control Register (CKEN) 31 16 Reserved R-0 15 1 0 Reserved 2 OBSEN AUXEN R-0 R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23.
www.ti.com PLL Controller 2.4.15 Clock Status Register (CKSTAT) The clock status register (CKSTAT) is shown in Figure 18 and described in Table 24. CKSTAT shows clock status for all clocks, except SYSCLKn. Figure 18. Clock Status Register (CKSTAT) 31 16 Reserved R-0 15 3 2 1 0 Reserved 4 BPON Rsvd OBSON AUXON R-0 R-1 R-0 R-0 or 1 (1) R-0 or 1 (2) LEGEND: R = Read only; -n = value after reset (1) (2) For PLLC1, OBSON defaults to 1; for PLLC2, OBSON is reserved and defaults to 0.
www.ti.com PLL Controller 2.4.16 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) is shown in Figure 19 and described in Table 25. Indicates SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the D[n]EN bit in PLLDIV[n] default. Figure 19.
www.ti.com Appendix A Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Table 13 34 Revision History Additions/Modifications/Deletions Changed Value range of PLLM bit.
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