TMS320C6452 DSP VLYNQ Port User's Guide Literature Number: SPRUF89 October 2007
SPRUF89 – October 2007 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 7 1 Introduction .............................................................................................................. 10 1.1 2 3 Purpose of the Peripheral ..................................................................................... 10 .........................................................................................................
................................................................... 42 4 Remote Configuration Registers ................................................................................. 44 Appendix A VLYNQ Protocol Specifications ........................................................................ 45 A.1 Special 8b/10b Code Groups ................................................................................. 45 A.2 Supported Ordered Sets ...............................................................
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A-1 VLYNQ Port Functional Block Diagram ................................................................................. External Clock Block Diagram ............................................................................................ Internal Clock Block Diagram ............................................................................................. VLYNQ Module Structure ........................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A-1 A-2 A-3 B-1 B-2 B-3 B-4 6 VLYNQ Port Pins ........................................................................................................... Serial Interface Width ...................................................................................................... Address Translation Example (Single Mapped Region) ..............................................................
Preface SPRUF89 – October 2007 Read This First About This Manual This document describes the VLYNQ™ communications interface port in the TMS320C6452 Digital Signal Processor (DSP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
www.ti.com TMS320C6452 DSP SPRUF86 — TMS320C6452 Peripheral Component Interconnect (PCI) User's Guide describes the peripheral component interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller.
www.ti.com TMS320C6452 DSP SPRUF96 — TMS320C6452 DSP Telecom Serial Interface Port (TSIP) User's Guide is a multi-link serial interface consisting of a maximum of two transmit data signals (or links), two receive data signals (or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP offers single channel of timeslot data management and single DMA capability that allow individual timeslots to be selectively processed.
User's Guide SPRUF89 – October 2007 VLYNQ Port 1 Introduction 1.1 Purpose of the Peripheral The VLYNQ™ communications interface port is a serial interface with a low pin count, high-speed point-to-point serial interface in the device for connecting to host processors and other VLYNQ compatible devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference.
www.ti.com Introduction • • • • • • 1.3 Symmetric Operation: – Tx pins on first device connect to Rx pins on second device and vice versa. – Data pin widths are automatically detected after reset (including connections to legacy VLYNQ devices). – Request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins. – Supports both Host/Peripheral and Peer to Peer communication models. Simple block code packet formatting (8b/10b).
www.ti.com Peripheral Architecture 2 Peripheral Architecture This section discusses the architecture and basic functions of the VLYNQ peripheral. 2.1 Clock Control The module's serial clock direction and frequency are software configurable through the CLKDIR and CLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from the internal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations.
www.ti.com Peripheral Architecture 2.2 Signal Descriptions The VLYNQ module on the device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pin multiplexing registers control the configuration. See the pin multiplexing information in the device-specific data manual. If the configured width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.7).
www.ti.com Peripheral Architecture 2.5 VLYNQ Functional Description The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is symmetrical. The VLYNQ module structure is shown in Figure 4. Figure 4.
www.ti.com Peripheral Architecture Figure 5.
www.ti.com Peripheral Architecture Figure 6.
www.ti.com Peripheral Architecture 2.6 Initialization Since VLYNQ devices can be controlled solely over the serial interface (that is, no local CPU exists), an automatic reliable initialization sequence (without user configuration) establishes a connection between two VLYNQ devices, just after a VLYNQ module is enabled and auto-negotiation occurs. Auto-negotiation is defined in Section 2.7. The same sequence is used to recover from error conditions.
www.ti.com Peripheral Architecture In the local device, the address of the VLYNQ remote memory map in the local configuration space is the transmit address accessing remote devices over the serial interface. The address of the VLYNQ remote memory map is programmed in the TX address map register (XAM). When the local device transmits, first it strips off the transmit address offset in the local device memory map. Then, the local device sends the data with an address offset from the transmit address.
www.ti.com Peripheral Architecture The following section shows an example illustrating the address translation used in each VLYNQ module. Address bits [31:26] are not used for address translation to remote devices on the C6452 device. Table 3 illustrates address map register configuration when the device is transmitting data to the remote device. Table 3.
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www.ti.com Peripheral Architecture 2.10 Flow Control The VLYNQ module includes flow control features. The VLYNQ module automatically generates flow control enable requests, /P/, when the RX/inbound FIFOs (FIFO1 and FIFO2) resources are consumed. The FIFOs can take up to 16 32-bit words. The remote device will begin transmitting idles, /I/, starting on the first byte boundary following reception of the request.
www.ti.com Peripheral Architecture • When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register (INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line, causing the VLYNQINT to pulse. If the system writes to INTSTATCLR while interrupts are still pending, a new VLQINT interrupt is generated. The VLYNQ interrupt generation mechanism is shown in Figure 8. Figure 8.
www.ti.com Peripheral Architecture 2.12.3 Remote Interrupts Remote interrupts occur when an interrupt packet is received over the serial interface from a remote device. The interrupt status is extracted from the packet and written to a location pointed to by the interrupt pointer register (INTPTR). The INTPTR should contain the address of the interrupt pending/set register (INTPENDSET). To get INTPTR to contain the address of INTPENDSET, program INTPTR with a value of 14h (the offset for INTPENDSET).
www.ti.com Peripheral Architecture 2.14 Power Management The VLYNQ module can be placed in reduced-power modes to conserve power during periods of low activity. The power management of the peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management of all of the peripherals on the processor.
www.ti.com VLYNQ Port Registers 3 VLYNQ Port Registers Table 5 describes the address space for the VLYNQ registers and memory. Table 5. VLYNQ Register Address Space Block Name Start Address End Address Size VLYNQ Control Registers 3800 0000h 3800 01FFh 512 bytes VLYNQ Remote Memory Map 3800 0200h 38FF FFFFh 64M - 512 bytes Table 6 lists the memory-mapped registers for the VLYNQ port controller. See the device-specific data manual for the memory address of these registers.
www.ti.com VLYNQ Port Registers 3.1 Revision Register (REVID) The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVID is shown in Figure 9 and described in Table 7. Figure 9. Revision Register (REVID) 31 16 ID R-1h 15 8 7 0 REVMAJ REVMIN R-2h R-6h LEGEND: R = Read only; -n = value after reset Table 7.
www.ti.com VLYNQ Port Registers 3.2 Control Register (CTRL) The control register (CTRL) determines operation of the VLYNQ module. The CTRL is shown in Figure 10 and described in Table 8. Figure 10.
www.ti.com VLYNQ Port Registers Table 8. Control Register (CTRL) Field Descriptions (continued) Bit 7 6-3 2 1 0 28 Field Value INT2CFG Reserved Interrupt to configuration register. Determines which register is written with the status contained in interrupt packets that are received over the serial interface. Always write 1 to this bit and configure the interrupt pointer register to point to the interrupt pending/set register.
www.ti.com VLYNQ Port Registers 3.3 Status Register (STAT) The status register (STAT) is used to detect conditions that may be of interest to the system designer. The STAT is shown in Figure 11 and described in Table 9. Figure 11.
www.ti.com VLYNQ Port Registers Table 9. Status Register (STAT) Field Descriptions (continued) Bit 8 Field Value RERROR Description Remote Error. Write a 1 to this bit to clear it. 0 No error. 1 This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is set when an error indication, /E/, is received from the serial interface. See Appendix A. If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts the VLYNQ interrupt (VLQINT).
www.ti.com VLYNQ Port Registers 3.4 Interrupt Priority Vector Status/Clear Register (INTPRI) The interrupt priority vector status/clear register (INTPRI) displays the highest priority vector with a pending interrupt when read. When writing, only bits [4:0] are valid, and the value represents the vector of the interrupt to be cleared. The INTPRI is shown in Figure 12 and described in Table 10. Figure 12.
www.ti.com VLYNQ Port Registers 3.6 Interrupt Pending/Set Register (INTPENDSET) The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the serial interface, these bits are cleared. The INTPENDSET is shown in Figure 14 and described in Table 12. Figure 14.
www.ti.com VLYNQ Port Registers 3.8 Transmit Address Map Register (XAM) The transmit address map register (XAM) is used to translate transmit packet addresses to remote device configuration bus addresses. The XAM is shown in Figure 16 and described in Table 14. Figure 16. Transmit Address Map Register (XAM) 31 2 1 0 TXADRMAP Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
www.ti.com VLYNQ Port Registers 3.10 Receive Address Map Offset 1 Register (RAMO1) The receive address map offset 1 register (RAMO1) is used with the receive address map size 1 register (RAMS1) to translate receive packet addresses to local device configuration bus addresses. The RAMO1 is shown in Figure 18 and described in Table 16. Figure 18.
www.ti.com VLYNQ Port Registers 3.12 Receive Address Map Offset 2 Register (RAMO2) The receive address map offset 2 register (RAMO2) is used with the receive address map size 2 register (RAMS2) to translate receive packet addresses to local device configuration bus addresses. The RAMO2 is shown in Figure 20 and described in Table 18. Figure 20.
www.ti.com VLYNQ Port Registers 3.14 Receive Address Map Offset 3 Register (RAMO3) The receive address map offset 3 register (RAMO3) is used with the receive address map size 3 register (RAMS3) to translate receive packet addresses to local device configuration bus addresses. The RAMO3 is shown in Figure 22 and described in Table 20. Figure 22.
www.ti.com VLYNQ Port Registers 3.16 Receive Address Map Offset 4 Register (RAMO4) The receive address map offset 4 register (RAMO4) is used with the receive address map size 4 register (RAMS4) to translate receive packet addresses to local device configuration bus addresses. The RAMS4 is shown in Figure 24 and described in Table 22. Figure 24.
www.ti.com VLYNQ Port Registers 3.18 Auto Negotiation Register (AUTNGO) The auto negotiation register (AUTNGO) reflects the ability of the VLYNQ module residing in the device to communicate with the remote VLYNQ device on their respective abilities after reset. The AUTNGO is shown in Figure 26 and described in Table 24. Figure 26. Auto Negotiation Register (AUTNGO) 31 17 16 Reserved 2X R-0 R-1 15 0 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24.
www.ti.com VLYNQ Port Registers 3.20 Negotiation Status Register (NGOSTAT) The Negotiation Status Register reflects the current abilities communicated between the local and remote VLYNQ. The NGOSTAT is shown in Figure 28 and described in Table 26 Figure 28. Negotiation Status Register (NGOSTAT) 31 1 0 Reserved Mode R-0 R-1 LEGEND: R/W = Read/Write; -n = value after reset Table 26. Negotiation Status Register (NGOSTAT) Field Descriptions Bit Field Value 31-1 Reserved 0 Reserved.
www.ti.com VLYNQ Port Registers 3.21 Interrupt Vector 3-0 Register (INTVEC0) The INTVEC0 is shown in Figure 29 and described in Table 27. Figure 29.
www.ti.com VLYNQ Port Registers Table 27. Interrupt Vector 3-0 Register (INTVEC0) Field Description (continued) Bit Field 6 INTTYPE0 5 4-0 Value 0 Interrupt Vector 0 is level sensitive 1 Interrupt Vector 0 is Pulse INTPOL0 INTVEC0 Description Interrupt Type 0 Interrupt Polarity 0 0 Interrupt Vector 0 is active high 1 Interrupt Vector 0 is active low 0-1Fh SPRUF89 – October 2007 Submit Documentation Feedback Interrupt Vector 0.
www.ti.com VLYNQ Port Registers 3.22 Interrupt Vector 7-4 Register (INTVEC1) The INTVEC1 is shown in Figure 30 and described in Table 28. Figure 30.
www.ti.com VLYNQ Port Registers Table 28. Interrupt Vector 7-4 Register (INTVEC1) Field Description (continued) Bit Field 12-8 7 INTVEC5 Value 0-1Fh INTEN4 0-1 6 5 4-0 INTTYPE4 Interrupt Enable 4. When set, this bit indicates that interrupts detected should be written to the Interrupt Pending/Set Register which will subsequently generate an interrupt depending on the status of the intlocal bit in the Control Register.
www.ti.com Remote Configuration Registers 4 Remote Configuration Registers The remote configuration registers listed in Table 29 are the same registers as previously described, but they are for the remote VLYNQ device. Note: Before attempting to access the remote registers (offsets 80h through C0h) , you must ensure that a link is established with the remote device. Poll the LINK bit in the VLYNQ status register (STAT) to do this.
www.ti.com Appendix A Appendix A VLYNQ Protocol Specifications VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control. The following sections include general 8b/10b coding definitions and their implementation. A.1 Special 8b/10b Code Groups Table A-1. Special 8b/10b Code Groups A.2 Code Group Name Octet Value Octet Bits Current RD - Current RD + K28.0 1C 0001 1100 001111 0100 110000 1011 K28.
www.ti.com Supported Ordered Sets A.2.1 Idle (/I/) The idle ordered sets are transmitted continuously and repetitively whenever the serial interface is idle. Idle is also used in the place of the flowed code in VLYNQ versions 2.0 and later. A.2.2 End of Packet (/T/) An end of packet delimiter delineates the ending boundary of a packet. A.2.3 Byte Disable (/M/) The byte disable symbol masks bytes for write operations. A.2.
www.ti.com VLYNQ 2.0 Packet Format A.3 VLYNQ 2.0 Packet Format The VLYNQ 2.0 packet format is shown in Figure A-1 and described in Table A-3, where 0
www.ti.com VLYNQ 2.X Packets The CMD2 bit is only included in the packet if the packet type indicates extended command (PKTTYPE = 0110). Use configuration packet types to remotely access VLYNQ module registers. The configuration packet types do not depend on control register bit settings. A.4 VLYNQ 2.X Packets An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in Example A-1.
www.ti.com VLYNQ 2.X Packets An example of a write burst flowed and interrupted by a read return data burst is shown below. In the example, a 1 indicates a data return channel (it is actually the return data command) and a 0 indicates a command channel, which is the command for the transaction. IIIIclaaaaddddIcldddIII1ddddII0dddddddddddddIIIIII0dddTIIIII1dTIIII A command, length, address, and start receive data from the idle stream.
www.ti.com Appendix B Appendix B Write/Read Performance The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency. Note: B.1 The data and throughput calculations shown here are sample calculations for most ideal situations.
www.ti.com Write Performance Table B-1. Scaling Factors (continued) Burst Size in 32-bit words Data Bytes Overhead Bytes Scaling Factor 16 64 7 90.14% Using a VLYNQ interface running at 99 MHz, the performance shown in Table B-2 is ideally expected. Table B-2. Expected Throughput (VLYNQ Interface Running at 99 MHz) Number of VLYNQ Pins Burst Size in 32-bit Words Throughput (Mbits/sec) Throughput (Mbytes/sec) 1 1 31.68 3.96 4 55.09 6.89 8 64.98 8.12 16 71.39 8.92 1 63.36 7.
www.ti.com Write Performance Table B-3. Expected Throughput (VLYNQ Interface Running at 76.5 MHz) Number of VLYNQ Pins Burst Size in 32-bit Words Throughput (Mbits/sec) Throughput (Mbytes/sec) 1 1 24.19 3.02 4 42.07 5.26 8 49.62 6.20 16 54.52 6.81 1 48.38 6.05 4 84.14 10.52 2 3 4 52 Write/Read Performance 8 99.25 12.41 16 109.03 13.63 1 72.58 9.07 4 126.21 15.78 8 148.87 18.61 16 163.55 20.44 1 96.77 12.10 4 168.28 21.03 8 198.50 24.81 16 218.07 27.
www.ti.com Read Performance B.2 Read Performance Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes. There is latency involved in reading the data from the remote device; and in some cases, a local latency in writing the returned data before the next read can start. The max read rate is calculated the same way as the max write rate.
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