MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 D D D D D D D D D Low Supply Voltage Range 1.8 V – 3.6 V Ultralow-Power Consumption Low Operation Current, 1.3 µA at 4 kHz, 2.2 V 160 µA at 1 MHz, 2.2 V Five Power Saving Modes: (Standby Mode: 0.8 µA, RAM Retention Off Mode: 0.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 20-PIN SOWB (DW) PLASTIC 20-PIN TSSOP (PW) MSP430C1111IDW MSP430C1121IDW MSP430F1101IDW MSP430F1121IDW MSP430F1101IPW MSP430F1121IPW TA – 40°C to 85°C functional block diagram XIN VCC XOUT VSS RST/NMI P1.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Terminal Functions TERMINAL NAME I/O DESCRIPTION NO. P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 short-form description (continued) CPU All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 instruction set (continued) Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 status register R2 15 9 Reserved For Future Enhancements rw-0 8 7 6 5 4 3 2 1 0 C V SCG1 SCG0 OscOff CPUOff GIE N Z rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 memory organization MSP430C1111 FFFFh FFE0h FFDFh Int. Vector 2 KB ROM MSP430C1121 FFFFh FFE0h FFDFh F800h Int. Vector 4 KB ROM F000h Int. Vector 1 KB Flash FC00h Segment0,1 0FFFh 0C00h 128B Flash SegmentA 1 KB Boot ROM 02FFh 16b Per. 8b Per. SFR 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h FFDFh Int.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 boot ROM containing bootstrap loader (continued) features of the bootstrap loader are: D D D D D UART communication protocol, fixed to 9600 baud Port pin P1.1 for transmit, P2.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 boot ROM containing bootstrap loader (continued) Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two positive edges have been applied to TEST while RST/NMI is low, and TEST is high when RST/NMI goes from low to high. The TEST signal is normally used internally to switch pins P1.4, P1.5, P1.6, and P1.7 between their application function and the JTAG function.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Segment0 w/ Interrupt Vectors 0FDFFh 0FC00h Segment1 0FBFFh 0FA00h Segment2 0F9FFh 0F800h Segment3 0F7FFh 0F600h Segment4 The memory in SegmentA and SegmentB is also called Information Memory. 0F5FFh 0F400h Segment5 VPP is generated internally. VCC current increases during programming.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL1 (continued) Read access is possible at any time without restrictions. The control bits of control register FCTL1 are: 15 8 7 FCTL1 0128h SEG WRT rw–0 FCTL1 read: 096h FCTL1 write: 0A5h Erase MEras WRT 0 WRT rw–0 res. r0 res. res. r0 r0 MEras rw–0 Erase rw-0 res. r0 0128h, bit1, Erase a segment 0128h, bit2, 0: No segment erase will be started.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory, timing generator, control register FCTL2 (continued) The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set. Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur (ACCVIFG=1). Read access is possible at any time without restrictions. SSEL1 SSEL0 Write ’1’ to EMEX PUC FN5..........
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL3 (continued) BUSY 012Ch, bit0, The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or if an access violation occurs. The BUSY bit is read-only, but a write operation is allowed. The BUSY bit should be tested before each write and erase cycle.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 flash memory control register FCTL3 (continued) LOCK 012Ch, bit4, The lock bit may be set during any write, segment-erase, or mass-erase request. Any active sequence in progress is completed normally. In segment-write mode, the SEGWRT bit is reset and the WAIT bit is set after the mode ends. The lock bit is controlled by software or hardware.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 ACCV S ACCVIFG FCTL1.1 ACCVIE Flash Module Flash Module IE1.5 Clear Flash Module PUC RST/NMI POR KEYV PUC VCC PUC System Reset Generator POR S NMIFG NMIRS IFG1.4 Clear NMIES TMSEL NMI WDTQn EQU PUC POR PUC NMIIE WDTIFG S IE1.4 IRQ Clear IFG1.0 Clear PUC Counter OSCFault WDT POR S OFIFG IFG1.1 IRQA TIMSEL OFIF WDTIE IE1.1 Clear IE1.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with memory manipulation instructions.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 oscillator and system clock (continued) DIVA 2 LFXT1CLK /1, /2, /4, /8 OSCOff ACLK Auxiliary Clock XTS XIN ACLKGEN SELM DIVM CPUOff LFXT1 OSCILLATOR 2 2 3 0,1 /1, /2, /4, /8, Off XOUT VCC Rsel SCG0 DCO 3 0 P2.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 digital I/O (continued) The seven registers are: • • • • • • • Input register 8 bits at port P1/P2 contains information at the pins Output register 8 bits at port P1/P2 contains output information Direction register 8 bits at port P1/P2 controls direction Interrupt edge select 8 bits at port P1/P2 input signal change necessary for interrupt Interrupt flags 8 bits at port P1/P2 indicates if interrupt(s) ar
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Timer_A (3 capture/compare registers) (continued) SSEL1 P1.0 TACLK P2.1 ACLK SMCLK INCLK 32 kHz to 8 MHz Timer Clock SSEL0 0 Data 16-Bit Timer 0 15 1 16-Bit Timer CLK RC Input Divider 2 3 ID1 ID0 POR/CLR Mode Control Carry/Zero MC1 P1.1 P2.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Comparator_A The primary function of the comparator module is to support precision A/D slope conversion applications, battery voltage supervision, and observation of external analog signals. The comparator is connected to port pins P2.3/CA0 and to P2.4/CA1. It is controlled via twelve control bits in registers CACTL1 and CACTL2. 0 V VCC P2CA0 0 P2.3/ CA0/ TA1 CA0 1 CAF CAON 0 Low Pass Filter 1 1 0 P2.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Comparator_A (continued) The control bits are: CAOUT, 05Ah, bit0, Comparator output CAF, 05Ah, bit1, The comparator output is transparent or fed through a small filter CA0, 05Ah, bit2, 0: Pin P2.3/CA0/TA1 is not connected to Comparator_A. 1: Pin P2.3/CA0/TA1 is connected to Comparator_A. CA1, 05Ah, bit3, 0: Pin P2.4/CA1/TA2 is not connected to Comparator_A. 1: Pin P2.4/CA1/TA2 is connected to Comparator_A.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Comparator_A (continued) 0 7 CACTL1 059h CAEX CA RSEL CA REF1 CA REF0 CAON CAIES CAIE CAIFG rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 CACTL2 05Ah 0 CACTL 2.7 CACTL 2.6 CACTL 2.5 CACTL 2.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector CCTL2 CCTL1 CCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016C
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 absolute maximum ratings† Voltage applied at VCC to VSS (MSP430C11x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V Voltage applied at VCC to VSS (MSP430F11x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 recommended operating conditions (continued) f (system) – Maximum Processor Frequency – MHz MSP430x11x1 Devices 9 8 MHz at 3.6 V 8 7 6 5 MHz at 2.2 V 5 4 3 2 MHz at 1.8 V 2 1 0 0 1 2 3 VCC – Supply Voltage – V 4 NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V. Figure 6.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC) excluding external current (f(system) = 1 MHz) PARAMETER TEST CONDITIONS C11x1 I(AM) Active mode F11x1 C11x1 I(CPUOff) Low-power mode, (LPM0) F11x1 I(LPM2) Low power mode Low-power mode, (LPM2) I(LPM3) Low-power mode, ((LPM3)) (C11x1) Low-power mode, ((LPM3
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Schmitt-trigger inputs Port P1 to Port P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN TYP MAX VIT IT+ Positive going input threshold voltage Positive-going VCC = 2.2 V VCC = 3 V 1.1 1.3 1.5 1.8 VIT IT– Negative going input threshold voltage Negative-going VCC = 2.2 V VCC = 3 V 0.4 0.9 .90 1.2 Vh hys hysteresis (VIT+ Input voltage hysteresis, IT – VIT IT–) VCC = 2.2 V VCC = 3 V 0.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) optional resistors, individually programmable with ROM code (see Note 13) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(opt1) 2.5 5 10 kΩ R(opt2) 3.8 7.7 15 kΩ R(opt3) 7.6 15 31 kΩ 11.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs P1.x, P2.x, TAx PARAMETER f(P20) f(TAx) TEST CONDITIONS VCC CL = 20 pF TA0, TA1, TA2, CL = 20 pF Internal clock source, SMCLK signal applied (see Note 16) 2.2 V/3 V P2.0/ACLK, Output frequency fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF P1.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 700 Mean –6 Sigma 650 Mean –4 Sigma Mean Mean +4 Sigma Mean +6 Sigma V (RefVT) 600 550 500 450 –45 –25 –5 15 35 55 75 95 Temperature [°C] Figure 7.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 0 V VCC 0 1 CAF CAON Low Pass Filter V+ V– + _ 0 0 1 1 To Internal Modules CAOUT Set CAIFG Flag τ ≈ 2.0 µs Figure 9. Block Diagram of Comparator_A Module VCAOUT Overdrive V– 400 mV t(response) V+ Figure 10.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) V VCC V (POR) No POR POR V (min) POR t Figure 11. Power-On Reset (POR) vs Supply Voltage 2.0 1.8 1.8 V POR [V] 1.6 1.4 1.2 1.5 Max 1.2 1.4 1.0 Min 1.1 0.8 0.8 0.6 0.4 0.2 25°C 0 –40 –20 0 20 40 60 80 Temperature [°C] Figure 12.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS MIN TYP MAX f(DCO03) Rsell = 0 0, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25°C VCC = 2.2 V VCC = 3 V 0.08 0.12 0.15 0.08 0.13 0.16 f(DCO13) Rsell = 1 1, DCO = 3, 3 MOD = 0, 0 DCOR = 0, 0 TA = 25°C VCC = 2.2 V VCC = 3 V 0.14 0.19 0.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) principle characteristics of the DCO D D D D Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 APPLICATION INFORMATION input/output schematic Port P1, P1.0 to P1.3, input/output with Schmitt-trigger VCC P1SEL.x 0 P1DIR.x (See Note 27) 1 Direction Control From Module (See Note 28) 0 P1OUT.x Pad Logic P1.0 – P1.3 1 Module X OUT (See Note 28) (See Note 27) P1IN.x GND EN Module X IN P1IRQ.x D P1IE.x P1IFG.x Q EN Set Interrupt Flag Interrupt Edge Select P1IES.x P1SEL.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features VCC P1SEL.x 0 P1DIR.x See Note 27 1 Direction Control From Module See Note 28 0 P1OUT.x Pad Logic P1.4–P1.7 1 Module X OUT See Note 28 See Note 27 GND TST Bus Keeper P1IN.x EN Module X IN D TEST TST P1IRQ.x P1IE.x P1IFG.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Port P2, P2.0 to P2.2, input/output with Schmitt-trigger P2SEL.x VCC 0 P2DIR.x 0: Input 1 Direction Control From Module See Note 28 Pad Logic 0 P2OUT.x See Note 27 1: Output P2.0 – P2.2 1 Module X OUT See Note 28 See Note 27 GND Bus Keeper P2IN.x EN D Module X IN CAPD.X P2IRQ.x P2IE.x P2IFG.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2SEL.3 P2DIR.3 VCC 0 Direction Control From Module P2OUT.3 0: Input 1 1: Output 0 Pad Logic See Note 27 See Note 28 P2.3 1 Module X OUT See Note 28 See Note 27 P2IN.3 GND Bus Keeper EN D Module X IN P2IE.3 P2IRQ.3 P2IFG.3 Interrupt Edge Select EN Q Set Interrupt Flag CAPD.3 Comparator_A CAREF P2CA CAEX P2IES.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module VCC P2SEL.5 0: Input 1: Output 0 P2DIR.5 Pad Logic See Note 27 1 Direction Control From Module See Note 28 0 P2OUT.5 P2.5 1 Module X OUT See Note 28 See Note 27 GND Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 P2IFG.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 APPLICATION INFORMATION Port P2, unbonded bits P2.6 and P2.7 P2SEL.x 0: Input 1: Output 0 P2DIR.x 1 Direction Control From Module 0 P2OUT.x 1 Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN P2IRQ.x D P2IE.x P2IFG.x Q PUC Interrupt Edge Select EN Set Interrupt Flag P2IES.x P2SEL.x NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2DIR.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.
MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D.
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