TMS320DM36x DMSoC Analog to Digital Converter (ADC) Interface User's Guide Literature Number: SPRUFI7 March 2009
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Contents Preface ........................................................................................................................................ 5 1 Features.............................................................................................................................. 8 2 1.1 Block Diagram ............................................................................................................. 8 1.2 Industry Compliance Statement ..............................................
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADC IF Block Diagram ...................................................................................................... 8 ADC Control (ADCTL) Register .......................................................................................... 12 Comparator Target Channel (CMPTGT) Register ..................................................................... 13 Comparison A/D Lower Data (CMPLDAT) Register .......................................
Preface SPRUFI7 – March 2009 Read This First About This Manual This document describes the analog-to-digital converter (ADC) interface peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
Related Documentation From Texas Instruments www.ti.com SPRUFH2— TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.
www.ti.com Related Documentation From Texas Instruments SPRUFI2— TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Users Guide This document describes the DDR2/mDDR memory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices.
User's Guide SPRUFI7 – March 2009 Analog to Digital Converter (ADC) Interface DM36x has a 6-channel, 10-bit analog-to-digital converter (ADC) interface. The CPU communicates to the ADC interface using 32-bit-wide control registers accessible via the internal peripheral bus.
Peripheral Architecture www.ti.com 1.2 Industry Compliance Statement The ADC interface does not conform to any recognized industry standards. 2 Peripheral Architecture 2.1 Clock Control The ADC interface is driven by the auxiliary clock of the PLL controller. The frequency of the auxiliary clock is equal to the input reference clock of the PLL controller, and therefore is not affected by the multiplier and divider values of the PLL controller.
Peripheral Architecture 2.3.2 www.ti.com Free-Run Mode Operation In free-run mode operation, the ADC interface performs A/D conversion continuously without stopping. For free-run mode operation, the ADC interface should first be configured for scan mode(SCNMD), and comparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configuration options. The ADC interface sets the BUSY bit in ADCTL once it is started by writing a 1 to the START bit in the ADCTL register.
Registers www.ti.com 2.6 EDMA Event Support The ADC interface module does not generate an EDMA event. 2.7 Power Management The ADC interface can be placed in reduced-power modes to conserve power during periods of low activity. Power management of the ADC Interface is controlled by the power and sleep controller (PSC) processor. The PSC acts as a master controller for power management for all of the peripherals on the device.
Registers 3.1 www.ti.com ADCTL The ADC control register (ADCTL) is shown in Figure 2 and described in Table 2. Figure 2. ADC Control (ADCTL) Register 31 24 Reserved R-0 23 16 Reserved R-0 15 8 Reserved R-0 7 6 5 4 3 2 1 0 BUSY CMPFLG CMPIEN CMPMD SCNFLG SCNIEN SCNMD START R-0 R/C-0 R/W-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2.
Registers www.ti.com 3.2 CMPTGT The comparator target channel (CMPTGT) register is shown in Figure 3 and described in Table 3. Figure 3. Comparator Target Channel (CMPTGT) Register 31 6 5 0 Reserved CMPTGT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3. Comparator Target Channel (CMPTGT) Field Descriptions Bit Field 31-6 Reserved 5-0 CMPTGT 3.3 Value 10 Description Any writes to these bit(s) must always have a value of 0.
Registers 3.4 www.ti.com CMPUDAT The comparison A/D Upper data (CMPUDAT) register is shown in Figure 5 and described in Table 5. Figure 5. Comparison A/D Upper Data (CMPUDAT) Register 31 10 9 0 Reserved CMPUDAT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. Comparison A/D Upper Data (CMPUDAT) Field Descriptions Bit 31-10 9-0 3.5 Field Reserved Value 0 CMPUDAT Description Any writes to these bit(s) must always have a value of 0.
Registers www.ti.com Table 7. CHSEL setting for Channel selection CHSEL Selected Channel 000001b Channel 0 000010b Channel 1 000100b Channel 2 001000b Channel 3 010000b Channel 4 100000b Channel 5 Figure 7. Analog Input Channel Select (CHSEL) Register 31 6 5 0 Reserved CHSEL R-0 R/W-0x3F LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. Analog Input Channel Select (CHSEL) Field Descriptions Bit Field 31-6 Reserved 5-0 CHSEL 3.
Registers www.ti.com Table 10. A/D Conversion Data 1 (AD1DAT) Field Descriptions Bit Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. 9-0 AD1DAT A/D conversion data for channel 1 3.9 AD2DAT The A/D conversion data 2 (AD2DAT) register is shown in Figure 10 and described in Table 11. Figure 10. A/D Conversion Data 2 (AD2DAT) Register 31 10 9 0 Reserved AD2DAT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11.
Registers www.ti.com Table 13. A/D Conversion Data 4 (AD4DAT) Field Descriptions Bit Field Value Description 31-10 Reserved Any writes to these bit(s) must always have a value of 0. 9-0 AD4DAT A/D conversion data for channel 4 3.12 AD5DAT The A/D conversion data 5 (AD5DAT) register is shown in and described in . Figure 13. A/D Conversion Data 5 (AD5DAT) Register 31 10 9 0 Reserved AD5DAT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
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