User's Guide SBAU159 – October 2009 DAC7716EVM DAC7716EVM This user's guide describes the characteristics, operation, and use of the DAC7716EVM. The evaluation module (EVM) is an evaluation board that allows for quick and easy evaluation of the DAC7716. The DAC7716 is a quad, high-accuracy, 12-bit R-2-R digital-to-analog converter (DAC). The device features low-power operation, good linearity, and the ability to use different reference voltages for the output channels.
EVM Overview 1 2 3 4 5 6 7 www.ti.com Contents EVM Overview ............................................................................................................... Analog Interface ............................................................................................................. Digital Interface .............................................................................................................. Power Supplies ..................................................................
Analog Interface www.ti.com 2 Analog Interface For maximum flexibility, the DAC7716EVM can interface to multiple analog sources. Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row, header at J1. This header provides access to the analog input and output pins of the DAC. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options. Table 1 summarizes the pinouts for analog interface J1. Table 1.
Digital Interface 3.1 www.ti.com Serial Data Interface Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row, header/socket combination at J2. This header/socket provides access to the digital control and serial data pins from both J2A (top side) and J2B (bottom side) of the connector. Consult Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options. Table 2 describes the serial interface pins. Table 2.
Power Supplies www.ti.com 4 Power Supplies Samtec part numbers SSW-105-22-F-D-VS-K and TSM-105-01-T-DV-P provide a 5-pin, dual-row, header/socket combination at J3. Table 3 lists the configuration details for J3. The voltage inputs to the DAC can be applied directly to the device. The DAC7716 requires multiple power supplies to operate. AVDD, AVSS, DVDD, and IOVDD are required to properly power the DAC. Table 3. J3 Configuration: Power-Supply Input Pin No. Pin Name Function Required J3.1 +VA +4.
EVM Operation www.ti.com Note that if an external reference voltage is input to J1.20, it will be filtered through a first-order, low-pass RC filter. To input your own reference signal without this filter, connect the reference signal directly to TP1 or TP2. Figure 1 shows the reference test points on the EVM. Figure 1. Reference Test Points 6 EVM Operation This section provides information on the analog input, digital control, and general operating conditions of the DAC7716EVM. 6.
EVM Operation www.ti.com 6.3 Default Jumper Settings and Switch Positions Figure 2 shows the jumpers found on the EVM and the respective factory default conditions for each. Figure 2. DAC7716EVM Default Jumper Locations Jumper JP1 controls whether the LDAC signal is controlled by J2.15 or J2.17. By default, the LDAC signal is controlled by J2.17 but can be changed using JP1. Jumpers JP2, JP3, JP4, and JP5 are used to control the gain of the individual DAC channels.
Schematics and Layout www.ti.com Switch S1 allows the user to pull down four control signals to ground. LDAC, Uni/Bip B, RST, and Uni/Bip A can be pulled low using the switch. By default, switch position S1.1 is open, causing LDAC to be connected to ground. Switches S1.2 and S1.4 are open to short-circuit Uni/Bip A and Uni/Bip B to ground. This configuration sets the DAC7716 to bipolar mode (default). Figure 3 shows the default settings for switch S1. Figure 3.
Schematics and Layout www.ti.com space Table 4. DAC7716EVM Bill of Materials (1) (1) (2) Item No. Qty Ref Des Description Manufacturer N/A Printed wiring board Texas Instruments C1, C6, C10, C11, C14, C15 Capacitor, ceramic 1.
1 2 3 4 6 5 REVISION HISTORY REV IOVDD +VA -VA ENGINEERING CHANGE NUMBER APPROVED +5VD LDAC SDO C3 10uF C1 1uF CS C4 10uF C6 1uF C2 10uF C5 10uF SCLK D Uni/Bip A Uni/Bip B RST 10 48 36 37 1 25 24 19 12 42 GPIO-0 8 7 6 5 GPIO-1 GPIO-1 Uni/Bip A S1 DIPSWITCH-4 Uni/Bip B RST 29 30 14 28 33 K1 A1 D1A REFGND-A NC NC NC NC NC NC NC NC 200k 7 -VA J1A 10uF 23 21 22 20 JP9 46 44 45 43 Vout-2 RFB1-2 RFB2-2 SGND-2 1 3 5 7 9 11 13 15 17 19 JP2 2 4 6 8 10 12 14 16 18 20 A0
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