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SM320F2812-HT

Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SGUS062A

June 2009–Revised April 2010

Summary of content (154 pages)

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SM320F2812-HT Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Contents 1 2 3 2 ........................................................................................................................... 11 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ......................................................... 12 Introduction ...................................................................................................................... 13 2.1 Description ......................................
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SM320F2812-HT www.ti.com 4 5 6 SGUS062A – JUNE 2009 – REVISED APRIL 2010 ....................................................................................................................... 52 4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 52 4.2 Event Manager Modules (EVA, EVB) ................................................................................... 55 4.2.1 General-Purpose (GP) Timers ........................
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 7 ................................................................................................. 113 ..................................................................................... 117 6.22 XINTF Signal Alignment to XCLKOUT ................................................................................ 121 6.23 External Interface Read Timing ........................................................................................
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 List of Figures 2-1 SM320F2812 Die Layout ........................................................................................................ 15 2-2 SM320F2812 172-Pin HFG CQFP (Top View) ............................................................................... 16 3-1 Functional Block Diagram .......................................................................................................
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6-23 General-Purpose Input Timing ................................................................................................ 109 6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 110 6-25 SPI Master External Timing (Clock Phase = 1) .............................................................................
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 List of Tables 2-1 Hardware Features ............................................................................................................... 14 2-2 Bare Die Information .............................................................................................................
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 6-43 6-44 6-45 6-46 6-47 6-48 6-49 6-50 6-51 6-52 6-53 6-54 6-55 6-56 6-57 6-58 6-59 6-60 6-61 6-62 6-63 8 www.ti.com ................................................. Interrupt Switching Characteristics ...........................................................................................
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SM320F2812-HT www.ti.com 6-64 Minimum Required Wait-States at Different Frequencies Copyright © 2009–2010, Texas Instruments Incorporated SGUS062A – JUNE 2009 – REVISED APRIL 2010 ................................................................
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 10 List of Tables www.ti.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Digital Signal Processor Check for Samples: SM320F2812-HT 1 Features 12 • High-Performance Static CMOS Technology – 150 MHz (6.67 ns Cycle Time) – Low Power (1.8 V Core at 135 MHz, 1.9 V, Core at 150 MHz, 3.3 V I/O) Design – 3.
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SM320F2812-HT SGUS062A xxx – JUNE 2009 – REVISED APRIL 2010 1.1 • • • • • • • • (2) 12 www.ti.
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SM320F2812-HT www.ti.com 2 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Introduction This section provides a summary of the device features, lists the pin assignments, and describes the function of each pin. This document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging. 2.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.2 www.ti.com Device Summary Table 2-1 provides a summary of the device features. Table 2-1. Hardware Features FEATURE F2812 Instruction Cycle (at 150 MHz) 6.67 ns Single-Access RAM (SARAM) (16 bit word) 18K 3.
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SM320F2812-HT www.ti.com 2.3 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Die Layout The SM320F2812 die layout is shown in Figure 2-1. See Table 2-3 for a description of each pad's function. Figure 2-1. SM320F2812 Die Layout Table 2-2. Bare Die Information DIE SIZE 219.4 x 207.0 (mils); 5572.0 x 5258.0 (mm) DIE PAD SIZE 55.0 x 64.0 (mm) DIE PAD COORDINATES DIE THICKNESS DIE PAD COMPOSITI ON BACKSIDE FINISH BACKSIDE POTENTIAL See Table 2-3 11.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.4 www.ti.com Pin Assignments XA[11] TDI XA[10] V V DD TDO TMS XA[9] C3TRIP C2TRIP C1TRIP XA[8] XCLKOUT XA[7] TCLKINA TDIRA T2CTRIP / EVASOC V DDIO V SS V DD XA[6] T1CTRIP_PDPINTA CAP3_QEPI1 XA[5] CAP2_QEP2 CAP1_QEP1 V SS T2PWM_T2CMP XA[4] T1PWM_T1CMP PWM6 V DD V SS PWM5 XD[13] XD[12] PWM4 PWM3 PWM2 PWM1 SCIRXDB SCITXDB CANRXA The SM320F2812 172-pin HFG ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2-2.
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SM320F2812-HT www.ti.com 2.5 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Signal Descriptions Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 mA (or 20 mA) pullup/pulldown is used. Table 2-3. Signal Descriptions (1) PIN NO. NAME 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (mm) DIE PAD Y-CENTER (mm) I/O/Z (2) PU/PD (3) DESCRIPTION XINTF SIGNALS XA[18] 154 173 42.6 2281.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions PIN NO. NAME 172-PIN HFG XMP/MC XHOLD 17 155 DIE PAD NO. 23 174 DIE PAD X-CENTER (mm) 2308.2 42.6 DIE PAD Y-CENTER (mm) 42.6 2157.6 (1) I/O/Z (2) I I (continued) PU/PD (3) DESCRIPTION PD Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 2-3. Signal Descriptions PIN NO. NAME 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (mm) DIE PAD Y-CENTER (mm) (1) I/O/Z (2) (continued) PU/PD (3) DESCRIPTION JTAG AND MISCELLANEOUS SIGNALS X1/XCLKIN 75 88 5361.5 3668.7 I Oscillator Input – input to the internal oscillator. This pin is also used to feed an external clock.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions PIN NO. NAME 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (mm) DIE PAD Y-CENTER (mm) (1) I/O/Z (2) (continued) PU/PD (3) DESCRIPTION JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 2-3. Signal Descriptions PIN NO. NAME 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (mm) DIE PAD Y-CENTER (mm) (1) I/O/Z (2) (continued) PU/PD (3) DESCRIPTION ADC ANALOG INPUT SIGNALS ADCINA7 163 186 42.6 1253.9 I ADCINA6 164 188 42.6 1094.3 I ADCINA5 165 190 42.6 954.0 I ADCINA4 166 192 42.6 794.4 I ADCINA3 167 194 42.6 654.1 I ADCINA2 168 196 42.6 513.9 I ADCINA1 169 197 42.6 434.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 2-3. Signal Descriptions PIN NO. NAME 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (mm) DIE PAD Y-CENTER (mm) (1) I/O/Z (2) (continued) PU/PD (3) DESCRIPTION POWER SIGNALS VDD 22 29 2927.6 VDD 36 43 4395.4 42.6 VDD 55 62 5361.5 1256.0 VDD 73 86 5361.5 3496.4 VDD - 98 5361.5 4671.835 VDD 98 113 3861.3 5057.5 VDD 110 125 2451.9 5057.5 VDD 125 141 663.7 5057.5 VDD 140 156 42.6 3845.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Signal Descriptions (Continued) (1) GPIO PERIPHERAL SIGNAL PIN NO. 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER DIE PAD Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION GPIO OR PERIPHERAL SIGNALS GPIOA OR EVA SIGNALS GPIOA0 PWM1 (O) 90 104 4908.6 5057.5 I/O/Z PU GPIO or PWM Output Pin #1 GPIOA1 PWM2 (O) 91 106 4690.0 5057.5 I/O/Z PU GPIO or PWM Output Pin #2 GPIOA2 PWM3 (O) 92 107 4566.0 5057.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Signal Descriptions (Continued) GPIO PERIPHERAL SIGNAL PIN NO. (1) (continued) 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER DIE PAD Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION GPIOB8 CAP4_QEP3 (I) 56 64 5361.5 1428.4 I/O/Z PU GPIO or Capture Input #4 GPIOB9 CAP5_QEP4 (I) 58 66 5361.5 1600.7 I/O/Z PU GPIO or Capture Input #5 GPIOB10 CAP6_QEPI2 (I) 59 67 5361.5 1691.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Signal Descriptions (Continued) GPIO PERIPHERAL SIGNAL PIN NO. 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (1) (continued) DIE PAD Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION GPIOF OR CAN SIGNALS GPIOF6 CANTXA (O) 85 99 5361.5 4758.0 I/O/Z PU GPIO or eCAN transmit data GPIOF7 CANRXA (I) 87 101 5192.7 5057.5 I/O/Z PU GPIO or eCAN receive data GPIOF OR McBSP SIGNALS GPIOF8 MCLKXA (I/O) 27 34 3461.4 42.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Signal Descriptions (Continued) GPIO PERIPHERAL SIGNAL PIN NO. 172-PIN HFG DIE PAD NO. DIE PAD X-CENTER (1) (continued) DIE PAD Y-CENTER I/O/Z (2) PU/PD (3) DESCRIPTION GPIOG OR SCI-B SIGNALS GPIOG4 SCITXDB (O) 88 102 5098.0 5057.5 I/O/Z – GPIO or SCI asynchronous serial port transmit data GPIOG5 SCIRXDB (I) 89 103 5003.3 5057.
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SM320F2812-HT www.ti.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.1 www.ti.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-1.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset is stored in an MP/MC mode bit in the XINTCNF2 register.
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SM320F2812-HT www.ti.com 3.2 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Brief Descriptions 3.2.1 C28x CPU The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F2812 implements the real-time mode in hardware within the CPU. This is a unique feature to the F2812, no software monitor is required.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-3. Boot Mode Selection BOOT MODE SELECTED (1) GPIO PU status (3) GPIOF4 (SCITXDA) GPIOF12 (MDXA) GPIOF3 (SPISTEA) GPIOF2 (SPICLK) (2) PU No PU No PU No PU Jump to Flash/ROM address 0x3F 7FF6 A branch instruction must have been programmed here prior to reset to redirect code execution as desired.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 3.2.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 HALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowest possible power consumption mode. Only a reset or XNMI wakes the device from this mode. 3.2.16 Peripheral Frames 0, 1, 2 (PFn) The F2812 segregates peripherals into three sections.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.2.20 Serial Port Peripherals The F2812 supports the following serial communication peripherals: eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. McBSP This is the multichannel buffered serial port that is used to connect to E1/T1 lines, : phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC devices.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-4.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 3-6.
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SM320F2812-HT www.ti.com 3.4 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-7. Table 3-7.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Data Space Prog Space 0x00 0000 XD(15:0) XA(18:0) 0x00 2000 0x00 4000 XINTF Zone 0 (8K × 16) XINTF Zone 1 (8K × 16) XZCS0 XZCS1 XZCS0AND1 0x00 6000 0x08 0000 XINTF Zone 2 (512K × 16) XZCS2 0x10 0000 XINTF Zone 6 (512K × 16) XZCS6 XINTF Zone 7 (16K × 16) (mapped here if MP/MC = 1) XZCS7 XZCS6AND7 0x18 0000 0x3F C000 0x40 0000 A. B. C. D.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 The operation and timing of the external interface, can be controlled by the registers listed in Table 3-8. Table 3-8.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.6 www.ti.com Interrupts Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 IFR(12:1) INTM IER(12:1) INT1 INT2 1 MUX INT11 INT12 (Flag) INTx Global Enable (Enable) INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 MUX PIEACKx (Enable/Flag) CPU 0 (Enable) (Flag) PIEIERx(8:1) PIEIFRx(8:1) From Peripherals or External Interrupts Figure 3-5. Multiplexing of Interrupts Using the PIE Block Table 3-10. PIE Peripheral Interrupts (1) CPU INTERRUPTS (1) PIE INTERRUPTS INTx.8 INTx.7 INTx.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 3-11.
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SM320F2812-HT www.ti.com 3.6.1 SGUS062A – JUNE 2009 – REVISED APRIL 2010 External Interrupts Table 3-12.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.7 www.ti.com System Control This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-6 shows the various clock and reset domains in the F2812 device that are discussed. See Note A A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency. Figure 3-6.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13. Table 3-13.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.8 www.ti.com OSC and PLL Block Figure 3-7 shows the OSC and PLL block on the F2812. XPLLDIS Latch XF_XPLLDIS XRS OSCCLK (PLL Disabled) X1/XCLKIN XCLKIN 0 CLKIN CPU On-Chip Oscillator (OSC) PLL Bypass /2 SYSCLKOUT 1 4-Bit PLL Select X2 PLL 4-Bit PLL Select PLL Block Figure 3-7. OSC and PLL Block The on-chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1/XCLKIN and X2 pins.
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SM320F2812-HT www.ti.com 3.8.1 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Loss of Input Clock In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL still issues a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1 MHz to 4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to work.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 • • • www.ti.com CL1 = CL2 = 24 pF Cshunt = 6 pF ESR range = 25 to 40 Ω 3.11 Watchdog Block The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.12 Low-Power Modes Block The low-power modes on the F2812 are similar to the 240x devices. Table 3-16 summarizes the various modes. Table 3-16.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 4 www.ti.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-2. INT1 to INT12 PIE TINT0 CPU-TIMER 0 C28x INT13 CPU-TIMER 1 (Reserved for TI system functions) TINT1 XINT13 INT14 A. B. TINT2 CPU-TIMER 2 (Reserved for TI system functions) The timer registers are connected to the Memory Bus of the C28x processor.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-1.
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SM320F2812-HT www.ti.com 4.2 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Event Manager Modules (EVA, EVB) The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 4-2 shows the module and signal names used.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-3.
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SM320F2812-HT www.ti.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.2.1 www.ti.com General-Purpose (GP) Timers There are two GP timers.
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SM320F2812-HT www.ti.com 4.2.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.3 www.ti.com Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include: • 12-bit ADC core with built-in S/H • Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 System Control Block SYSCLKOUT High-Speed Prescaler ADCENCLK C28x HSPCLK Analog MUX Result Registers Result Reg 0 ADCINA0 70A8h Result Reg 1 S/H ADCINA7 12-Bit ADC Module Result Reg 7 70AFh Result Reg 8 70B0h Result Reg 15 70B7h ADCINB0 S/H ADCINB7 ADC Control Registers S/W EVA SOC Sequencer 2 Sequencer 1 S/W SOC EVB ADCSOC Figure 4-4.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Figure 4-5 shows the ADC pin-biasing for internal reference and Figure 4-6 shows the ADC pin-biasing for external reference. ADCINA[7:0] ADCINB[7:0] ADCLO Test Pin ADCBGREFIN† ADC 16-Channel Analog Inputs Analog input 0−3 V with respect to ADCLO Connect to Analog Ground 24.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Test Pin ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Input ADCREFP 2V ADC Reference Medium Input ADCREFM 1V ADC 16-Channel Analog Inputs Analog Input 0−3 V With Respect to ADCLO Connect to Analog Ground 24.9 k 20 k (See Note C) 1 F − 10 F NOTES: A. B. C. D. ADC Analog Power VDDA1 VDDA2 VSSA1 VSSA2 Analog 3.3 V Analog 3.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4. Table 4-4.
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SM320F2812-HT www.ti.com 4.4 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Enhanced Controller Area Network (eCAN) Module The CAN module has the following features: • Fully compliant with CAN protocol, version 2.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 eCAN0INT www.ti.com Controls Address eCAN1INT Data 32 Enhanced CAN Controller Message Controller Memory Management Unit Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit Words 32 CPU Interface, Receive Control Unit, Timer Management Unit 32 eCAN Memory (512 Bytes) Registers and Message Objects Control 32 eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.
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SM320F2812-HT www.ti.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4-6.
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SM320F2812-HT www.ti.com 4.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of Peripheral Frame 2.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 4-7 provides a summary of the McBSP registers. Table 4-7.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-7.
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SM320F2812-HT www.ti.com 4.6 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Serial Communications Interface (SCI) Module The F2812 device include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Figure 4-10 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode TXSHF Register Parity Even/Odd Enable TXENA 8 SCICCR.6 SCICCR.5 TXRDY TXWAKE SCICTL1.3 Transmitter−Data Buffer Register 8 1 TX INT ENA SCICTL2.7 SCICTL2.0 TX FIFO Interrupts TX FIFO _0 TX FIFO _1 SCITXD TX EMPTY SCICTL2.6 TXINT TX Interrupt Logic −−−−− To CPU TX FIFO _15 WUT SCI TX Interrupt select logic SCITXBUF.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.7 www.ti.com Serial Peripheral Interface (SPI) Module The F2812 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4-10. Table 4-10.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Figure 4-11 is a block diagram of the SPI in slave mode. SPIFFENA Overrun INT ENA Receiver Overrun Flag SPIFFTX.14 RX FIFO registers SPISTS.7 SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 −−−−− SPIINT/SPIRXINT RX FIFO Interrupt RX Interrupt Logic RX FIFO _15 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.
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SM320F2812-HT www.ti.com 4.8 SGUS062A – JUNE 2009 – REVISED APRIL 2010 GPIO MUX The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pins can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 4-12.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Figure 4-12 shows how the various register bits select the various modes of operation for GPIO function. GPxDAT/SET/CLEAR/TOGGLE Register Bit(s) GPxQUAL Register Digital I/O GPxMUX Register Bit 0 Peripheral I/O HighImpedance Control GPxDIR Register Bit 0 1 MUX 1 MUX SYSCLKOUT Input Qualification High-Impedance Enable (1) XRS Internal (Pullup or Pulldown) PIN A. B.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 5 www.ti.com Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 SM PREFIX TMX = TMP = TMS = SM = SMJ = 320 F 2812 HFG M TEMPERATURE RANGE experimental device prototype device qualified device commercial processing MIL-PRF-38535 (QML) S = -55°C to 220°C PACKAGE TYPE DEVICE FAMILY 320 = TMS320 DSP Family TECHNOLOGY F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O) C = ROM (1.8-V/1.9-V Core/3.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074) describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial communication interface.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Updated information on the TMS320™ DSP controllers can be found on the worldwide web at: http://www.ti.com . To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number SPRS174), use the commentsatbooks.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.2 See www.ti.com Recommended Operating Conditions (1) MIN VDDIO Device supply voltage, I/O VDD, VDD1 Device supply voltage, CPU VSS Supply ground NOM MAX UNIT 3.14 3.3 3.47 1.8 V (135 MHz) 1.71 1.8 1.89 1.9 V (150 MHz) 1.81 1.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 1.00E+06 Hours 1.00E+05 1.00E+04 1.00E+03 1.00E+02 70 150 200 220 Die Junction Temperature (°C) Figure 6-1. SM320F2812-HT Life Expectancy Curve Notes: 1. See data sheet for absolute maximum and minimum recommended operating conditions. 2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.4 www.ti.com Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT TA = –55°C to 125°C MODE TEST CONDITIONS IDD IDDIO IDDA (1) TYP MAX (2) TYP Operational All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is continuously transmitted out of the SCIA, SCIB, and 195 mA 230 mA 15 mA CAN ports. The hardware multiplier is exercised.
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SM320F2812-HT www.ti.com 6.5 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Current Consumption Graphs 250 Current (mA) 200 150 100 50 0 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) IDD A. B. C. D. IDDIO IDD3VFL IDDA Total 3.3−V current Test conditions are as defined in Table 6-5 for operational currents under nominal process voltage and temperature conditions. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a trivial amount of current (<1 mA) drawn by VDD1.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.6 www.ti.com Reducing Current Consumption 28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 6-1 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. Table 6-1.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-2. Recommended Low-Dropout Regulators SUPPLIER PART NUMBER Texas Instruments TPS767D301 NOTE The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V. See Figure 6-8, Figure 6-4. F2812 Typical Power-Up and Power-Down Sequence – Option 2 6.8 Signal Transition Levels Note that some of the signals use different reference voltages, see the recommended operating conditions table.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 2.4 V (VOH) 80% 20% 0.4 V (VOL) Figure 6-5. Output Levels Output transition times are specified as follows: • For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.10 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.12 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP. Table 6-3 lists the cycle times of various clocks. Table 6-3.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled (1) NO. C8 tc(CI) Cycle time, XCLKIN MIN MAX UNIT 6.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com See Note A See Note B A. B. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configuration. XCLKOUT configured to reflect SYSCLKOUT. Figure 6-8. Clock Timing 6.14 Reset Timing Table 6-9.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 VDDIO, VDD3VFL VDDAn, VDDAIO (3.3 V) (See Note B) 2.5 V VDD, VDD1 (1.8 V (or 1.9 V)) 0.3 V XCLKIN X1 XCLKIN/8 (See Note C) XCLKOUT User-Code Dependent tOSCST tw(RSL1) XRS Address/Data Valid.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 VDDIO, VDD3VFL VDDAn, VDDAIO (3.3 V) VDD, VDD1 (1.8 V (or 1.9 V)) www.ti.com 2.5 V 0.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.15 Low-Power Mode Wakeup Timing Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table. Table 6-10.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table. Table 6-11.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A C E B Device Status STANDBY D F STANDBY Normal Execution Flushing Pipeline Wake−up Signal tw(WAKE-INT) td(WAKE-STBY) X1/XCLKIN td(IDLE−XCOH) XCLKOUT† 32 SYSCLKOUT Cycles NOTES: A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned off.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-12.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 A. B. C. D. E. F. G. H. www.ti.com IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush perperly. Clocks to the device are turned off and the internal oscillator and PLL are shut down.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-13.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-15. External ADC Start-of-Conversion – EVA – Switching Characteristics (1) PARAMETER MIN td(XCOH-EVASOCL) Delay time, XCLKOUT high to EVASOC low tw(EVASOCL) Pulse duration, EVASOC low (1) (2) (2) MAX UNIT 1 × tc(SCO) cycle 32 × tc(HCO) ns XCLKOUT = SYSCLKOUT Not production tested. XCLKOUT td(XCOH-EVASOCL) tw(EVASOCL) EVASOC Figure 6-18. EVASOC Timing Table 6-16.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-18.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com XCLKOUT td(XCOH-GPO) GPIO tr(GPO) tf(GPO) Figure 6-21. General-Purpose Output Timing 6.18 General-Purpose Input/Output (GPIO) – Input Timing See Note A GPIO Signal 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 QUALPRD Sampling Window SYSCLKOUT QUALPRD = 1 (2 x SYSCLKOUT cycles) x 5 Output From Qualifier NOTES: A. This glitch is ignored by the input qualifier.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 XCLKOUT GPIOxn tw(GPI) Figure 6-23. General-Purpose Input Timing NOTE The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC pins as well. 6.19 SPI Master Mode Timing Table 6-21. SPI Master Mode External Timing (Clock Phase = 0) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. 1 MAX MIN MAX 128tc(LCO) 5tc(LCO) 127tc(LCO) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz). 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid SPISTE (see Note A) A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-22. SPI Master Mode External Timing (Clock Phase = 1) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. 1 MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master Out Data Is Valid SPISIMO Data Valid 10 11 Master In Data Must Be Valid SPISOMI SPISTE (see Note A) A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-25.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.20 SPI Slave Mode Timing Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0) (1) NO. 12 13 (4) 14 (4) 15 (4) 16 20 (1) (2) (3) (4) MIN Cycle time, SPICLK tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1) (1) NO. 12 13 (4) 14 (4) 17 MIN Cycle time, SPICLK tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.21 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6-25 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles. Table 6-25.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions: Table 6-28. XTIMING Register Configuration Restrictions (1) (1) (2) (2) XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥1 ≥1 ≥0 ≥1 ≥1 ≥0 0, 1 Not production tested.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 or Table 6-31. XTIMING Register Configuration Restrictions (1) (1) (2) (2) XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥2 ≥1 0 ≥2 ≥1 0 0, 1 Not production tested. No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Asynchronous XREADY: Table 6-32.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-28. XTIMING0 XTIMING1 XTIMING2 LEAD/ACTIVE/TRAIL XTIMING6 XTIMING7 XBANK SYSCLKOUT C28x CPU /2 1† XTIMCLK 0 1 XCLKOUT 1† /2 0 0 0 XINTCNF2 (XTIMCLK) † XINTCNF2 (CLKMODE) XINTCNF2 (CLKOFF) Default Value after reset Figure 6-28.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.22 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency of XTIMCLK.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.23 External Interface Read Timing Table 6-34.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE ≥1 ≥0 ≥0 0 0 N/A (1) N/A (1) N/A (1) N/A (1) (1) N/A = "Don't care" for this example 6.24 External Interface Write Timing Table 6-36.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.25 External Interface Ready-on-Read Timing With One External Wait State Table 6-37.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-40.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 WS (Asynch) Active Lead See Note C Trail XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK td(XCOH-XZCSL) XZCS0AND1, XZCS2, XZCS6AND7 td(XCOHL-XZCSH) td(XCOH-XA) XA[0:18] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD tsu(XD)XRD XWE ta(XRD) XR/W ta(A) th(XD)XRD DIN XD[0:15] tsu(XRDYasynchL)XCOHL te(XRDYasynchH) th(XRDYasynchH)XZCSH th(XRDYasynchL) tsu(XRDYasynchH)XCOHL XREADY(Asynch) See Note D See Note E Legend: = Don’t care.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.26 External Interface Ready-on-Write Timing With One External Wait State Table 6-41.
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SM320F2812-HT www.ti.com 6.27 SGUS062A – JUNE 2009 – REVISED APRIL 2010 XHOLD and XHOLDA f the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode. On a reset (XRS), the HOLD mode bit is set to 0.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.28 www.ti.com XHOLD/XHOLDA Timing Table 6-44.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-45.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.29 On-Chip Analog-to-Digital Converter 6.29.1 ADC Absolute Maximum Ratings Supply voltage range VALUE (1) UNIT VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG –0.3 to 4.6 V VSS1 to VDD1 –0.3 to 2.5 V ±20 mA Analog Input (ADCIN) Clamp Current, total (max) (1) (2) 134 (2) Unless otherwise noted, the absolute maximum ratings are specified over operating conditions.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions Table 6-46. DC Specifications (1) (2) TA = –55°C to 220°C PARAMETER MIN Resolution ADC clock (3) TYP UNIT MAX 12 Bits 1 kHz 25 MHz ACCURACY INL (Integral nonlinearity) (4) 1–18.75 MHz ADC clock ±1.5 LSB DNL (Differential nonlinearity) (4) 1–18.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-47. AC Specifications (1) (2) TA = –55°C to 125°C PARAMETER MIN TYP MAX TA = 220°C MIN TYP MAX UNIT SINAD Signal-to-noise ratio + distortion 62 57 dB SNR Signal-to-noise ratio 62 57 dB THD Total harmonic distortion -68 -68 dB ENOB (SNR) Effective number of bits 10.1 9.1 Bits SFDR Spurious free dynamic range 69 68 dB (1) (2) Not production tested.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Rs Source Signal Ron 1 kΩ ADCIN0 Switch Cp 10 pF ac Ch 1.25 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): Sampling Capacitor (Ch): Parasitic Capacitance (Cp): Source Resistance (Rs): 1 kΩ 1.25 pF 10 pF 50 Ω Figure 6-37. ADC Analog Input Impedance Model 6.29.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.29.5 Detailed Description 6.29.5.1 Reference Voltage The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP is set to 2 V and ADCVREFM is set to 1 V. 6.29.5.2 Analog Inputs The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time. These inputs are software-selectable. 6.29.5.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-50. Sequential Sampling Mode Timing (1) SAMPLE n SAMPLE n + 1 AT 25–MHz ADC CLOCK, tc(ADCCLK) = 40 ns REMARKS Acqps value = 0-15 ADCTRL1[8:11] td(SH) Delay time from event trigger to sampling 2.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on two selected channels on every Sample/Hold pulse.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-51. Simultaneous Sampling Mode Timing SAMPLE n td(schB0_n+1) Delay time for successive results to appear in Result register (1) (continued) SAMPLE n + 1 AT 25-MHz ADC CLOCK, tc(ADCCLK) = 40 ns (3 + Acqps) × tc(ADCCLK) 120 ns REMARKS 6.29.8 Definitions of Specifications and Terminology 6.29.8.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing Table 6-52. McBSP Timing Requirements (1) (2) (3) NO.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-53. McBSP Switching Characteristics (1) NO.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY= 00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY= 01b) Bit (n−1) (n−2) M17 (n−3) M18 DR (RDATDLY= 10b) Bit (n−1) (n−2) Figure 6-41.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.30.2 McBSP as SPI Master or Slave Timing Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1) NO.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1) MASTER NO. MIN SLAVE MAX MIN MAX UNIT M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high P – 10 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high P – 10 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns M42 tc(CKX) Cycle time, CLKX 16P ns (1) 2P Not production tested.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1) NO. MASTER SLAVE MIN MIN MAX MAX UNIT M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high P – 10 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high P – 10 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns M52 tc(CKX) Cycle time, CLKX 16P ns (1) 2P Not production tested.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1) NO. MASTER SLAVE MIN MIN MAX MAX UNIT M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low P – 10 8P – 10 ns M59 th(CKXL-DRV) Hold time, DR valid after CLKX low P – 10 8P – 10 ns M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns M61 tc(CKX) Cycle time, CLKX 16P ns (1) 2P Not production tested.
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SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.31 Flash Timing 6.31.1 Recommended Operating Conditions (4) Nf Flash endurance for the array (Write/erase cycles) 0°C to 85°C NOTP Maximum One-Time Programmable (OTP) endurance for the array (Write cycles) 0°C to 85°C (4) MIN NOM 100 1000 UNIT cycles 1 write Flash Timing Endurance is the minimum number of write/erase or write cycles specified over a programming temperature range of 0°C to 85°C.
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SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-64.
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SM320F2812-HT www.ti.com 7 SGUS062A – JUNE 2009 – REVISED APRIL 2010 Mechanical Data The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
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PACKAGE OPTION ADDENDUM www.ti.
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