Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 44 (16.58x16.58) 8-Bit 15 MHz I/O number 40

COP8SGE5, COP8SGE7, COP8SGH5

COP8SGK5, COP8SGR5, COP8SGR7

www.ti.com

SNOS516E –JANUARY 2000–REVISED APRIL 2013

COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k

Memory, Two Comparators and USART

Check for Samples: COP8SGE5, COP8SGE7, COP8SGH5, COP8SGK5, COP8SGR5, COP8SGR7

KEY FEATURES

PERIPHERAL FEATURES

2345

• Low Cost 8-Bit Microcontroller

• Multi-Input Wakeup Logic

• Quiet Design (Low Radiated Emissions) • Three 16-bit timers (T1 — T3), each with two

16-bit registers supporting:

• Multi-Input Wakeup Pins with Optional

Interrupts (8 pins) – Processor Independent PWM mode

• Mask Selectable Clock Options – External Event Counter mode

– Crystal Oscillator – Input Capture mode

– Crystal Oscillator Option with On-Chip Bias • Idle Timer (T0)

Resistor

• MICROWIRE/PLUS Serial Interface (SPI

– External Oscillator Compatible)

– Internal R/C Oscillator • Full Duplex USART

• Internal Power-On-Reset—User Selectable • Two Analog Comparators

• WATCHDOG and Clock Monitor Logic—User

I/O FEATURES

Selectable

• Software Selectable I/O Options (TRI-STATE

• Eight High Current Outputs

Output,Push-Pull Output, Weak Pull-Up Input,

• 256 or 512 Bytes On-Board RAM

and High Impedance Input)

• 8k to 32k ROM or OTP EPROM with Security

• Schmitt Trigger Inputs on Ports G and L

Feature

• Eight High Current Outputs

CPU FEATURES

• Packages: 28 SOIC with 24 I/O pins, 40 PDIP

with 36 I/O pins, 44 PLCC, LQFP and WQFN

• Versatile Easy to Use Instruction Set

with 40 I/O pins

• 0.67 μs Instruction Cycle Time

• Fourteen Multi-Source Vectored Interrupts

FULLY STATIC CMOS DESIGN

Servicing

• Low Current Drain (typically < 4 μA)

– External Interrupt / Timers T0 — T3

• Two Power Saving Modes: HALT and IDLE

– MICROWIRE/PLUS™ Serial Interface

– Multi-Input Wake Up

TEMPERATURE RANGE

– Software Trap

• −40°C to +85°C, −40°C to +125°C

– USART (2; 1 Receive and 1 Transmit)

– Default VIS (Default Interrupt)

DEVELOPMENT SUPPORT

• 8-Bit Stack Pointer SP (Stack in RAM)

• Windowed Packages for PDIP and PLCC

• Two 8-bit Register Indirect Data Memory

• Real Time Emulation and Debug Tools

Pointers

Available

• True Bit Manipulation

• BCD Arithmetic Instructions

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2COP8, MICROWIRE/PLUS, WATCHDOG are trademarks of Texas Instruments.

3iceMASTER is a registered trademark of MetaLink Corporation.

4MICROWIRE/PLUS, DriveWay are trademarks of dcl_owner.

5All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (81 pages)

PAGE 1
COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com DESCRIPTION The COP8SG Family ROM and OTP based microcontrollers are highly integrated COP8™ Feature core devices with 8k to 32k memory and advanced features including Analog comparators, and zero external components.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Block Diagram Figure 1. COP8SGx Block Diagram Device Description ARCHITECTURE The COP8 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Single Byte/Single Cycle Code Execution The efficiency is due to the fact that the majority of instructions are of the single byte variety, resulting in minimum program space. Because compact code does not occupy a substantial amount of program memory space, designers can integrate additional features and functionality into the microcontroller program memory space.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Connection Diagram Figure 2. Top View 28-Lead SOIC or PDIP See DW or N Package Figure 5. Top View 44-Lead PLCC See FN Package Figure 3. Top View 44-Lead WQFN See NJN Package Figure 4. Top View 40-Lead PDIP See NFJ Package Figure 6.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Table 1. Pinouts for 28 -, 40- and 44-Pin Packages Port Type Alt.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Ordering Information PDIP PDIP PDIP LQFP Figure 7. Part Numbering Scheme Electrical Characteristics Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) 7V −0.3V to VCC +0.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) −40°C ≤ TA ≤ +85°C unless otherwise specified. Parameter IDLE Current Conditions Min Typ Max Units (2) CKI = 15 MHz VCC = 5.5V, tC = 0.67 μs 2.25 mA CKI = 10 MHz VCC = 5.5V, tC = 1 μs 1.5 mA CKI = 4 MHz VCC = 4.5V, tC = 2.5 μs 0.8 mA Input Levels (VIH, VIL) RESET 0.8 Vcc Logic High V Logic Low 0.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 AC Electrical Characteristics −40°C ≤ TA ≤ +85°C unless otherwise specified. Parameter Instruction Cycle Time (tC) Conditions Crystal/Resonator, External Typ 4.5V ≤ VCC ≤ 5.5V 0.67 2.7V ≤ VCC ≤ 4.5V 2 Max Units μs μs 4.5V ≤ VCC ≤ 5.5V R/C Oscillator (Internal) Frequency Variation Min (1) (2) 4.5V ≤ VCC ≤ 5.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) 7V −0.3V to VCC +0.3V Voltage at Any Pin Total Current into VCC Pin (Source) 100 mA Total Current out of GND Pin (Sink) 110 mA −65°C to +140°C Storage Temperature Range ESD Protection Level (1) (2) 2kV (Human Body Model) Absolute maximum ratings indicate limits beyond which damage to the device may occur.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 DC Electrical Characteristics (continued) −40°C ≤ TA ≤ +125°C unless otherwise specified. Parameter Conditions Min Typ Max Units Output Current Levels D Outputs Source VCC = 4.5V, VOH = 3.3V −0.4 mA Sink VCC = 4.5V, VOL = 1.0V 9 mA All Others Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 2.7V −9 Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.3V −0.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Comparators AC and DC Characteristics VCC = 5V, −40°C ≤ TA ≤ +125°C. Parameter Input Offset Voltage (1) Conditions Min 0.4V ≤ VIN ≤ VCC − 1.5V Input Common Mode Voltage Range ±5 Units ±25 mV 100 Low Level Output Current VOL = 0.4V −1.6 High Level Output Current VOH = VCC − 0.4V 1.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Typical Performance Characteristics TA = 25°C (unless otherwise specified) Figure 9. Figure 10. Figure 11. Figure 12.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Pin Descriptions The COP8SGx I/O structure enables designers to reconfigure the microcontroller's I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R/C or external clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeroes.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com NOTE Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.7 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF. Figure 13. I/O Port Configurations Figure 14. I/O Port Configurations—Output Mode Figure 15.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The architecture of the devices are a modified Harvard architecture. With the Harvard architecture, the program memory ROM is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from ROM to RAM.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com DATA MEMORY SEGMENT RAM EXTENSION Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S). The data store memory is either addressed directly by a single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address).
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The following examples illustrate the declaration of ECON and the User information. Syntax: [label:] .sect .db econ, conf value ;1 byte, ;configures options .db .endsect ; up to 8 bytes Example: The following sets a value in the ECON register and User Identification for a COP8SGR728M7.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Figure 19. Reset Timing (Power-On Reset Enabled) with VCC Tied to RESET Figure 20. Reset Circuit Using Power-On Reset OSCILLATOR CIRCUITS There are four clock oscillator options available: Crystal Oscillator with or without on-chip bias resistor, R/C Oscillator with on-chip resistor and capacitor, and External Oscillator.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Crystal Oscillator The crystal Oscillator mode can be selected by programming ECON Bit 4 to 1. CKI is the clock input while G7/CKO is the clock generator output to the crystal. An on-chip bias resistor connected between CKI and CKO can be enabled by programming ECON Bit 3 to 1 with the crystal oscillator option selection. The value of the resistor is in the range of 0.5M to 2M (typically 1.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 With On-Chip Bias Resistor Without On-Chip Bias Resistor Figure 21. Crystal Oscillator Figure 22. External Oscillator For operation at lower than maximum R/C oscillator frequency. For operation at maximum R/C oscillator frequency. Figure 23.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The IDLE Timer T0 can generate an interrupt when the twelfth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 2.731 ms at the maximum clock frequency (tC = 0.67 μs). A control flag T0EN allows the interrupt from the twelfth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Figure 24. Timer in PWM Mode In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag. Figure 25 shows a block diagram of the timer in External Event Counter mode.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. The trigger conditions can also be programmed to generate interrupts.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com Mode SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Interrupt B Source Timer Counts On TxC2 TxC1 1 0 1 PWM: TxA Toggle Autoreload RA Autoreload RB tC 1 0 0 PWM: No TxA Toggle Autoreload RA Autoreload RB tC 0 0 0 External Event Counter Timer Underflow Pos. TxB Edge Pos. TxA Edge 0 0 1 External Event Counter Timer Underflow Pos. TxB Edge Pos. TxA Edge 0 1 0 Captures: Pos. TxA Edge Pos.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com On wakeup from G7 or Port L, the devices resume execution from the HALT point. On wakeup from RESET execution will resume from location PC=0 and all RESET conditions apply.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 This toggle condition of the twelfth bit of the IDLE Timer T0 is latched into the T0PND pending flag. The user has the option of being interrupted with a transition on the twelfth bit of the IDLE Timer T0. The interrupt can be enabled or disabled via the T0EN control bit. Setting the T0EN flag enables the interrupt and vice versa.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 USART Each device contains a full-duplex software programmable USART.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA) PEN PSEL1 XBIT9/ PSEL0 CHL1 CHL0 ERR RBFL TBMT Bit 7 Bit 0 PEN: This bit enables/disables Parity (7- and 8-bit modes only). Read/Write, cleared on reset. PEN = 0 Parity disabled. PEN = 1 Parity enabled. PSEL1, PSEL0: Parity select bits. Read/Write, cleared on reset.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 PE: Flags a Parity Error. Read only, cleared on read, cleared on reset. PE = 0 Indicates no Parity Error has been detected since the last time the ENUR register was read. PE = 1 Indicates the occurrence of a Parity Error. SPARE: Reserved for future use. Read/Write, cleared on reset. RBIT9: Contains the ninth data bit received when the USART is operating with nine data bits per frame.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Associated I/O Pins Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to Port L pin L2; it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function of Port L pin L3, requiring no setup. The baud rate clock for the USART can be generated on-chip, or can be taken from an external source.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 The third format for transmission (CHL0 = 0, CHL1 = 1) consists of one Start bit, nine Data bits and 7/8, one or two Stop bits. This format also supports the USART “ATTENTION” feature. When operating in this format, all eight bits of TBUF and RBUF are used for data. The ninth data bit is transmitted and received using two bits in the ENU and ENUR registers, called XBIT9 and RBIT9.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses 0xEC to 0xEF Hex in the program memory space.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Table 5. Baud Rate Divisors (1.8432 MHz Prescaler Output) (1) (1) Baud Rate Baud Rate Divisor − 1 (N-1) 110 (110.03) 1046 134.5 (134.58) 855 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 4800 23 7200 15 9600 11 19200 5 38400 2 The entries in Table 5 assume a prescaler output of 1.8432 MHz. In the asynchronous mode the baud rate could be as high as 987.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Table 6. Prescaler Factors (continued) Prescaler Select Prescaler Factor 11010 13.5 11011 14 11100 14.5 11101 15 11110 15.5 11111 16 As an example, considering Asynchronous Mode and a CKI clock of 4.608 MHz, the prescaler factor selected is: 4.608/1.8432 = 2.5 (1) The 2.5 entry is available in Table 6. The 1.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Effect of HALT/IDLE The USART logic is reinitialized when either the HALT or IDLE modes are entered. This reinitialization sets the TBMT flag and resets all read only bits in the USART control and status registers. Read/Write bits remain unchanged. The Transmit Buffer (TBUF) is not affected, but the Transmit Shift register (TSFT) bits are set to one.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 F2 Comparator1 positive input F1 Comparator1 negative input www.ti.com A Comparator Select Register (CMPSL) is used to enable the comparators, read the outputs of the comparators internally, and enable the outputs of the comparators to the pins. Two control bits (enable and output enable) and one result bit are associated with each comparator.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Figure 34. Interrupt Block Diagram MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The device requires seven instruction cycles to perform the actions listed above. If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com VIS Execution When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Figure 36. VIS Flowchart Programming Example: External Interrupt WAIT: PSW CNTRL RBIT RBIT SBIT SBIT SBIT JP . . . .
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 . . JP INT_EXIT www.ti.com ; Return, set the GIE bit NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs, the associated pending bit is set to 1.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window. Table 9 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error will continue until the clock frequency has reached the minimum specified value, after which the G1 output will go high following 16 tC–32 tC clock cycles.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com DETECTION OF ILLEGAL CONDITIONS The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeroes. The opcode for software interrupt is 00.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 WARNING The SIO register should only be loaded when the SK clock is in the idle phase. Loading the SIO register while the SK clock is in the active phase, will result in undefined data in the SIO register. Setting the BUSY flag when the input SK clock is in the active phase while in the MICROWIRE/PLUS is in the slave mode may cause the current SK clock for the SIO shift register to be narrow.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Table 12. MICROWIRE/PLUS Mode Settings(1) (continued) G4 (SO) Config. Bit G5 (SK) Config. Bit 0 0 G4 Fun. G5 Fun. TRI- Ext. MICROWIRE/PLUS STATE SK Slave Operation The user must set the BUSY flag immediately upon entering the Slave mode. This ensures that all data bits sent by the Master is shifted properly.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Figure 40. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High Figure 41. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Address S/ADD REG 58 www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Instruction Set INTRODUCTION This section defines the instruction set of the COP8 Family members. It contains information about the instruction set features, addressing modes and types. INSTRUCTION FEATURES The strength of the instruction set is based on the following features: • Mostly single-byte opcode instructions minimize program size.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Reg/Data Contents Contents Memory Before After Accumulator XX Hex A6 Hex Memory Location A6 Hex A6 Hex 0005 Hex Register B or X Indirect. The memory address is specified by the contents of the B Register or X register (pointer register). In assembly language, the notation [B] or [X] specifies which register serves as the pointer.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Reg/Data Contents Contents Memory Before After B Pointer 12 Hex 07 Hex Indirect from Program Memory. This is a special case of an indirect instruction that allows access to data tables stored in program memory. In the “Load Accumulator Indirect” (LAID) instruction, the upper and lower bytes of the Program Counter (PCU and PCL) are used temporarily as a pointer to program memory.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Reg www.ti.com Contents Contents Before After PCU 02 Hex 02 Hex PCL 05 Hex 0F Hex Jump Absolute. In this 2-byte instruction, 12 bits of the instruction opcode specify the new contents of the Program Counter. The upper three bits of the Program Counter remain unchanged, restricting the new Program Counter address to the same 4 kbyte address space as the current instruction.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 INSTRUCTION TYPES The instruction set contains a wide variety of instructions. The available instructions are listed below, organized into related groups. Some instructions test a condition and skip the next instruction if the condition is not true. Skipped instructions are executed as no-operation (NOP) instructions.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Logical Instructions The logical instructions perform the operations AND, OR, and XOR (Exclusive OR). Other logical operations can be performed by combining these basic operations. For example, complementing is accomplished by exclusiveORing the Accumulator with FF Hex.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 NOTE The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A > Meml IFBNE # If B Not Equal Do next if lower 4 bits of B ≠ Imm DRSZ Reg Decrement Reg.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com JMPL 3/4 JMP 2/3 JP 1/3 JSRL 3/5 JSR 2/5 JID 1/3 VIS 1/5 RET 1/5 RETSK 1/5 RETI 1/5 INTR 1/7 NOP 1/1 Memory Transfer Instructions Register Direct Immed. Indirect X A, (1) LD A, (1) [B] [X] 1/1 1/3 2/3 1/1 1/3 2/3 2/2 LD B, Imm 1/1 LD B, Imm 2/2 LD Mem, Imm 2/2 3/3 LD Reg, Imm 2/3 IFEQ MD, Imm 3/3 (1) 68 Register Indirect Auto Incr. & Decr.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Table 14.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 www.ti.com Mask Options See Section ECON (CONFIGURATION) REGISTER. COP8 Tools Overview TI is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through TI’s interaction and guidance, these tools cooperate to form a choice of tools that fits each developer's needs.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 PM and adapters for OTP programming.) COP8 Development and OTP Programming Tools • COP8-PM: COP8 Development Programming Module. Windows programming tool for COP8 OTP/Flash Families. Includes 40 DIP programming socket, control software, RS232 cable, and power supply. (Programming adapters are extra.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 SNOS516E – JANUARY 2000 – REVISED APRIL 2013 Aisys DriveWay COP8 DriveWay COP8 OTP Programmers www.ti.
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COP8SGE5, COP8SGE7, COP8SGH5 COP8SGK5, COP8SGR5, COP8SGR7 www.ti.com SNOS516E – JANUARY 2000 – REVISED APRIL 2013 REVISION HISTORY Date October 2001 April 2013 Section Summary of Changes Electrical Characteristics Added spec. for comparator enable time. Changed comparator response time to 600 ns. Comparators Added note regarding comparator enable time. All Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device COP8SGE728M8/63SN Package Package Pins Type Drawing SOIC DW 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.4 3.2 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) COP8SGE728M8/63SN SOIC DW 28 1000 367.0 367.0 45.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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MECHANICAL DATA NNA0044A www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.