Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller NFBGA 491 (17x17) Sitara™ 32-Bit Single-Core 600 MHz

AM3517, AM3505

www.ti.com

SPRS550E –OCTOBER 2009–REVISED MARCH 2013

AM3517/05 Sitara™ ARM Microprocessors

Check for Samples: AM3517, AM3505

1 Device Summary

1.1 Features

123456

– SIDETONE Core Support (McBSP2 and

• AM3517/05 Sitara™ ARM Microprocessor:

3 Only) For Filter, Gain, and Mix

– MPU Subsystem

Operations

• 600-MHz Sitara™ ARM

Cortex™-A8 Core

– 128-Channel Transmit/Receive Mode

• NEON

SIMD Coprocessor and Vector

– Direct Interface to I2S and PCM Device

floating point (FP) co-processor

and TDM Buses

– Memory Interfaces:

• HDQ/1-Wire Interface

• 166 MHz 16/32- bit mDDR/DDR2 Interface

• 4 UARTs (One with Infrared Data

with 1 GByte total addressable space

Association [IrDA] and Consumer Infrared

• Up to 83 MHz General Purpose Memory

[CIR] Modes)

Interface supporting 16-bit Wide

• 3 Master/Slave High-Speed Inter-

Multiplexed Address/Data bus

Integrated Circuit (I2C) Controllers

• 64 K-Byte SRAM

• 12 32-bit General Purpose Timers

• 3 Removable Media Interfaces

• 1 32-bit Watchdog Timer

[MMC/SD/SDIO]

• 1 32-bit 32-kHz Sync Timer

– IO Voltage:

• Up to 186 General-Purpose I/O (GPIO)

• mDDR/DDR2 IOs: 1.8V

Pins

• Other IOs: 1.8V and 3.3V

• Display subsystem

– Core Voltage: 1.2V

– Parallel Digital Output

– Commercial and Extended Temperature

– Up to 24-Bit RGB

Grade

– Supports Up to 2 LCD Panels

(operating restrictions apply)

– Support for Remote Frame Buffer Interface

– 16-bit Video Input Port capable of capturing

(RFBI) LCD Panels

HD video

– Two 10-bit Digital-to-Analog Converters

– HD resolution Display Subsystem

(DACs) Supporting

– Serial Communication

• Composite NTSC/PAL Video

• High-End CAN Controller

• Luma/Chroma Separate Video (S-Video)

• 10/100 Mbit Ethernet MAC

– Rotation 90, 180, and 270 degrees

• USB OTG subsystem with standard

– Resize Images From 1/4x to 8x

DP/DM interface [HS/FS/LS]

– Color Space Converter

• Multiport USB Host Subsystem

[HS/FS/LS] – 8-bit Alpha Blending

– 12-pin ULPI or 6/4/3-pin Serial • Video Processing Front End (VPFE) 16-bit

Interface Video Input Port

• Four Master/Slave Multichannel Serial – RAW Data Interface

Port Interface (McSPI) Ports

– 75-MHz Maximum Pixel Clock

• Five Multichannel Buffered Serial Ports

– Supports REC656/CCIR656 Standard

– 512-Byte Transmit/Receive Buffer

– Supports YCbCr422 Format (8-bit or 16-bit

(McBSP1/3/4/5)

With Discrete Horizontal and Vertical Sync

– 5K-Byte Transmit/Receive Buffer Signals)

(McBSP2)

– Generates Optical Black Clamping Signals

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerVR SGX is a trademark of Imagination Technologies Ltd.

3Sitara is a trademark of Texas Instruments.

4Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.

5ARM, Jazelle are registered trademarks of ARM Ltd or its subsidiaries.

6All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (222 pages)

PAGE 1
AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 AM3517/05 Sitara™ ARM Microprocessors Check for Samples: AM3517, AM3505 1 Device Summary 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 • • • • – Built-in Digital Clamping and Black Level Compensation – 10-bit to 8-bit A-law Compression Hardware – Supports up to 16K Pixels (Image Size) in Horizontal and Vertical Directions System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority) Comprehensive Power, Reset and Clock Management ARM Cortex™-A8 Memory Architecture – ARMv7 Architecture – In-Order, Dual-Issue, Superscalar Microprocessor Core – AR
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AM3517, AM3505 www.ti.com 1.3 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Description AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN, EMAC, and USB OTG PHY that are well suited for industrial apllications.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the AM3517/05 Sitara ARM Microprocessor.
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AM3517, AM3505 www.ti.com 1.5 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 ZCN and ZER Package Differences Table 1-1 shows the ZER and ZCN package differences on the device. Table 1-1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com ........................................ 1 ............................................. 1 1.2 Applications .......................................... 2 1.3 Description ........................................... 3 1.4 Functional Block Diagram ........................... 4 1.5 ZCN and ZER Package Differences ................. 5 Revision History .............................................. 7 2 Terminal Description ....................
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history table highlights the technical changes made from the previous to the current revision. SEE Section 2 ADDITIONS/MODIFICATIONS/DELETIONS Pin Assignments: Changed name of pin N22 from NC to VDDS in Figure 2-1, ZCN Pin Map [Quadrant A] Section 2.2 Ball Characteristics: Remove N22 from NC row.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 2 Terminal Description 2.1 2.1.1 Pin Assignments Pin Map (Top View) The following illustrations show the top views of the 484-pin [ZER] and 491-pin [ZCN] package pin assignments in four quadrants (A, B, C, and D). Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected.
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AM3517, AM3505 www.ti.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 13 12 www.ti.
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AM3517, AM3505 www.ti.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 L K J 13 12 11 VSS VSS VSS VSS VSS www.ti.
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AM3517, AM3505 www.ti.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 M 22 VSS N www.ti.
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AM3517, AM3505 www.ti.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.
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AM3517, AM3505 www.ti.com 2.2 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Ball Characteristics Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for the ZCN/ZER packages. The following list describes the table column headers. 1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0).
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. Table 2-1. Ball Characteristics (ZCN Pkg.) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] D8 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E13 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A14 sdrc_ncs1 0 O L Z 0 VDDS 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] sys_ ndmareq2 1 I gpio_42 4 IO safe_mode 7 gpmc_a10 0 O sys_ ndmareq3 1 I H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] M1 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ ndmareq2 1 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] AD23 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_68 4 IO safe_mode 7 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] Y25 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_83 4 IO safe_mode 7 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] AD1 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] AD6 Y7 AA7 AB7 AC7 AD7 AE7 AD8 AE8 D25 C25 B25 D24 AA9 PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode rmii_mdio_cl 0 k 7 O H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] AB9 AC9 AD9 AE9 AA10 AB10 AC10 AD10 AE10 AD11 AE11 AB12 AC12 AD12 26 PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 mmc1_cmd gpio_121 0 IO L PD 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] V3 PIN NAME [2] MODE [3] safe_mode 7 hecc1_ rxd 0 TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] I H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] mm_fsusb2_t 5 xdat AD16 AC16 AB16 AA16 AE17 TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] AA3 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_5 4 IO sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Z Z 0 VDDSHV 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-1. Ball Characteristics (ZCN Pkg.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-1. Ball Characteristics (ZCN Pkg.) (continued) BALL LOCATION [1] MODE [3] TYPE [4] Y16, Y15, VDDSHV Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, T7, T6, R7, R6, P20, P19, N19, N7, N6, M7, M6, M5, L19, K19, K7, K6, K5, J7, H18, H17 0 PWR 1.8V/3.3V Y9, W18, VDDS U20, R5, N22, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13, F11, F10, F8 0 PWR 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] E3 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D3 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C3 sdrc_d2 0 IO L Z 0 VDDS 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] K3 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS sdrc_cke0 sdrc_cke0_s 7 afe I K1 sdrc_nras 0 O L Z 0 VDDS 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] W10 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_44 4 IO gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] gpmc_nbe0_ 0 cle O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_60 4 IO gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] T22 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] W15 W13 AA13 MODE [3] TYPE [4] mcbsp3_clkx 2 IO gpio_162 4 IO uart3_cts_rct 0 x IO gpio_163 4 IO uart3_rts_sd 0 O gpio_164 IO 4 BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] H PU 7 VDDSHV 1.8V/3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] AA19 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_5 4 IO sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Z Z 0 VDDSHV 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13] F20 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 L PU 4 VDDSHV 1.8V/3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-2. Ball Characteristics (ZER Pkg.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-2. Ball Characteristics (ZER Pkg.) (continued) BALL PIN NAME LOCATION [2] [1] MODE [3] TYPE [4] A21, B1, E15, E17, F12, F14, F18, G10, G12, G13, G8, G17, H18, J17, L22, N16, P17, R16, R18, T9, T11, T13, T17, U8, U10, U12, U14, U16, U18, V7, V8, V17, AA22, AB11 0 PWR 1.8V/3.3V F5, F16, VDDS G15, H5, K7, L6, L16, N1, N5, N6, P5, R6, T5, T7, T15, U6, AA1 0 PWR 1.8V L5 VREFSSTL 0 I .5 * VDDS G9 VDDSOSC O PWR 1.
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AM3517, AM3505 www.ti.com 2.3 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Multiplexing Characteristics Table 2-3 provides descriptions of the AM3517/05 pin multiplexing on the ZCN and ZER packages. Table 2-3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-3.
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AM3517, AM3505 www.ti.com 2.4 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Signal Description Many signals are available on multiple pins according to the software configuration of the pin multiplexing options. 1. SIGNAL NAME: The signal name 2. DESCRIPTION: Description of the signal 3. TYPE: Type = Ball type for this specific function: – I = Input – O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog 4. BALL: Associated ball location 5.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-4. External Memory Interfaces - GPMC Signals Description (continued) SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] ZCN BALL[4] ZER BALL[4] gpmc_nadv_ale Address Valid or Address Latch Enable O R1 AA14 gpmc_noe Output Enable O R2 AB14 gpmc_nwe Write Enable O R3 AA15 gpmc_nbe0_cle Lower Byte Enable.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-5.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-5. External Memory Interfaces - SDRC Signals Description (continued) SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] sdrc_dqs1n Data Strobe 1 IO A17 H1 sdrc_dqs2p Data Strobe 2 IO A6 U1 sdrc_dqs2n Data Strobe 2 IO B6 U2 sdrc_dqs3p Data Strobe 3 IO A2 Y1 sdrc_dqs3n Data Strobe 3 IO B2 Y2 ddr_padref Impedance control for DDR2 output.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-7.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-8.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-13. Serial Communication Interfaces - I2C Signals Description (I2C3) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] i2c3_scl I2C Master Serial clock. Output is open drain. IOD W4 W16 i2c3_sda I2C Serial Bidirectional Data. Output is open drain. IOD W5 W17 Table 2-14.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-15.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-17.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-19. Serial Communication Interfaces – USB Signals Description (continued) SIGNAL NAME [1] DESCRIPTION [2] ZCN BALL [4] ZER BALL [4] usb0_vbus For host or device mode A operation, tie the VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-19.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-19.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-20.
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AM3517, AM3505 www.ti.com 2.4.5 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Test Interfaces Table 2-21.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-23. Test Interfaces – HWDBG Signals Description (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] hw_dbg13 Debug signal 13 O AD22,AB20 E20 hw_dbg14 Debug signal 14 O AB25,AE21 E18 hw_dbg15 Debug signal 15 O AA23,AD21 D20 hw_dbg16 Debug signal 16 O AA24,AC21 D19 hw_dbg17 Debug signal 17 O AA25,AE22 D18 2.4.6 Miscellaneous Table 2-24.
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AM3517, AM3505 www.ti.com 2.4.7 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 General-Purpose IOs Table 2-25.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-25.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-25.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 2-25.
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AM3517, AM3505 www.ti.com 2.4.8 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 System and Miscellaneous Terminals Table 2-26. System and Miscellaneous Signals Description SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] sys_32k 32-kHz clock input I K24 A8 sys_xtalin Main input clock.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 2.4.9 www.ti.com Power Supplies Table 2-27. Power Supplies Description BALL (ZCN Pkg.) [4] BALL (ZER Pkg.) [4] 1.2-V core and oscillator macros power supply.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 2-27. Power Supplies Description (continued) SIGNAL NAME[1] DESCRIPTION[2] BALL (ZCN Pkg.) [4] BALL (ZER Pkg.) [4] 1.8/3.3-V power supply.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 3 Electrical Characteristics 3.1 Absolute Maximum Ratings The following table specifies the absolute maximum ratings over the operating junction temperature range of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 The supply voltages and power consumption estimates are detailed in Table 3-2. Table 3-2. Estimated Power Consumption at Ball Level SIGNAL NAME MAX CURRENT (mA) DESCRIPTION VDD_CORE 1.2-V core and oscillator macros power supply AM3517 1500 mA VDDS_SRAM_MPU 1.8-V MPU SLDO analog power supply AM3505 1400 mA 40 mA VDDS_SRAM_CORE_BG 1.8-V Core SLDO and VDDA of BandGap analog power supply 40 mA VDDS_DPLL_MPU_USBHOST 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 3.2 www.ti.com Recommended Operating Conditions All AM3517/05 modules are used under the operating conditions contained in Table 3-3. Note: Logic functions and parameter values are not assured if the device is operated out of the range specified in the recommended operating conditions. Table 3-3. Recommended Operating Conditions PARAMETER DESCRIPTION MIN NOM MAX UNIT VDD_CORE Core and oscillator macros power supply 1.152 1.20 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 The following diagram illustrates the power domains: vdds_dpll_mpu_usbhost DLL/DCDL BandGap vdds BCK MEM LDO in 1.8 V out 1.2 V VDDS vddshv VDDSHV LDO3 1.0 V/1.2 V MPU DPLL_MPU LDO in 1.8 V out 1.2 V vdd_core Core DPLL_CORE SRAM 1 LDO 0 V/1.0 V/1.2 V SRAM1 ARRAY LDO tv_ref HSDIVIDER (for capacitor) vdds_dpll_per_core SRAM 2 LDO 0 V/1.0 V/1.2 V vdda_dac SRAM2 ARRAY cap_vdd_sram_core Dual Video DAC LDO in 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 3.3 www.ti.com DC Electrical Characteristics Table 3-4 summarizes the dc electrical characteristics. Table 3-4. DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT LVCMOS Pin Buffers VIH High-level input voltage VIL VDDSHV = 1.8 V Low-level input voltage VOH High-level output voltage VOL Low-level output voltage II Input current for dual voltage IO pins (1) 0.65 x VDDSHV. VDDSHV = 3.3 V(1) 2 sys_xtalin 0.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 3-4. DC Electrical Characteristics (continued) PARAMETER VOL Low-level output voltage MIN NOM MAX UNIT Low/Full speed 0.0 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 3.4 www.ti.com Core Voltage Decoupling For module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device because this minimizes the inductance of the circuit board wiring and interconnects. Table 3-5 summarizes the power supplies decoupling characteristics. Table 3-5.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 The following illustrates an example of power supply decoupling.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 3.5 www.ti.com Power-up and Power-down This section provides the timing requirements for the AM3517/05 hardware signals. 3.5.1 Power-up Sequence The following steps give an example of power-up sequence supported by the AM3517/05. 1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillator supply (VDDSOSC) should come up first to a stable state. 2. IO 3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Figure 3-3 shows the power-up sequence. VDDS, VDDS_SRAM_CORE_BG VDDS_SRAM_MPU, VDDSOSC VDDSHV 1.8V 3.3V 1.2V VDD_CORE sys_nrespwron sys_32k sys_xtalin VDDS_DPLL_PER_CORE , VDDS_DPLL_MPU_USBHOST, VDDA_DAC, VDDA1P8V_USBPHY 1.8V 3.3V VDDA3P3V_USBPHY Figure 3-3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 3.5.2 www.ti.com Power-down Sequence The AM3517/05 device proceeds with the power-down sequence shown below. The following steps give an example of the power-down sequence supported by the AM3517/05 device. 1. Reset AM3517/05 device. 2. Stop all signals driven to AM3517/05. 3. Option 1: Power down all domains simutaneously. 4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 4 Clock Specifications The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency (sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks, sys_clkout1 and sys_clkout2. Figure 4-1 shows the interface to the external clock sources and clock outputs.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 0 Sys_32k Sys_32k_in 1 32.5 kHz Fixed Divider /800 Sys_clk= 26 MHz Sys_xtalin Sys_xtalout 0 Latch Sys_boot7 1 JTAG Overrides for DFT 1 Sys_clk PowerOn Reset Figure 4-2. 32-kHz Clock Generation The AM3517/05 outputs externally two clocks: • sys_clkout1 can output the oscillator clock (26 MHz) at any time. • sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 sys_xtalin sys_xtalout VSSOSC Crystal 26 MHz C1 A. B. C2 Oscillator components (Crystal, C1, C2) must be located close to the AM35x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator. The VSSOSC terminal provides a Kelvin ground reference for the external crystal components.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 4-3. 32-kHz Input Clock Source Electrical Characteristics PARAMET ER DESCRIPTION f Frequency, sys_32k Ci Input capacitance Ri MIN TYP MAX UNIT 32.768 Input resistance kHz 0.25 0.45 pF 6 GΩ 10 Table 4-4 details the input requirements of the 32-kHz input clock. Table 4-4.
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AM3517, AM3505 www.ti.com 4.3 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Output Clock Specifications Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available: • sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 4-10 details the sys_clkout2 output clock timing characteristics. Table 4-10. SYS_CLKOUT2 Output Clock Switching Characteristics NAME DESCRIPTION MIN f 1 / CO0 Frequency CO1 tw(CLKOUT2) Pulse duration, sys_clkout2 low or high CO2 tR(CLKOUT2) Rise time, sys_clkout2 (1) CO3 (1) tF(CLKOUT2) Fall time, sys_clkout2 TYP 0.40 * tc(CLKOUT2) MAX UNIT 166 MHz 0.60 * tc(CLKOUT2) ns 3.7 ns 4.
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AM3517, AM3505 www.ti.com 4.4 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 DPLL Specifications The AM3517/05 integrates four DPLLs. The PRM and CM drive them. The four main DPLLs are: • DPLL1 (MPU) • DPLL3 (Core) • DPLL4 (Peripherals) • DPLL5 (Second Peripherals DPLL) Figure 4-6 illustrates the DPLL implementation. Device VDDS_DPLL_MPU_USBHOST Power Rail DPLL1 DPLL3 DPLL4 DPLL5 VDDS_DPLL_PER_CORE 030-016 Figure 4-6. DPLL Implementation 4.4.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 4.4.1.1 www.ti.com DPLL1 (MPU) DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE DPLL) output as a high-frequency bypass input clock. 4.4.1.2 DPLL3 (CORE) DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the emulation trace clock.
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AM3517, AM3505 www.ti.com 4.4.2 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 DPLL Noise Isolation The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the cell to isolate it from substrate noise injection. The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 5 Video DAC Specifications A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the video analog signal. One of the video DACs also includes TV detection and power-down mode.
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AM3517, AM3505 www.ti.com 5.1 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Interface Description Table 5-1 summarizes the external pins of the video DAC. Table 5-1. External Pins of 10-bit Video DAC PIN NAME I/O DESCRIPTION tv_out1 O TV analog output composite DAC1 video output. An external resistor is connected between this node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note that this is the output node that drives the load (75 ).
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 5.2 www.ti.com Electrical Specifications Over Recommended Operating Conditions (TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650Ω , RLOAD = 75Ω , unless otherwise noted) Table 5-2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 (TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 , RLOAD = 75 , unless otherwise noted) Table 5-3. Video DAC Dynamic Electrical Specification PARAMETER (1) fCLK CONDITIONS/ASSUMPTIONS MIN TYP MAX Equal to input clock frequency Clock jitter rms clock jitter required in order to assure 10bit accuracy Attenuation at 5.1 MHz Corner frequency for signal 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 5.3 www.ti.com Analog Supply (vdda_dac) Noise Requirements In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section. The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current divided by the supply variation.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External Component Value Choice). 5.4 External Component Value Choice The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal resistor RSET.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6 Timing Requirements and Switching Characteristics Note: The timing data shown is preliminary data and is subject to change in future revisions. 6.1 Timing Test Conditions All timing requirements and switching characteristics are valid over the recommended operating conditions of Table 3-3, unless otherwise specified. 6.2 6.2.
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AM3517, AM3505 www.ti.com 6.2.4 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Clock Duty Cycle Error The maximum duty cycle error is the difference between the absolute value of the maximum high-level pulse duration or the maximum low-level pulse duration and the typical pulse duration value: • Maximum pulse duration = typical pulse duration + maximum duty cycle error • Minimum pulse duration = typical pulse duration - maximum duty cycle error 6.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.4 www.ti.com External Memory Interfaces The AM3517/05 processor includes the following external memory interfaces: • General-purpose memory controller (GPMC) • SDRAM controller (SDRC) 6.4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX F0 tc(CLK) Cycle time (1), output clock gpmc_clk period 10 F1 tw(CLKH) Typical pulse duration, output clock gpmc_clk high 0.5 P (2) 0.5 P (2) ns F1 tw(CLKL) Typical pulse duration, output clock gpmc_clk low 0.5 P (2) 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued) NO. PARAMETER 1.8V, 3.3V UNIT MIN MAX F8 td(CLKH-nADV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale transition G (9) - 1.9 G (9) + 4.1 ns F9 td(CLKH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_nadv_ale invalid D (8) - 1.9 D (8) + 4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued) NO. PARAMETER 1.8V, 3.3V UNIT MIN MAX F14 td(CLKH-nWE) Delay time, gpmc_clk rising edge to gpmc_nwe transition I (11) - 1.9 I (11) + 4.1 ns F15 td(CLKH-Data) Delay time, gpmc_clk rising edge to data bus transition J (12) - 2.1 J (12) + 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com F1 F1 F0 gpmc_clk F3 F2 F18 gpmc_ncsx F4 gpmc_a[10:1] Valid Address F7 F6 F19 gpmc_nbe0_cle F19 gpmc_nbe1 F6 F8 F8 F20 F9 gpmc_nadv_ale F10 F11 gpmc_noe F13 F12 D0 gpmc_d[15:0] gpmc_waitx F23 gpmc_io_dir OUT F24 IN OUT 030-021 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 F1 F0 F1 gpmc_clk F2 F3 gpmc_ncsx F4 Valid Address gpmc_a[10:1] F6 F7 gpmc_nbe0_cle F7 gpmc_nbe1 F6 F8 F8 F9 gpmc_nadv_ale F10 F11 gpmc_noe F13 F13 F12 D0 gpmc_d[15:0] F21 F12 D1 D2 D3 F22 gpmc_waitx F24 F23 gpmc_io_dir OUT IN OUT 030-022 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_ncsx F4 Valid Address gpmc_a[10:1] F17 F6 F17 F17 gpmc_nbe0_cle F17 F17 F17 gpmc_nbe1 F6 F8 F8 F9 gpmc_nadv_ale F14 F14 gpmc_nwe F15 gpmc_d[15:0] D0 D1 F15 D2 F15 D3 gpmc_waitx gpmc_io_dir OUT 030-023 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 F1 F0 F1 gpmc_clk F3 F2 gpmc_ncsx F7 F6 Valid gpmc_nbe0_cle F6 F7 Valid gpmc_nbe1 F4 Address (MSB) gpmc_a[26:17] F12 F5 F4 gpmc_a[16:1]_d[15:0] Address (LSB) F8 F13 D0 D1 F12 D2 F8 D3 F9 gpmc_nadv_ale F10 F11 gpmc_noe gpmc_waitx F24 F23 gpmc_io_dir OUT IN OUT 030-024 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-5.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_ncsx F4 gpmc_a[26:17] Address (MSB) F17 F6 F17 F17 gpmc_nbe0_cle F17 F17 F17 gpmc_nbe1 F6 F8 F8 F9 gpmc_nadv_ale F14 F14 gpmc_nwe F15 gpmc_d[15:0] Address (LSB) D0 D1 F15 F15 D2 D3 gpmc_waitx OUT gpmc_io_dir 030-025 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write 6.4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1) (2) (continued) NO. PARAMETER 1.8V,3.3V MIN UNIT MAX FI7 Maximum output enable generation delay from internal functional clock 6.5 ns FI8 Maximum write enable generation delay from internal functional clock 6.5 ns FI9 Maximum functional clock skew 100 ps Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode NO.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued) NO. PARAMETER 1.8V/ 3.3V UNIT MIN MAX I(8) – 0.2 I(8) + 2.0 FA18 td(nCSV-nOEIV) Delay time, gpmc_ncsx(13) valid to gpmc_noe invalid (Burst read) FA20 tw(AV) Pulse duration, address valid – 2nd, 3rd, and 4th accesses FA25 td(nCSV-nWEV) Delay time, gpmc_ncsx(13) valid to gpmc_nwe valid E(5) – 0.2 E(5) + 2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 GPMC_FCLK gpmc_clk FA5 FA1 gpmc_ncsx FA9 gpmc_a[10:1] Valid Address FA0 FA10 gpmc_nbe0_cle Valid FA0 gpmc_nbe1 Valid FA10 FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe gpmc_d[15:0] Data IN 0 Data IN 0 gpmc_waitx FA14 gpmc_io_dir FA15 OUT IN OUT 030-026 Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com GPMC_FCLK gpmc_clk FA5 FA5 FA1 FA1 gpmc_ncsx FA16 FA9 FA9 gpmc_a[10:1] Address 0 Address 1 FA0 FA0 FA10 FA10 gpmc_nbe0_cle Valid gpmc_nbe1 Valid FA0 FA0 Valid Valid FA10 FA10 FA3 FA3 FA12 FA12 gpmc_nadv_ale FA4 FA4 FA13 FA13 gpmc_noe gpmc_d[15:0] Data Upper gpmc_waitx FA15 gpmc_io_dir FA14 OUT IN FA14 OUT FA15 IN 030-027 Figure 6-8.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 GPMC_FCLK gpmc_clk FA21 FA20 FA20 FA20 FA1 gpmc_ncsx FA9 Add0 gpmc_a[10:1] Add1 Add2 Add3 D0 D1 D2 Add4 FA0 FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA12 gpmc_nadv_ale FA18 FA13 gpmc_noe gpmc_d[15:0] D3 D3 gpmc_waitx FA15 gpmc_io_dir OUT FA14 IN OUT 030-028 Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1) (2) (3) (4) (1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 Valid Address gpmc_a[10:1] FA0 FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_d[15:0] Data OUT gpmc_waitx gpmc_io_dir OUT 030-029 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-10.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 GPMC_FCLK gpmc_clk FA1 FA5 gpmc_ncsx FA9 gpmc_a[26:17] Address (MSB) FA0 FA10 gpmc_nbe0_cle Valid FA0 FA10 gpmc_nbe1 Valid FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe FA29 gpmc_a[16:1]_d[15:0] FA37 Address (LSB) FA14 gpmc_io_dir Data IN Data IN FA15 OUT IN OUT gpmc_waitx 030-030 Figure 6-11.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 gpmc_a[26:17] Address (MSB) FA0 FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_a[16:1]_d[15:0] FA28 Valid Address (LSB) Data OUT gpmc_waitx gpmc_io_dir OUT 030-031 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing 6.4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters (1) NO. PARAMETER 1.8V, 3.3V MIN GNFI1 Maximum output data generation delay from internal functional clock GNFI2 Maximum input data capture delay by internal functional clock GNFI3 GNFI4 (2) UNIT MAX 6.5 ns 4 ns Maximum device select generation delay from internal functional clock 6.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued) NO. GNF15 PARAMETER tw(nOEIV-nCSIV) 1.8V, 3.3V Delay time, gpmc_noe invalid to gpmc_ncsx(13) invalid UNIT MIN MAX M(12) - 0.2 M(12) + 2.0 ns (1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 GPMC_FCLK GNF1 GNF6 GNF7 GNF8 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 GNF4 gpmc_a[16:1]_d[15:0] Address 030-033 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing GPMC_FCLK GNF12 GNF10 GNF15 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale GNF14 GNF13 gpmc_noe gpmc_a[16:1]_d[15:0] DATA gpmc_waitx 030-034 Figure 6-15.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com GPMC_FCLK GNF1 GNF6 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] GNF4 DATA 030-035 In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1. Figure 6-16.
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AM3517, AM3505 www.ti.com 6.4.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.4.2.1 www.ti.com LPDDR Interface This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.4.2.1.3 PCB Stackup The minimum stackup required for routing the microprocessor is a six layer stack as shown in Table 6-14. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint. Table 6-14.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 X Y OFFSET LPDDR Device Y Y OFFSET LPDDR Controller A1 Microprocessor A1 Recommended LPDDR Device Orientation Figure 6-19. AM3517/05 and LPDDR Device Placement Table 6-16. Placement Specifications NO.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com LPDDR Controller A1 LPDDR Device A1 Region should encompass all LPDDR circuitry and varies depending on placement. Non-LPDDR signals should not be routed on the LPDDR signal layers within the LPDDR keep out region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-19. LPDDR Signal Terminations NO. PARAMETER MIN 1 CK Net Class 0 2 ADDR_CTRL Net Class 0 3 Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3) 0 (1) (2) (3) TYP MAX UNIT NOTES 10 Ω See Note (1) 22 Zo Ω See Notes (1), (2), (3) 22 Zo Ω See Notes (1), (2), (3) Only series termination is permitted, parallel or SST specifically disallowed.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. T E0 T E1 LPDDR Controller A1 Microprocessor T A1 E2 T E3 Figure 6-22. DQS and DQ Routing and Topology Table 6-21. DQS and DQ Routing Specification (1) NO.
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AM3517, AM3505 www.ti.com 6.4.2.2 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 DDR2 Interface This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.4.2.2.3 PCB Stackup The minimum stackup required for routing the AM3517/05 is a six-layer stack as shown in Table 6-23. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint. Table 6-23.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Complete stack up specifications are provided in Table 6-24.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-24. PCB Stack Up Specifications No.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-25. Placement Specifications No. 1 Parameter Min X 2 Y 3 Y Offset 4 DDR2 Keepout Region 5 Clearance from non-DDR2 signal to DDR2 Keepout Region (1) (2) (3) (4) (5) Max Unit 1750 Mils Notes See Notes (1) (2) , 1280 Mils See Notes (1) (2) 650 Mils See Notes (1) (2) 4 w , (3) . See Note (4) See Note (5) , See Figure 6-23 for dimension definitions.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.4.2.2.6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 6-26 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM3517/05and DDR2 interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 6-26. Bulk Bypass Capacitors No.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.4.2.2.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05 DDR2 power, and AM3517/05 DDR2 ground connections. Table 6-27 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. 6.4.2.2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-28. Clock Net Class Definitions Clock Net Class AM3517/05 Device Pin Names CK sdrc_clk/sdrc_nclk DQS0 sdrc_dqs0p /sdrc_dqs0n DQS1 sdrc_dqs1p /sdrc_dqs1n DQS2 sdrc_dqs2p/sdrc_dqs2n DQS3 sdrc_dqs3p/sdrc_dqs3n Table 6-29.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.4.2.2.10 VREF Routing VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the layout guidelines for VREF.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-31.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-32. DQS and Dx Routing Specification (1) No.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-33. SDRC_STRBENx Routing Specification (1) (2) No.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.5 www.ti.com Video Interfaces 6.5.1 Video Processing Subsystem (VPSS) The Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.). 6.5.1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.5.1.1.1 Video Processing Front End (VPFE) Timing The following tables assume testing over recommended operating conditions. Table 6-34. VPFE Timing Requirements NO. 1.8V, 3.3V PARAMETER MIN MAX 13.33 100 UNIT VF1 tc(VDIN_CLK) Cycle time, pixel clock input, VDIN_CLK VF2 tsu(VDIN_D-VDIN_CLK) Setup time, VDIN_D to VDIN_CLK rising edge 3.5 ns ns VF3 tsu(VDIN_HD-VDIN_CLK) Setup time, VDIN_HD to VDIN_CLK rising edge 3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com VDIN_CLK (Falling Edge) VDIN_CLK (Rising Edge) VF15, VF16, VF17 VF12, VF13, VF14 VDIN_HD, VDIN_VD, VDIN_FIELD VF12, VF13, VF14 VF15, VF16, VF17 SPRS550-002 Figure 6-33. VPFE Output Timings VF18 VDIN_HD (Falling Edge) VDIN_HD (Rising Edge) VF19 VF20 VDIN_D[xx] SPRS550-003 Figure 6-34. VPFE Input Timings With VDIN0_HD as Pixel Clock 6.5.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.5.2.1.1 LCD Display in TFT Mode Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35). Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode (1) NO. PARAMETER 1.8V, 3.3V UNIT MIN MAX DL0 td(PCLKA-HSYNCT) Delay time, dss_pclk active edge to dss_hsync transition -4.215 4.215 ns DL1 td(PCLKA-VSYNCT) Delay time, dss_pclk active edge to dss_vsync transition -4.215 4.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.5.2.1.2 LCD Display in STN Mode Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36). Table 6-37. LCD Display Interface Switching Characteristics in STN Mode (1) NO. PARAMETER 1.8V, 3.3V UNIT MIN MAX 6.9 DL3 td(PCLKA-DATAV) Delay time, dss_pclk active edge to dss_data bus valid -4.21 DL4 tc(PCLK) Cycle time (4), dss_pclk 22.73 DL5 tw(PCLK) Pulse duration, dss_pclk low or high 10.
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AM3517, AM3505 www.ti.com 6.6 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Serial Communications Interfaces 6.6.1 Multichannel Buffered Serial Port (McBSP) Timing There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct serial interface between the AM3517/05 device and other devices in a system such as other application devices or codecs.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration (continued) PARAMETER VDDSHV = 1.8V, 3.3V tW(CLKL) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low (1) tdc(CLK) Duty cycle error, mcbsp1_clkr / mcbspx_clkx (1) UNIT 0.5*P (2) 0.5*P (2) ns -0.75 0.75 ns Table 6-40. McBSP3 Output Clock Pulse Duration PARAMETER VDDSHV = 1.8V, 3.3V MIN tC(CLK) Cycle time, mcbsp3_clkx UNIT MAX 31.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode No. B2 PARAMETER VDDSHV=3.3V td(CLKAE-FSV) Delay time, mcbsp1_clkr active edge to mcbsp1_fsr / mcbsp1_fsx valid VDDSHV=1.8V MIN MAX MIN MAX 0.2 14.8 0.2 14.8 UNIT ns Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode No. PARAMETER VDDSHV = 3.3V MIN B5 B6 tsu(FSXVCLKXAE) th(CLKXAEFSXV) MAX VDDSHV = 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode (continued) No. PARAMETER B6 th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbsp1_fsx valid after mcbsp1_clkr / mcbsp1_clkx active edge VDDSHV = 3.3V VDDSHV = 1.8V UNIT Half Cycle Slave 0.5 0.5 ns Full Cycle Slave 1.0 1.0 ns Table 6-46. McBSP1 Switching Characteristics - Falling Edge and Receive Mode No. B2 PARAMETER VDDSHV = 3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.1.1.2 McBSP2 The following tables show the timing requirements and switching characteristics for McBSP2. Table 6-49. McBSP2 Timing Requirements - Rising Edge and Receive Mode No. PARAMETER VDDSHV = 3.3V MIN B3 B4 B5 B6 tsu(DRVCLKXAE) th(CLKXAEDRV) tsu(FSVCLKXAE) th(CLKXAEFSV) Setup time, mcbsp2_dr valid before mcbsp2_clkx active edge MAX VDDSHV = 1.8V MIN UNIT MAX Half Cycle Master 5.0 5.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-52. McBSP2 Switching Characteristics - Rising Edge and Transmit Mode No. PARAMETER B2 td(CLKXAEFSXV) Delay time, mcbsp2_clkx active edge to mcbsp2_fsx valid B8 td(CLKXAEDXV) Delay time, mcbsp2_clkx active edge to mcbsp2_dx valid VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX 0.2 14.8 0.2 14.8 ns Master 0.6 14.8 0.6 14.8 ns Slave 0.6 14.8 0.6 14.8 ns Table 6-53.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode (continued) No. B6 PARAMETER th(CLKXAEFSXV) Hold time, mcbsp2_fsx valid after mcbsp2_clkx active edge VDDSHV = 3.3V VDDSHV = 1.8V UNIT Half Cycle Slave 5.2 5.2 ns Full Cycle Slave 1.0 1.0 ns Table 6-56. McBSP2 Switching Characteristics - Falling Edge and Transmit Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode No. B2 PARAMETER td(CLKXAEFSXV) VDDSHV = 3.3V Delay time, mcbsp3_clkx active edge to mcbsp3_fsx valid VDDSHV = 1.8V MIN MAX MIN MAX 0.2 22.2 0.2 22.2 UNIT ns Table 6-59. McBSP3 (Set #1) Timing Requirements - Rising Edge and Transmit Mode No. PARAMETER VDDSHV = 3.3V MIN B5 B6 tsu(FSXVCLKXAE) th(CLKXAEFSXV) MAX VDDSHV = 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-62. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Receive Mode No. B2 PARAMETER td(CLKXAEFSXV) VDDSHV = 3.3V Delay time, mcbsp3_clkx active edge to mcbsp3_fsx valid VDDSHV = 1.8V MIN MAX MIN MAX 0.2 22.2 0.2 22.2 UNIT ns Table 6-63. McBSP3 (Set #1) Timing Requirements - Falling Edge and Transmit Mode No. PARAMETER VDDSHV = 3.3V MIN B5 B6 tsu(FSXVCLKXAE) th(CLKXAEFSXV) MAX VDDSHV = 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode (continued) No. B5 B6 PARAMETER tsu(FSVCLKXAE) th(CLKXAEFSV) VDDSHV = 3.3V VDDSHV = 1.8V UNIT Setup time, mcbsp3_fsx valid before mcbsp3_clkx active edge Half Cycle Slave 5.2 5.2 ns Full Cycle Slave 4.2 4.2 ns Hold time, mcbsp3_fsx valid after mcbsp3_clkx active edge Half Cycle Slave 5.2 5.2 ns Full Cycle Slave 1.0 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode (continued) No. B4 B5 B6 PARAMETER th(CLKXAEDRV) tsu(FXSVCLKXAE) th(CLKXAEFSXV) Hold time, mcbsp3_dr valid after mcbsp3_clkx active edge VDDSHV = 3.3V VDDSHV = 1.8V UNIT Half Cycle Master 5.8 5.8 ns Half Cycle Slave 5.2 5.2 ns Full Cycle Master 1.5 1.5 ns Full Cycle Slave 0.9 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode (continued) No. B3 B4 B5 B6 PARAMETER tsu(DRVCLKXAE) th(CLKXAEDRV) tsu(FSVCLKXAE) th(CLKXAEFSV) Setup time, mcbsp4_dr valid before mcbsp4_clkx active edge VDDSHV = 3.3V VDDSHV = 1.8V UNIT Half Cycle Master 7.5 7.5 ns Half Cycle Slave 7.7 7.7 ns Full Cycle Master 3.2 3.2 ns Full Cycle Slave 4.2 4.2 ns Half Cycle Master 7.7 7.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode (continued) No. B8 PARAMETER td(CLKXAEDXV) Delay time, mcbsp4_clkx active edge to mcbsp4_dx valid VDDSHV = 3.3V VDDSHV = 1.8V UNIT Master 0.6 16.6 0.6 16.6 ns Slave 0.6 17.3 0.6 17.3 ns Table 6-77. McBSP4 Timing Requirements - Falling Edge and Receive Mode No. PARAMETER VDDSHV = 3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-80. McBSP4 Switching Characteristics - Falling Edge and Transmit Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V MIN MAX MIN MAX UNIT B2 td(CLKXAEFSXV) Delay time, mcbsp4_clkx active edge to mcbsp4_fsx valid 0.2 16.6 0.2 16.6 ns B8 td(CLKXAEDXV) Delay time, mcbsp4_clkx active edge to mcbsp4_dx valid Master 0.6 16.6 0.6 16.6 ns Slave 0.6 17.3 0.6 17.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.1.1.5 McBSP5 The following tables show the timing conditions and switching characteristics for McBSP5. Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode No. PARAMETER VDDSHV = 3.3V MIN B3 B4 B5 B6 tsu(DRVCLKXAE) th(CLKXAEDRV) tsu(FSVCLKXAE) th(CLKXAEFSV) Setup time, mcbsp5_dr valid before mcbsp5_clkx active edge MAX VDDSHV = 1.8V MIN UNIT MAX Half Cycle Master 7.5 7.5 ns Half Cycle Slave 7.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode (continued) No. B8 PARAMETER td(CLKXAEDXV) Delay time, mcbsp5_clkx active edge to mcbsp5_dx valid VDDSHV = 3.3V VDDSHV = 1.8V UNIT Master 0.6 14.8 0.6 14.8 ns Slave 0.6 14.8 0.6 14.8 ns Table 6-85. McBSP5 Timing Requirements - Falling Edge and Receive Mode No. PARAMETER VDDSHV = 3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-88. McBSP5 Switching Characteristics - Falling Edge and Transmit Mode No. PARAMETER B2 td(CLKXAEFSXV) Delay time, mcbsp5_clkx active edge to mcbsp5_fsx valid B8 td(CLKXAEDXV) Delay time, mcbsp5_clkx active edge to mcbsp5_dx valid VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX 0.2 22.2 0.2 22.2 ns Master 0.6 22.2 0.6 22.2 ns Slave 0.6 22.2 0.6 22.2 ns 6.6.1.1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.6.1.1.7 McBSP Timing Diagrams mcbspx_clkr B2 B2 mcbspx_fsr B3 mcbspx_dr B4 D7 D5 D6 030-068 Figure 6-37. McBSP Rising Edge Receive Timing in Master Mode mcbspx_clkr B5 B6 mcbspx_fsr B3 mcbspx_dr B4 D7 D6 D5 030-069 Figure 6-38. McBSP Rising Edge Receive Timing in Slave Mode mcbspx_clkx B2 B2 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-070 Figure 6-39.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 mcbspx_clkr B5 B6 mcbspx_fsr B3 mcbspx_dr B4 D7 D6 D5 030-073 Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode mcbspx_clkx B2 B2 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-074 Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode mcbspx_clkx B5 B6 mcbspx_fsx B8 mcbspx_dx D7 D6 D5 030-075 Figure 6-44.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.2 www.ti.com Multichannel Serial Port Interface (McSPI) Timing The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and any channel (n). 6.6.2.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-95. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode (1) NO. PARAMETER 1.8 V MIN SM0 tc(CLK) Cycle time, mcspix_clk 20.83 tj(CLK) Cycle jitter (4), mcspix_clk -200 SM1 tw(CLK) Pulse duration, mcspix_clk high or low 0.45P SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo shifted -2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-97. McSPI3 Interface Switching Characteristics – Master Mode (1) NO. PARAMETER 1.8 V MIN SM0 tc(CLK) Cycle time, mcspix_clk 41.67 tj(CLK) Cycle jitter (4) -200 (5) (2) (3) 3.3 V MAX MIN UNIT MAX 41.67 200 (5) tw(CLK) Pulse duration, mcspix_clk high or low 0.45P td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo shifted -2.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 mcspix_csn(EPOL=1) www.ti.
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AM3517, AM3505 www.ti.com 6.6.3 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Multiport Full-Speed Universal Serial Bus (USB) Interface The AM3517/05 microprocessor provides three USB ports working in full- and low-speed data transactions (up to 12Mbit/s). Connected to either a serial link controller or a serial PHY (PHY interface modes) it supports: • 6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode • 4-pin bidirectional mode • 3-pin bidirectional mode 6.6.3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Transmit mmx_txen_n FSU5 Receive FSU8 mmx_txdat FSU6 FSU7 FSU9 mmx_txse0 FSU1 FSU2 FSU1 FSU2 FSU3 FSU4 mmx_rxdp mmx_rxdm mmx_rxrcv 030-080 In mmx, x is equal to 0, 1, or 2. Figure 6-47. Low-/Full-Speed USB Unidirectional Standard 6-pin Mode 6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode The following tables assume testing over the recommended operating conditions.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode (continued) NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX tF(txen) Fall time, mmx_txen_n 4.0 ns tR(dat) Rise time, mmx_txdat 4.0 ns tF(dat) Fall time, mmx_txdat 4.0 ns tR(se0) Rise time, mmx_txse0 4.0 ns tF(se0) Fall time, mmx_txse0 4.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode (continued) NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX FSU24 td(DATI-TXENH) Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 FSU25 td(SE0I-TXENH) Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 tR(do) Rise time, mmx_txen_n 4.0 ns tF(do) Fall time, mmx_txen_n 4.0 ns tR(do) Rise time, mmx_txdat 4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1) (continued) NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX th(CLKH-NXT/IV) Hold time, hsusbx_nxt valid after hsusbx_clk rising edge 0.2 ns HSU5 ts(DATAV-CLKH) Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 7.5 ns HSU6 th(CLKH-DATIV) Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns Table 6-109.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.5 www.ti.com USB0 OTG (USB2.0 OTG) The AM3517/05 USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.
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AM3517, AM3505 www.ti.com 6.6.6 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 High-End Controller Area Network Controller (HECC) Timing The AM3517/05 device has a High-End Controller Area Network Controller (HECC). The HECC uses established protocol to communicate serially with other controllers in harsh environments. The HECC is fully compliant with the Controller Area Network (CAN) protocol, version 2.0B. Key features of the HECC include the following: • CAN, version 2.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.7 www.ti.com Ethernet Media Access Controller (EMAC) The Ethernet Media Access Controller (EMAC) provides an efficient interface between the AM3517/05 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The EMAC controls the flow of packet data from the AM3517/05 device to the PHY.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 1 2 3 REF_CLK 5 5 TXEN 4 TXD[1:0] 6 7 RXD[1:0] 8 9 CRS_DV 10 11 RXER_IN SPRS550-004 Figure 6-52.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.8 www.ti.com Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-117. Timing Requirements for UARTx Receive (1) 1.8V, 3.3V NO. (1) MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (RXDn) .96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit .96U 1.05U ns U = UART baud time = 1/programmed baud rate. Table 6-118. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1) NO. 1.8V, 3.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Pulse duration 90% 90% 50% 50% 10% 10% tr tf 030-118 Figure 6-56. UART IrDA Pulse Parameters 6.6.9.1.1 IrDA—Receive Mode Table 6-119. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION MIN NOMINAL MAX UNIT SIR 2.4 Kbit/s 1.41 78.1 88.55 μs 9.6 Kbit/s 1.41 19.5 22.13 μs 19.2 Kbit/s 1.41 9.75 11.07 μs 38.4 Kbit/s 1.41 4.87 5.96 μs 57.6 Kbit/s 1.41 3.25 4.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 6.6.9.1.2 IrDA—Transmit Mode Table 6-121. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode SIGNALING RATE ELECTRICAL PULSE DURATION MIN NOMINAL UNIT MAX SIR 2.4 Kbit/s 78.1 78.1 78.1 μs 9.6 Kbit/s 19.5 19.5 19.5 μs 19.2 Kbit/s 9.75 9.75 9.75 μs 38.4 Kbit/s 4.87 4.87 4.87 μs 57.6 Kbit/s 3.25 3.25 3.25 μs 115.2 Kbit/s 1.62 1.62 1.62 μs 0.576 Mbit/s 414 416 419 ns 1.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com tCYCH tHW0 tHW1 HDQ 030-096 Figure 6-58. HDQ Read Bit Timing (Data) tCYCD tDW0 tDW1 HDQ 030-097 Figure 6-59. HDQ Write Bit Timing (Command/Address or Data) Command _byte_written Data_byte_received 0_(LSB ) Break 1 tRSPS 6 1 7_(MSB) 0_(LSB) 6 HDQ 030-098 Figure 6-60. HDQ Communication Timing 6.6.10.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 tSLOT_and_ tREC tRDV_and_ tREL 1-WIRE tLOWR 030-100 Figure 6-62. 1-Wire Read Bit Timing (Data) tSLOT_and_tREC tLOW0 1-WIRE tLOW1 030-101 Figure 6-63.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.6.11 I2C Interface The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus. The I2C controller supports the multimaster mode which allows more than one device capable of controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can operate as either transmitter or receiver, according to the function of the device.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 START REPEAT START START STOP i2cX_sda I2 I6 I5 I1 I3 I4 I8 I6 I7 i2cX_scl 030-093 2 Figure 6-64.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com 6.6.11.2 I2C High-Speed Mode Table 6-127. I2C High-Speed Mode Timings (1) (2) 1.8V, 3.3V NO. PARAMETER UNIT MIN I1 fSCL Clock frequency, i2cX_scl tw(SCLH) Pulse duration, i2cX_scl high MAX 3.
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AM3517, AM3505 www.ti.com 6.7 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Removable Media Interfaces 6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory cards, or SDIO cards. The application interface is responsible for managing transaction semantics.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2) NO. PARAMETER tsu(CLKIH-CMDIV) (continued) 1.8V, 3.3V MIN HSSD4/SD4 (3)(4) UNIT MAX Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 1249.2 ns MMC/SD/SDIO Interface 3 HSSD3/SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 1198.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-133. Y Parameter CLKD Y 1 or Even 0.5 Odd (trunc[CLKD/2])/CLKD 6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-134. MMC/SD/SDIO Timing Conditions High-Speed MMC Mode TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT MIN MAX High-Speed MMC Mode Input Conditions tr Input signal rise time 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-136. MMC/SD/SDIO Switching Characteristics High-Speed MMC Mode (1) (2) N O. PARAMETER 1.8V, 3.3V MIN UNIT MAX High-Speed MMC Mode MMC1 tc(clk) Cycle time, output clk period 20.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0). 6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-139.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-140. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification Mode (1) (2) (3) NO. PARAMETER 1.8 V MIN 3.3V MAX MIN UNIT MAX Standard MMC Mode and MMC Identification Mode MMC/SD/SDIO Interface 1 MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 2.13 2.41 ns MMC4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 3.47 2.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification Mode(1)(2) (continued) NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX tdc(clk) Duty cycle error, output clk 2604.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0). MMC1 MMC2 mmcx_clk MMC3 MMC4 mmcx_cmd MMC7 MMC8 mmcx_dat[3:0] 030-104 In mmcx, x is equal to 1, 2, or 3. Figure 6-66. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive MMC1 MMC2 mmcx_clk MMC5 MMC5 mmcx_cmd MMC6 MMC6 mmcx_dat[3:0] 030-105 In mmcx, x is equal to 1, 2, or 3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3) (continued) NO. PARAMETER 1.8V, 3.3V MIN UNIT MAX HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 5.61 ns HSSD8 th(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.28 ns MMC/SD/SDIO Interface 2 HSSD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2) (continued) NO. PARAMETER 1.8 V, 3.3 V UNIT MIN MAX HSSD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to mmc2_cmd transition 3.72 14.11 ns HSSD6 td(CLKOH-DATx) Delay time, mmc2_clk rising clock edge to mmc2_datx transition 3.72 14.
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AM3517, AM3505 www.ti.com 6.7.1.5 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 MMC/SD/SDIO in Standard SD Mode The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-149. MMC/SD/SDIO Timing Conditions Standard SD Mode TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT MIN MAX Standard SD Mode Input Conditions tR Input signal rise time 0.19 10 ns tF Input signal fall time 0.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-150. MMC/SD/SDIO Timing Requirements Standard SD Mode (1) (2) (3) NO. PARAMETER 1.8 V, 3.3V MIN UNIT MAX Standard SD Mode MMC/SD/SDIO Interface 1 SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 6.23 ns SD4 th(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 19.37 ns SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk rising clock edge 6.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2) (continued) NO. PARAMETER 1.8V, 3.3V UNIT MIN MAX SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd transition 6.13 35.53 ns SD6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to mmc1_datx transition 6.13 35.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com SD1 SD2 mmcx_clk SD5 SD5 mmcx_cmd SD6 SD6 mmcx_dat[3:0] 030-109 In mmcx, x is equal to 1, 2, or 3. Figure 6-71.
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AM3517, AM3505 www.ti.com 6.8 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Test Interfaces The emulation and trace interfaces allow tracing activities of the following CPUs: • ARM CortexTM-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time trace of the ARM subsystem operations. All processors can be emulated via JTAG ports. 6.8.1 Embedded Trace Macro Interface (ETM) The following tables assume testing over the recommended operating conditions. Table 6-154.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-156. JTAG Timing Requirements Free Running Clock Mode (1) (2) (3) NO. PARAMETER 1.8V MIN 3.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 JT4 JT5 JT6 jtag_tck JT1 JT2 JT3 jtag_rtck JT7 JT8 JT9 JT10 jtag_tdi jtag_tms JT12 JT13 jtag_emux(IN) JT11 jtag_tdo JT14 jtag_emux(OUT) 030-113 In jtag_emux, x is equal to 0 to 1. Figure 6-73. JTAG Interface Timing Free Running Clock Mode 6.8.2.2 JTAG Adaptive Clock Mode The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-158.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode (1) 1.
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AM3517, AM3505 www.ti.com SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 7 Package Characteristics 7.1 Package Thermal Resistance Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the AM3517/05. Table 7-1. AM3517/05 Thermal Resistance Characteristics (1) PACKAGE POWER (W) RJA(C/W) RJB(C/W) RJC(C/W) BOARD TYPE Figure 6-31 ZCN Pkg. 1.6 24.58 10.81 - 2S2P ZER Pkg. 1.6 15.
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AM3517, AM3505 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 www.ti.com X AM3517 A ZCN PREFIX X = Experimental Device P = Prototype Device blank = Production Device ( ) ( ) blank = no security C = crypto enabled blank = commercial temperature A = extended temperature PACKAGE TYPE ZCN = 491-pin sPBGA ZER = 484-pin sPBGA DEVICE SILICON REVISION Figure 7-1. Device Nomenclature 7.2.2 Documentation Support 7.2.2.
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AM3517, AM3505 www.ti.com 7.3 SPRS550E – OCTOBER 2009 – REVISED MARCH 2013 Mechanical Data The following packaging information reflects the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2013 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.