AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 AM335x ARM® Cortex™-A8 Microprocessors (MPUs) Check for Samples: AM3359, AM3358 1 Device Summary 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 PRODUCT PREVIEW – Error Locator Module (ELM) • Used in Conjunction with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm • Supports 4-Bit, 8-Bit, and 16-Bit per 512byte Block Error Location Based on BCH Algorithms • Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) – Supports protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/I
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 (TPTC) and One Third-Party Channel Controller (TPCC), Which Supports Up to 64 Programmable Logical Channels and Eight QDMA Channels.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 1.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Description The AM335x microprocessors, based on the ARM Cortex-A8, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 1.4 www.ti.com Functional Block Diagram The AM335x microprocessor functional block diagram is shown in Figure 1-1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Device Summary 1.1 3.5 Features Touchscreen Controller and Analog-to-Digital Subsystem Electrical Parameters .................. 94 4 Power and Clocking ................................... 96 5 ..................................... 96 ............................... 103 Peripheral Information and Timings ............. 112 5.1 5.2 Parameter Information ............................
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (May 2012) to Revision E • • • • • • • • • • PRODUCT PREVIEW • • • • • • • • • • • • • • • • • • • • • • • • • • • 8 Page Changed ARM speeds features list item ..........................................................................................
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 • • • • • • • • • • • • • • • • • • • • • • • • SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Changed Figure 4-12, OSC1 (ZCZ Package) Crystal Circuit Schematic .................................................. Changed Figure 4-14, OSC1 (ZCE Package) LVCMOS Circuit Schematic ............................................... Changed Figure 4-15, OSC1 (ZCZ Package) LVCMOS Circuit Schematic ...............................................
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 2 Terminal Description 2.1 Pin Assignments NOTE The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. 2.1.1 ZCE Package Pin Maps (Top View) The pin maps below show the pin assignments on the ZCE package in three sections (left, middle, and right).
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-2.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.1.2 www.ti.com ZCZ Package Pin Maps (Top View) The pin maps below show the pin assignments on the ZCZ package in three sections (left, middle, and right).
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-5.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.2 www.ti.com Ball Characteristics The AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73) and this document may reference internal signal names when discussing peripheral input and output signals since many of the AM335x package terminals can be multiplexed to one of several peripheral signals.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 9. POWER: The voltage supply that powers the terminal’s IO buffers. 10. HYS: Indicates if the input buffer is with hysteresis. 11. BUFFER STRENGTH: Drive strength of the associated output buffer. 12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. 13. IO CELL: IO cell information.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) PIN NAME [2] SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) D14 B14 PIN NAME [2] EMU1 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] NA NA PRODUCT PREVIEW NA NA 24 R14 V15 U15 T15 PIN NAME [2] GPMC_A4 GPMC_A5 GPMC_A6 GPMC_A7 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) NA NA NA NA W10 V9 V16 U16 T16 V17 U7 V7 PIN NAME [2] GPMC_A8 GPMC_A9 (8) GPMC_A10 GPMC_A11 GPMC_AD0 GPMC_AD1 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] V12 W13 V13 PRODUCT PREVIEW W14 U14 W15 V15 W16 26 R8 T8 U8 V8 R9 T9 U10 T10 PIN NAME [2] GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5 GPMC_AD6 GPMC_AD7 GPMC_AD8 GPMC_AD9 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) T12 U12 U13 T13 W17 T11 U12 T12 R12 V13 PIN NAME [2] GPMC_AD10 GPMC_AD11 GPMC_AD12 GPMC_AD13 GPMC_AD14 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] V17 V10 PRODUCT PREVIEW V8 V18 V16 W8 28 U13 R7 T6 U18 V12 V6 PIN NAME [2] GPMC_AD15 GPMC_ADVn_ALE GPMC_BEn0_CLE GPMC_BEn1 GPMC_CLK GPMC_CSn0 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) V14 U15 U17 W9 R15 U8 U9 V9 T13 T7 T17 U6 PIN NAME [2] GPMC_CSn1 GPMC_CSn2 GPMC_CSn3 (4) GPMC_OEn_REn GPMC_WAIT0 GPMC_WEn SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] W18 C18 PRODUCT PREVIEW B19 W7 U1 30 U17 C17 C16 R6 R1 PIN NAME [2] GPMC_WPn I2C0_SDA I2C0_SCL LCD_AC_BIAS_EN LCD_DATA0 (3) SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) U2 V1 V2 W2 W3 R2 R3 R4 T1 T2 PIN NAME [2] LCD_DATA1 (3) LCD_DATA2 (3) LCD_DATA3 (3) LCD_DATA4 (3) LCD_DATA5 (3) SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] V3 U3 PRODUCT PREVIEW V4 W4 32 T3 T4 U1 U2 PIN NAME [2] LCD_DATA6 (3) LCD_DATA7 (3) LCD_DATA8 (3) LCD_DATA9 (3) SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) U5 V5 V6 U6 U3 U4 V2 V3 PIN NAME [2] LCD_DATA10 (3) LCD_DATA11 (3) LCD_DATA12 (3) LCD_DATA13 (3) SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] W6 V7 PRODUCT PREVIEW T7 W5 34 V4 T5 R5 V5 PIN NAME [2] LCD_DATA14 (3) LCD_DATA15 (3) LCD_HSYNC LCD_PCLK (5) SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) U7 NA NA NA U5 B13 B12 C12 PIN NAME [2] LCD_VSYNC (5) MCASP0_FSX MCASP0_ACLKR MCASP0_AHCLKR SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] NA NA PRODUCT PREVIEW NA NA NA 36 A14 A13 C13 D12 D13 PIN NAME [2] MCASP0_AHCLKX MCASP0_ACLKX MCASP0_FSR MCASP0_AXR0 MCASP0_AXR1 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) R19 P17 L19 K17 M18 M17 J17 J16 PIN NAME [2] MDC MDIO MII1_RX_DV MII1_TX_EN SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] K19 M19 PRODUCT PREVIEW N19 J19 38 J15 L18 K18 H16 PIN NAME [2] MII1_RX_ER MII1_RX_CLK MII1_TX_CLK MII1_COL SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) J18 P18 P19 N16 H17 M16 L15 L16 PIN NAME [2] MII1_CRS MII1_RXD0 MII1_RXD1 MII1_RXD2 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] N17 L18 PRODUCT PREVIEW M18 N18 40 L17 K17 K16 K15 PIN NAME [2] MII1_RXD3 MII1_TXD0 MII1_TXD1 MII1_TXD2 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) M17 G17 G19 G18 J18 G18 G17 G16 PIN NAME [2] MII1_TXD3 MMC0_CMD MMC0_CLK MMC0_DAT0 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] H17 H18 PRODUCT PREVIEW H19 G15 F18 F17 PIN NAME [2] MMC0_DAT1 MMC0_DAT2 MMC0_DAT3 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) PIN NAME [2] SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] B17 B16 PIN NAME [2] SPI0_D1 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) E19 F18 C19 D18 D19 E15 E17 D15 D16 D17 PIN NAME [2] UART0_RXD UART0_RTSn UART1_TXD UART1_RXD UART1_RTSn SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] E17 T18 D18 M15 PIN NAME [2] UART1_CTSn USB0_CE SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] D8 SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued) ZCE BALL ZCZ BALL NUMBER [1] NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] BALL RESET TYPE BALL RESET RESET REL. ZCE POWER / HYS REL.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 (1) An internal 10 kohm pull up is turned on when the oscillator is diasabled. The oscillator is disabled by default after power is applied. (2) An internal 15 kohm pull down is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied. (3) LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3 www.ti.com Signal Description The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 (1) SIGNAL NAME: The signal name (2) DESCRIPTION: Description of the signal (3) TYPE: Ball type for this specific function: – I = Input – O = Output – I/O = Input/Output – D = Open drain – DS = Differential – A = Analog (4) BALL: Package ball location Table 2-8.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-10.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.1 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 External Memory Interfaces Table 2-11.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-11.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-12.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.2 www.ti.com General Purpose IOs Table 2-13.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-14.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-15.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Miscellaneous Table 2-17.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.3.1 www.ti.com eCAP Table 2-18. eCAP/eCAP0 Signals Description SIGNAL NAME [1] eCAP0_in_PWM0_out DESCRIPTION [2] Enhanced Capture 0 input or Auxiliary PWM0 output TYPE [3] I/O ZCE BALL [4] E18 ZCZ BALL [4] C18 Table 2-19.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.3.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 eHRPWM Table 2-21. eHRPWM/eHRPWM0 Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4] ehrpwm0A eHRPWM0 A output. O A18 A13, A17 ehrpwm0B eHRPWM0 B output.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.3.3 www.ti.com eQEP Table 2-24. eQEP/eQEP0 Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4] eQEP0A_in eQEP0A quadrature input I M18 B12, K16 eQEP0B_in eQEP0B quadrature input I L18 C13, K17 eQEP0_index eQEP0 index. I/O K17 D13, J16 eQEP0_strobe eQEP0 strobe. I/O P19 A14, L15 Table 2-25.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.3.4 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Timer Table 2-27. Timer/Timer4 Signals Description SIGNAL NAME [1] timer4 DESCRIPTION [2] Timer trigger event / PWM out TYPE [3] I/O ZCE BALL [4] C15, C18, K17, V10 ZCZ BALL [4] A15, C17, J16, R7 Table 2-28.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.4 www.ti.com PRU-ICSS Table 2-31. PRU-ICSS/eCAP Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] pr1_ecap0_ecap_capin_apwm_o Enhanced capture input or Auxiliary PWM out I/O ZCE BALL [4] E18, V17 ZCZ BALL [4] C18, U13 Table 2-32.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-34.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.4.1 www.ti.com PRU0 Table 2-37.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.4.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 PRU1 Table 2-39.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.5 www.ti.com Removable Media Interfaces Table 2-41.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.6 2.3.6.1 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Serial Communication Interfaces CAN Table 2-44. CAN/DCAN0 Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4] dcan0_rx DCAN0 Receive Data I D19, F17, N18 D17, E16, K15 dcan0_tx DCAN0 Transmit Data O E17, E19, M17 D18, E15, J18 Table 2-45.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.6.2 www.ti.com GEMAC_CPSW Table 2-46. GEMAC_CPSW/MDIO Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4] mdio_clk MDIO Clk O R19 M18 mdio_data MDIO Data I/O P17 M17 Table 2-47.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-49.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 2-52.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.6.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 I2C Table 2-53. I2C/I2C0 Signals Description SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4] I2C0_SCL I2C0 Clock I/OD B19 C16 I2C0_SDA I2C0 Data I/OD C18 C17 Table 2-54.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.6.4 www.ti.com McASP Table 2-56.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 2.3.6.5 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 SPI Table 2-58. SPI/SPI0 Signals Description SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCE BALL [4] ZCZ BALL [4] spi0_cs0 SPI Chip Select I/O A17 A16 spi0_cs1 SPI Chip Select I/O B16 C15 spi0_d0 SPI Data I/O B18 B17 spi0_d1 SPI Data I/O B17 B16 spi0_sclk SPI Clock I/O A18 A17 Table 2-59.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.6.6 www.ti.com UART Table 2-60. UART/UART0 Signals Description SIGNAL NAME [1] TYPE [3] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4] uart0_ctsn UART Clear to Send I F19 E18 uart0_rtsn UART Request to Send O F18 E17 uart0_rxd UART Receive Data I E19 E15 uart0_txd UART Transmit Data O F17 E16 Table 2-61.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 2-65.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 2.3.6.7 www.ti.com USB Table 2-66.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 3 Device Operating Conditions 3.1 Absolute Maximum Ratings Table 3-1. Absolute Maximum Ratings Over Junction Temperature Range (Unless Otherwise Noted)(1)(2) MAX Supply voltage for the MPU core domain PARAMETER -0.5 1.5 V VDD_CORE Supply voltage range for the core domain -0.5 1.5 V CAP_VDD_RTC(4) Supply voltage range for the RTC core domain -0.5 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 3.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Recommended Operating Conditions Device Operating Performance Points are defined in Table 3-2 through Table 3-7. Table 3-2. VDD_CORE Operating Performance Points for ZCZ Package with Device Revision Code "Blank"(1) VDD_CORE OPP Device Rev. "Blank" VDD_CORE MIN NOM MAX DDR3, DDR3L(2) DDR2(2) mDDR(2) L3 and L4 OPP100 1.056 V 1.100 V 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 3-5. VDD_CORE Operating Performance Points for ZCZ Package with Device Revision Code "A" or Newer(1) VDD_CORE OPP Rev "A" or Newer VDD_CORE MIN NOM MAX DDR3, DDR3L(2) DDR2(2) mDDR(2) L3 and L4 OPP100 1.056 V 1.100 V 1.144 V 303 MHz(3) 266 MHz 200 MHz 200 MHz and 100 MHz OPP50 0.912 V 0.950 V 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 3-8 summarizes the power consumption at the AM335x power terminals. Table 3-8.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com The power-on hours (POH) information in Table 3-9 is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. Table 3-9.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 PARAMETER SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT VDDS_PLL_MPU(5) Supply voltage range for DPLL MPU, Analog 1.710 1.800 1.890 V VDDS_OSC Supply voltage range for system oscillator IO's, Analog 1.710 1.800 1.890 V VDDA1P8V_USB0(5) Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V 1.710 1.800 1.890 V VDDA1P8V_USB1(6) Supply voltage range for USB PHY, Analog, 1.8V 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 3-10. Recommended Operating Conditions (continued) PARAMETER SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT USB0_ID Voltage range for the USB ID input 1.710 1.800 1.890 V USB1_ID(6) Voltage range for the USB ID input 1.710 1.800 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 3.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 DC Electrical Characteristics Table 3-11 summarizes the dc electrical characteristics. Note: The interfaces or signals described in Table 3-11 correspond to the interfaces or signals available in multiplexing mode 0. All interfaces or signals multiplexed on the terminals described in Table 3-11 have the same dc electrical characteristics. Table 3-11.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 3-11.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 3-11. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (continued) PARAMETER MIN NOM MAX UNIT ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_T XD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,PWRONRSTn,NMIn,TMS,TDO,USB0_DRVVBUS,U SB1_DRVVBUS (VDDSHV6 = 3.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 3-11. DC Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (continued) PARAMETER MIN NOM MAX UNIT All other LVCMOS pins (VDDSHVx = 1.8 V; x=1-6) VIH High-level input voltage 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 3.4 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 External Capacitors To improve module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. 3.4.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 3-13. Power-Supply Decoupling Capacitor Characteristics (continued) TYP UNIT CVDDSHV4(5) PARAMETER 10.02 μF (5) 10.02 μF CVDDSHV6(3) 10.06 μF CVDDSHV5 (1) Not available on the ZCE package. (2) Typical values consist of 1 cap of 10 μF and 4 caps of 10 nF. (3) Typical values consist of 1 cap of 10 μF and 6 caps of 10 nF.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Figure 3-1 illustrates an example of the external capacitors.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 3.5 www.ti.com Touchscreen Controller and Analog-to-Digital Subsystem Electrical Parameters The touchscreen controller (TSC) and analog-to-digital converter (ADC) subsystem (TSC_ADC) is an 8-channel general-purpose ADC with optional support for interleaving TSC conversions for 4-wire, 5-wire, or 8-wire resistive panels.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 3-15. TSC_ADC Electrical Parameters (continued) PARAMETER CONDITION MIN NOM MAX UNIT Spurious Free Dynamic Range Internal Voltage Reference: VDDA_ADC = 1.8V External Voltage Reference: VREFP - VREFN = 1.8V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 80 dB Signal-to-Noise Plus Distortion Internal Voltage Reference: VDDA_ADC = 1.8V External Voltage Reference: VREFP - VREFN = 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 4 Power and Clocking 4.1 Power Supplies 4.1.1 Power-Up Sequencing 1.8V VDDS_RTC 1.8V RTC_PWRONRSTn 1.8V PMIC_POWER_EN 1.8V All 1.8-V Supplies 1.8V/1.5V/1.35V VDDS_DDR PRODUCT PREVIEW 3.3V IO 3.3-V Supplies 1.1V VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. B. C. D. E. F.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 1.8V VDDS_RTC 1.8V RTC_PWRONRSTn 1.8V PMIC_POWER_EN 3.3V All 1.8-V Supplies All 3.3-V Supplies See Notes Below 1.8V 1.8V/1.5V/1.35V VDDS_DDR 1.1V VDD_CORE, VDD_MPU PRODUCT PREVIEW PWRONRSTn CLK_M_OSC A. B. C. D. E. F. G. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released. The 3.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 1.8V VDDS_RTC 1.8V RTC_PWRONRSTn 1.8V PMIC_POWER_EN 1.8V All 1.8-V Supplies 1.8V/1.5V/1.35V VDDS_DDR 3.3V All 3.3-V Supplies 1.1V VDD_CORE, VDD_MPU PRODUCT PREVIEW PWRONRSTn CLK_M_OSC A. B. C. D. E. F. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 1.8V 1.1V VDDS_RTC, CAP_VDD_RTC 1.8V RTC_PWRONRSTn 1.8V PMIC_POWER_EN 1.8V VDDSHV 1-6 All other 1.8-V Supplies 1.8V/1.5V/1.35V VDDS_DDR 3.3V All 3.3-V Supplies 1.1V PRODUCT PREVIEW VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. B. C. D. E. F. G.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 1.8V VDDS_RTC, All other 1.8-V Supplies 1.8V/1.5V/1.35V VDDS_DDR 3.3V All 3.3-V Supplies 1.1V VDD_CORE, VDD_MPU CAP_VDD_RTC PWRONRSTn CLK_M_OSC PRODUCT PREVIEW A. B. C. D. E. F. CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 If none of the VDDSHVx [1-6] power supplies are configured as 3.3 V, the VDDS power supply may ramp down along with the VDDSHVx [1-6] supplies or after all the VDDSHVx [1-6] supplies have ramped down. It is recommended to maintain VDDS ≥1.5V as all the other supplies fully ramp down to minimize in-rush currents. 4.1.3 VDD_MPU_MON Connections Figure 4-6 shows the VDD_MPU_MON connectivity.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 4.1.4 www.ti.com Digital Phase-Locked Loop Power Supply Requirements The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display DPLL, DDR DPLL, MPU DPLL. Figure 4-7 illustrates the power supply connectivity implemented in the AM335x device.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 4.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Clock Specifications 4.2.1 Input Clock Specifications The AM335x device has two clock inputs. Each clock input passes through an internal oscillator which can be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock source (bypass mode).
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com AM335x VSS_OSC XTALIN XTALOUT C1 C2 Crystal Optional Rd Optional Rbias A. B. PRODUCT PREVIEW Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 4-3. OSC0 Crystal Circuit Characteristics NAME DESCRIPTION Cpkg Shunt capacitance of package MIN Pxtal The actual values of the ESR, fxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, fxtal, and CL parameters yields a maximum power dissipation value. tsX Start-up time ZCE package ZCZ package TYP MAX pF 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 4.2.2.2 www.ti.com OSC0 LVCMOS Digital Clock Source Figure 4-10 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this mode of operation, the XTALOUT terminal should not be used to source any external components.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 AM335x (ZCE Package) RTC_XTALIN RTC_XTALOUT Optional Rbias Optional Rd Crystal C1 A. B. C2 Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 4-5. OSC1 Crystal Circuit Requirements NAME DESCRIPTION fxtal Crystal parallel resonance frequency Fundamental mode oscillation only MIN TYP MAX Crystal frequency stability and tolerance Maximum RTC error = 10.512 minutes per year -20.0 20.0 ppm Maximum RTC error = 26.28 minutes per year -50.0 50.0 ppm 32.768 UNIT kHz CC1 C1 capacitance 12.0 24.0 pF CC2 C2 capacitance 12.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 4.2.2.4 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 OSC1 LVCMOS Digital Clock Source Figure 4-14 shows the recommended oscillator connections when OSC1 of the ZCE package is connected to an LVCMOS square-wave digital clock source and Figure 4-15 shows the recommended oscillator connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 4.2.2.5 www.ti.com OSC1 Not Used Figure 4-16 shows the recommended oscillator connections when OSC1 of the ZCE package is not used and Figure 4-17 shows the recommended oscillator connections when OSC1 of the ZCZ package is not used.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 4.2.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Output Clock Specifications The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0 input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73).
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5 Peripheral Information and Timings The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.3 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Controller Area Network (CAN) For more information, see the Controller Area Network (CAN) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.3.1 DCAN Electrical Data and Timing Table 5-1. Timing Requirements for DCANx Receive (see Figure 5-1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.4 www.ti.com Ethernet Media Access Controller (EMAC) and Switch 5.4.1 Ethernet MAC and Switch Electrical Data and Timing The Ethernet MAC and Switch implemented in the AM335x device supports GMII mode, but the AM335x design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals. Therefore, the AM335x device does not support GMII mode.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 4 1 3 2 MDIO_CLK 4 Figure 5-3. MDIO_CLK Timing Table 5-6. Switching Characteristics for MDIO_DATA (see Figure 5-4) NO. 1 PARAMETER td(MDC-MDIO) MIN Delay time, MDC high to MDIO valid TYP 10 MAX UNIT 390 ns 1 MDIO_CLK (Output) Figure 5-4. MDIO_DATA Timing - Output Mode 5.4.1.2 Ethernet MAC and Switch MII Electrical Data and Timing Table 5-7.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 5-8. Timing Requirements for GMII[x]_TXCLK - MII Mode (see Figure 5-6) 10 Mbps NO. MIN 100 Mbps TYP MAX MIN TYP MAX UNIT 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-10. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode (see Figure 5-8) NO. 1 PARAMETER td(TX_CLK-TXD) Delay time, TX_CLK high to TXD[3:0] valid td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 10 Mbps MIN 5 TYP 100 Mbps MAX MIN 25 5 TYP MAX 25 UNIT ns 1 GMII[x]_TXCLK (input) GMII[x]_TXD[3:0], GMII[x]_TXEN (outputs) PRODUCT PREVIEW Figure 5-8.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.4.1.3 www.ti.com Ethernet MAC and Switch RMII Electrical Data and Timing Table 5-11. Timing Requirements for RMII[x]_REFCLK - RMII Mode (see Figure 5-9) NO. MIN TYP MAX UNIT 1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns 2 tw(REF_CLKH) Pulse Duration, REF_CLK high 7 13 ns 3 tw(REF_CLKL) Pulse Duration, REF_CLK low 7 13 ns 1 2 RMII[x]_REFCLK (Input) 3 Figure 5-9.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-13. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode (see Figure 5-11) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.4.1.4 www.ti.com Ethernet MAC and Switch RGMII Electrical Data and Timing Table 5-14. Timing Requirements for RGMII[x]_RCLK - RGMII Mode (see Figure 5-12) 10 Mbps NO. 1 MIN 100 Mbps TYP MAX MIN TYP 1000 Mbps MAX MIN TYP MAX UNIT tc(RXC) Cycle time, RXC 360 440 36 44 7.2 8.8 ns 2 tw(RXCH) Pulse duration, RXC high 160 240 16 24 3.6 4.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-16. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode (see Figure 5-14) NO. 1 10 Mbps PARAMETER MIN 100 Mbps TYP MAX MIN 1000 Mbps TYP MAX MIN TYP MAX UNIT tc(TXC) Cycle time, TXC 360 440 36 44 7.2 8.8 ns 2 tw(TXCH) Pulse duration, TXC high 160 240 16 24 3.6 4.4 ns 3 tw(TXCL) Pulse duration, TXC low 160 240 16 24 3.6 4.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5 www.ti.com External Memory Interfaces The device includes the following external memory interfaces: • General-purpose memory controller (GPMC) • mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface (EMIF) 5.5.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-20. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2) PARAMETER OPP100 UNIT MIN MAX F0 1 / tc(clk) Frequency(15), output clock gpmc_clk F1 tw(clkH) Typical pulse duration, output clock gpmc_clk high 0.5P(12) 0.5P(12) ns F1 tw(clkL) Typical pulse duration, output clock gpmc_clk low 0.5P(12) 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com – SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) otherwise Case GpmcFCLKDivider = 2: – H = 0.5 * OEExtraDelay * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK(14) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3) – H = (2 + 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com F1 F0 F1 gpmc_clk F2 F3 F18 gpmc_csn[x] F4 gpmc_a[10:1] Valid Address F6 F7 F19 gpmc_be0n_cle F19 gpmc_be1n F6 F8 F8 F20 F9 gpmc_advn_ale F10 F11 PRODUCT PREVIEW gpmc_oen F13 F12 gpmc_ad[15:0] D0 gpmc_wait[x] A. B. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-16.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 F1 F0 F1 gpmc_clk F2 F3 gpmc_csn[x] F4 Valid Address gpmc_a[10:1] F6 F7 gpmc_be0n_cle F7 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F10 F11 gpmc_oen F13 F13 gpmc_ad[15:0] D0 F21 F12 D1 D2 D3 PRODUCT PREVIEW F12 F22 gpmc_wait[x] A. B. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-17.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_csn[x] F4 Valid Address gpmc_a[10:1] F17 F6 F17 F17 gpmc_be0n_cle F17 F17 F17 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F14 F14 PRODUCT PREVIEW gpmc_wen F15 gpmc_ad[15:0] D0 D1 F15 F15 D2 D3 gpmc_wait[x] A. B. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-18.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 F1 F0 F1 gpmc_clk F2 F3 gpmc_csn[x] F6 F7 gpmc_be0n_cle Valid F6 F7 gpmc_be1n Valid F4 gpmc_a[27:17] Address (MSB) F12 F4 gpmc_ad[15:0] F5 Address (LSB) F13 D0 F8 D1 F12 D2 F8 D3 F9 gpmc_advn_ale F10 F11 PRODUCT PREVIEW gpmc_oen gpmc_wait[x] A. B. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-19.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com F1 F1 F0 gpmc_clk F2 F3 F18 gpmc_csn[x] F4 gpmc_a[27:17] Address (MSB) F17 F6 F17 F6 F17 F17 gpmc_be1n F17 F17 gpmc_be0n_cle F8 F8 F20 F9 gpmc_advn_ale F14 F14 PRODUCT PREVIEW gpmc_wen F15 gpmc_ad[15:0] Address (LSB) D0 F22 D1 F15 F15 D2 D3 F21 gpmc_wait[x] A. B. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-20.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.5.1.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 GPMC and NOR Flash—Asynchronous Mode Table 5-22 and Table 5-23 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-21 through Figure 5-26). Table 5-21.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 5-23. GPMC and NOR Flash Timing Requirements—Asynchronous Mode NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-24. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com GPMC_FCLK gpmc_clk FA5 FA1 gpmc_csn[x] FA9 gpmc_a[10:1] Valid Address FA0 FA10 gpmc_be0n_cle Valid FA0 gpmc_be1n Valid FA10 FA3 FA12 gpmc_advn_ale FA4 PRODUCT PREVIEW FA13 gpmc_oen Data IN 0 gpmc_ad[15:0] Data IN 0 gpmc_wait[x] A. B. C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 GPMC_FCLK gpmc_clk FA5 FA5 FA1 FA1 gpmc_csn[x] FA16 FA9 FA9 gpmc_a[10:1] Address 0 Address 1 FA0 FA10 FA0 FA10 gpmc_be0n_cle Valid Valid FA0 gpmc_be1n FA0 Valid FA10 Valid FA10 FA3 FA3 FA12 FA12 gpmc_advn_ale FA4 PRODUCT PREVIEW FA4 FA13 FA13 gpmc_oen gpmc_ad[15:0] Data Upper gpmc_wait[x] A. B. C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com GPMC_FCLK gpmc_clk FA21 FA20 FA20 FA20 Add1 Add2 Add3 D0 D1 D2 FA1 gpmc_csn[x] FA9 Add0 gpmc_a[10:1] Add4 FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA12 gpmc_advn_ale FA18 PRODUCT PREVIEW FA13 gpmc_oen gpmc_ad[15:0] D3 D3 gpmc_wait[x] A. B. C. D. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 gpmc_fclk gpmc_clk FA1 gpmc_csn[x] FA9 gpmc_a[10:1] Valid Address FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 PRODUCT PREVIEW gpmc_wen FA29 gpmc_ad[15:0] Data OUT gpmc_wait[x] A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-24.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com GPMC_FCLK gpmc_clk FA1 FA5 gpmc_csn[x] FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle Valid FA0 FA10 gpmc_be1n Valid FA3 FA12 gpmc_advn_ale FA4 PRODUCT PREVIEW FA13 gpmc_oen FA29 gpmc_ad[15:0] FA37 Data IN Address (LSB) Data IN gpmc_wait[x] A. B. C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 gpmc_fclk gpmc_clk FA1 gpmc_csn[x] FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 FA29 gpmc_ad[15:0] PRODUCT PREVIEW gpmc_wen FA28 Valid Address (LSB) Data OUT gpmc_wait[x] A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-26.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.1.3 www.ti.com GPMC and NAND Flash—Asynchronous Mode Table 5-26 and Table 5-27 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-27 through Figure 5-30). Table 5-25.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-28.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com GPMC_FCLK GNF1 GNF6 GNF2 GNF5 gpmc_csn[x] gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF0 gpmc_wen GNF3 GNF4 gpmc_ad[15:0] (1) Command In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5. Figure 5-27.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 GPMC_FCLK GNF12 GNF10 GNF15 gpmc_csn[x] gpmc_be0n_cle gpmc_advn_ale GNF14 GNF13 gpmc_oen gpmc_ad[15:0] DATA gpmc_wait[x] (1) (2) (3) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2 www.ti.com mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface The device has a dedicated interface to mDDR(LPDDR),DDR2, DDR3, and DDR3L SDRAM. It supports JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit data path to external SDRAM memory.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.1.2.2 Compatible JEDEC LPDDR Devices Table 5-30 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices. Table 5-30. Compatible JEDEC LPDDR Devices (Per Interface)(1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Complete stackup specifications are provided in Table 5-32. Table 5-32.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.1.2.4 Placement Figure 5-33 shows the required placement for the LPDDR devices. The dimensions for this figure are defined in Table 5-33. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.1.2.5 LPDDR Keepout Region The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keepout region is defined for this purpose and is shown in Figure 5-34. This region should encompass all LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional clearances required for the keepout region are shown in Table 5-33.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.1.2.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x device LPDDR power, and AM335x device LPDDR ground connections.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.1.2.9 LPDDR Signal Termination There is no specific need for adding terminations on the LPDDR interface. However, system designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.1.3 LPDDR CK and ADDR_CTRL Routing Figure 5-35 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the majority of the total length of signal path AB and AC. C A LPDDR Interface B A1 AM335x A1 Figure 5-35.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 A1 DQ[0] DQ[1] LPDDR Interface Figure 5-36 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. AM335x Figure 5-36. DQS[x] and DQ[x] Routing and Topology Table 5-40.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.2 www.ti.com DDR2 Routing Guidelines 5.5.2.2.1 Board Designs TI only supports board designs that follow the guidelines outlined in this document. The switching characteristics and the timing diagram for the DDR2 memory interface are shown in Table 5-41 and Figure 5-37. Table 5-41. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Interface NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 16-Bit DDR2 Device AM335x DDR_D0 DDR_D7 DDR_DQM0 DDR_DQS0 DQ7 LDM LDQS DDR_DQSn0 DDR_D8 LDQS DQ8 DDR_D15 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DQ15 UDM UDQS UDQS DDR_ODT T ODT DDR_BA0 T BA0 DDR_BA2 DDR_A0 T T BA2 A0 DDR_A15 DDR_CSn0 T T A15 CS DDR_CASn DDR_RASn DDR_WEn DDR_CKE DDR_CK T T T T T T CAS DDR_CKn RAS WE CKE CK CK DDR_VREF 0.1 µF (B) 0.1 µF (A) 1 K Ω 1% DDR_VREF VREF 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.2.2.2 Compatible JEDEC DDR2 Devices Table 5-42 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices. Table 5-42. Compatible JEDEC DDR2 Devices (Per Interface)(1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Complete stackup specifications are provided in Table 5-44. Table 5-44. PCB Stackup Specifications(1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.2.2.4 Placement Figure 5-40 shows the required placement for the DDR2 devices. The dimensions for this figure are defined in Table 5-45. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.2.2.5 DDR2 Keepout Region The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keepout region is defined for this purpose and is shown in Figure 5-41. This region should encompass all DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional clearances required for the keepout region are shown in Table 5-45.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.2.2.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x device DDR2 power, and AM335x device DDR2 ground connections.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.2.2.9 DDR2 Signal Termination Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to ensure signal integrity.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.2.2.10 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 5-38 and Figure 5-39. Other methods of creating DDR_VREF are not recommended. Figure 5-42 shows the layout guidelines for DDR_VREF.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.2.3 DDR2 CK and ADDR_CTRL Routing Figure 5-43 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the majority of the total length of signal path AB and AC. T C A DDR2 Interface B A1 AM335x A1 Figure 5-43. CK and ADDR_CTRL Routing and Topology NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-53. DQS[x] and DQ[x] Routing Specification(1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.3 www.ti.com DDR3 and DDR3L Routing Guidelines NOTE All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted. 5.5.2.3.1 Board Designs TI only supports board designs utilizing DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-54 and Figure 5-45. Table 5-54.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.3.3 DDR3 Interface 5.5.2.3.3.1 DDR3 Interface Schematic The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 5-46 shows the schematic connections for 16-bit interface on AM335x device using one x16 DDR3 device and Figure 5-48 shows the schematic connections for 16-bit interface on AM335x device using two x8 DDR3 devices.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 16-Bit DDR3 Interface 16-Bit DDR3 Device DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DMU DQSU DQSU# DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DDR_DQS0 DDR_DQSn0 DML DQSL DQSL# DDR_CK DDR_CKn CK CK# DDR_ODT DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 ODT CS# BA0 BA1 BA2 DDR_A0 A0 15 PRODUCT PREVIEW DDR_A15 A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE DDR_RESETn ZQ DDR_VREF 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.3.2 Compatible JEDEC DDR3 Devices Table 5-56 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface. Generally, the DDR3 interface is compatible with DDR3-800 devices in the x8 or x16 widths. Table 5-56. Compatible JEDEC DDR3 Devices (Per Interface) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-58. PCB Stackup Specifications(1) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.3.4 Placement Figure 5-49 shows the required placement for the AM335x device as well as the DDR3 devices. The dimensions for this figure are defined in Table 5-59. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.3.3.5 DDR3 Keepout Region The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 5-50. This region should encompass all DDR3 circuitry and the region size varies with component placement and DDR3 routing. Additional clearances required for the keepout region are shown in Table 5-59.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.3.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x device DDR3 power, and AM335x device DDR3 ground connections.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.3.3.8 Net Classes Table 5-62 lists the clock net classes for the DDR3 interface. Table 5-63 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow. Table 5-62.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.4.1 Two DDR3 Devices Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 5.5.2.3.4.1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 A1 A1 www.ti.com VDDS_DDR A3 A3 = Rcp Cac Rcp 0.1 µF AT AT AS+ AS- A2 A2 A1 PRODUCT PREVIEW Figure 5-53. CK Routing for Two Single-Side DDR3 Devices Rtt A3 = AT Vtt AS A2 Figure 5-54.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com A1 A1 To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 5-55 and Figure 5-56 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration. VDDS_DDR A3 A3 = Rcp Cac Rcp 0.1 µF AT AT PRODUCT PREVIEW AS+ AS- A2 A2 A1 Figure 5-55.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.5.2.3.4.2 One DDR3 Device A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16-bit bank. 5.5.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 5-57 shows the topology of the CK net classes and Figure 5-58 shows the topology for the corresponding ADDR_CTRL net classes.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device A1 A1 Figure 5-59 shows the CK routing for one DDR3 device. Figure 5-60 shows the corresponding ADDR_CTRL routing. VDDS_DDR Rcp Cac Rcp 0.1 µF AT AT PRODUCT PREVIEW = AS+ AS- A2 A2 A1 Figure 5-59. CK Routing for One DDR3 Device Rtt AT = Vtt AS A2 Figure 5-60. ADDR_CTRL Routing for One DDR3 Device 5.5.2.3.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 AM335x DQS[x] IO Buffer DDR3 DQS[x] IO Buffer DQS[x]+ DQS[x]Routed Differentially x = 0, 1 Figure 5-61. DQS[x] Topology AM335x DQ[x] IO Buffer DDR3 DQ[x] IO Buffer DQ[x] x = 0, 1 Figure 5-62. DQ[x] Topology 5.5.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices DQS[x]+ DQS[x]- PRODUCT PREVIEW Figure 5-63 and Figure 5-64 show the DQS[x] and DQ[x] routing.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.5.2.3.6 Routing Specification 5.5.2.3.6.1 CK and ADDR_CTRL Routing Specification Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-64. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com DQLMX0 DQ0 DQ1 DQ[0:7], DM0, DQS0 DQ[8:15], DM1, DQS1 DQLMX1 DQLMY0 DQLMY1 1 0 DQ0 - DQ1 represent data bytes 0 - 1. There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore: DQLM0 = DQLMX0 + DQLMY0 DQLM1 = DQLMX1 + DQLMY1 Figure 5-66. DQLM for Any Number of Allowed DDR3 Devices PRODUCT PREVIEW Table 5-65.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.6 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Inter-Integrated Circuit (I2C) For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.6.1 I2C Electrical Data and Timing Table 5-66.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 9 11 I2C[x]_SDA 6 8 14 4 13 5 10 I2C[x]_SCL 1 12 3 7 2 3 Stop Start Repeated Start Stop Figure 5-67. I2C Receive Timing Table 5-68. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings (see Figure 5-68) PRODUCT PREVIEW NO. 15 STANDARD MODE PARAMETER MIN MAX FAST MODE MIN MAX UNIT tc(SCL) Cycle time, SCL 10 2.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.7 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 LCD Controller (LCDC) The LCD controller consists of two independent controllers, the raster controller and the LCD interface display driver (LIDD) controller. Each controller operates independently from the other and only one of them is active at any given time. • The raster controller handles the synchronous LCD interface.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 5-71. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode (continued) (see Figure 5-70 through Figure 5-78) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 W_SU (0 to 31) CS_DELAY (0 to 3) W_STROBE (1 to 63) W_HOLD (1 to 15) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 7 4 LCD_DATA[15:0] 5 Write Data 20 LCD_VSYNC (RS) 10 10 LCD_HSYNC (R/W) 11 6 6 LCD_AC_BIAS_EN (E0) PRODUCT PREVIEW 7 A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com R_SU (0 to 31) R_STROBE (1 to 63) R_HOLD (1 to 15) CS_DELAY (0 to 3) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 14 7 16 17 15 LCD_DATA[15:0] Read Data 18 LCD_VSYNC (RS) LCD_HSYNC (R/W) 6 6 LCD_AC_BIAS_EN (E0) 7 PRODUCT PREVIEW A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 R_SU (0−31) 1 2 3 R_STROBE (1−63) R_HOLD (1−15) CS_DELAY (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 19 6 6 LCD_MEMORY_CLK (CS1) Async Mode 7 14 16 17 15 LCD_DATA[15:0] Read Status 18 6 6 LCD_AC_BIAS_EN (CS0) 8 PRODUCT PREVIEW 7 8 LCD_VSYNC (ALE) 9 LCD_HSYNC (DIR) 12 12 LCD_PCLK (EN) 13 A. Motorola mode can be configured to perform asynchronous operations or synchronous operations.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com W_HOLD (1−15) 1 W_SU (0−31) W_SU (0−31) W_STROBE (1−63) 2 3 W_HOLD (1−15) CS_DELAY (0−3) W_STROBE (1−63) CS_DELAY (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 19 6 6 6 6 5 4 5 LCD_MEMORY_CLK (CS1) Async Mode 7 4 LCD_DATA[15:0] Write Address Write Data 20 6 6 6 6 LCD_AC_BIAS_EN (CS0) 7 PRODUCT PREVIEW 8 8 LCD_VSYNC (ALE) 9 10 10 10 10 LCD_HSYNC (WS) 11 LCD_PCLK (RS) A.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 R_SU (0−31) W_HOLD (1−15) 1 W_SU (0−31) 2 3 W_STROBE (1−63) R_STROBE (1−63) CS_DELAY (0−3) R_HOLD (1−15) CS_DELAY (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 19 6 6 LCD_MEMORY_CLK (CS1) Async Mode 7 4 LCD_DATA[15:0] 5 16 14 17 15 Write Address 18 20 6 6 Read Data 6 6 LCD_AC_BIAS_EN (CS0) 8 PRODUCT PREVIEW 7 8 LCD_VSYNC (ALE) 9 10 10 LCD_HSYNC (WS) 11 12 12 LCD_PCLK (RS) A.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com R_SU (0−31) 1 2 3 R_STROBE (1−63) R_HOLD (1−15) CS_DELAY (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 19 6 6 LCD_MEMORY_CLK (CS1) Async Mode 7 14 16 17 15 LCD_DATA[15:0] Read Status 18 6 6 LCD_AC_BIAS_EN (CS0) PRODUCT PREVIEW 7 8 8 LCD_VSYNC (ALE) 9 LCD_HSYNC (WS) 12 12 LCD_PCLK (RS) 13 A. Intel mode can be configured to perform asynchronous operations or synchronous operations.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.7.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 LCD Raster Mode Table 5-72. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode (see Figure 5-80 through Figure 5-83) PARAMETER OPP50 MIN OPP100 MAX 15.8 MIN MAX 7.9 UNIT 1 tc(LCD_PCLK) Cycle time, pixel clock 2 tw(LCD_PCLKH) Pulse duration, pixel clock high 0.45tc 0.55tc 0.45tc 0.55tc ns 3 tw(LCD_PCLKL) Pulse duration, pixel clock low 0.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Data Pixels (From 1 to P) 1, 1 2, 1 1, 2 2, 2 P−2, 1 3, 1 P−1, 1 P, 1 P−1, 2 P, 2 1, 3 Data Lines (From 1 to L) P, 3 LCD PRODUCT PREVIEW 1, L−2 P, L−2 1, L−1 2, L−1 1, L 2, L P−2, L 3, L P−1, L−1 P, L−1 P−1, L P, L Figure 5-79.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 6 LCD_AC_BIAS_EN 7 8 LCD_VSYNC 9 10 10 LCD_HSYNC 11 1 2 3 LCD_PCLK (passive mode) 5 1, L 2, L P, L 1, 1 2, 1 P, 1 PRODUCT PREVIEW 4 LCD_DATA[7:0] (passive mode) 1 2 3 LCD_PCLK (active mode) 5 4 LCD_DATA[23:0] (active mode) VBP = 0 VFP = 0 VWS = 1 1, L 2, L P, L PPLMSB + PPLLSB 16 x (1 to 2048) HFP (1 to 256) HSW (1 to 64) HBP (1 to 256) Line L A.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 6 LCD_AC_BIAS_EN 8 LCD_VSYNC 10 10 LCD_HSYNC 11 1 2 3 LCD_PCLK (passive mode) 4 PRODUCT PREVIEW LCD_D[7:0] (passive mode) 1, 1 P, 1 2, 1 1, 2 2, 2 1, 1 2, 1 5 P, 2 1 2 3 LCD_PCLK (active mode) 4 LCD_DATA[23:0] (active mode) VBP = 0 VFP = 0 VWS = 1 PPLMSB + PPLLSB 16 x (1 to 2048) HFP (1 to 256) HSW (1 to 64) HBP (1 to 256) PPLMSB + PPLLSB Line 1 A.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.8 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Multichannel Audio Serial Port (McASP) The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT).
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.8.2 www.ti.com McASP Electrical Data and Timing Table 5-73. McASP Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 1(1) 4(1) ns tF Input signal fall time 1(1) 4(1) ns 15 30 pF Output Condition CLOAD Output load capacitance (1) Except when specified otherwise. Table 5-74. Timing Requirements for McASP(1) (see Figure 5-84) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 5-75. Switching Characteristics Over Recommended Operating Conditions for McASP(1) (see Figure 5-85) NO.
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AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.9 www.ti.com Multichannel Serial Port Interface (McSPI) For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.9.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 2 9 POL=0 1 3 2 POL=1 SPI_SCLK (In) 4 4 5 SPI_D[x] (SIMO, In) 5 Bit n-1 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 PRODUCT PREVIEW EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (In) 4 5 SPI_D[x] (SIMO, In) Bit n-1 4 5 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure 5-86.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 2 9 POL=0 1 3 2 POL=1 SPI_SCLK (In) SPI_D[x] (SOMI, Out) 6 7 6 Bit n-1 Bit n-2 Bit n-3 Bit 0 Bit n-4 PHA=1 EPOL=1 PRODUCT PREVIEW SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (In) 6 SPI_D[x] (SOMI, Out) Bit n-1 6 6 Bit n-2 Bit n-3 6 Bit 1 Bit 0 Figure 5-87.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com 5.9.1.2 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 McSPI—Master Mode Table 5-79. McSPI Timing Conditions—Master Mode LOW LOAD TIMING CONDITION PARAMETER MIN HIGH LOAD MAX MIN MAX UNIT Input Conditions tr Input signal rise time 8 16 ns tf Input signal fall time 8 16 ns 5 25 pF Output Condition Cload Output load capacitance Table 5-80.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 4 5 SPI_D[x] (SOMI, In) 5 Bit n-1 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 PRODUCT PREVIEW SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 5 SPI_D[x] (SOMI, In) Bit n-1 4 5 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure 5-88.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 PHA=0 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 7 SPI_D[x] (SIMO, Out) Bit n-1 6 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 PRODUCT PREVIEW SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 SPI_D[x] (SIMO, Out) Bit n-1 6 Bit n-2 6 Bit n-3 6 Bit 1 Bit 0 Figure 5-89.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.10 Multimedia Card (MMC) Interface For more information, see the Multimedia Card (MMC) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.10.1 MMC Electrical Data and Timing Table 5-82.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-84. Switching Characteristics for MMC[x]_CLK (see Figure 5-91) NO. STANDARD MODE PARAMETER MIN fop(CLK) Operating frequency, MMC_CLK tcop(CLK) Operating period: MMC_CLK fid(CLK) Identification mode frequency, MMC_CLK tcid(CLK) Identification mode period: MMC_CLK 6 tw(CLKL) 7 5 TYP HIGH-SPEED MODE MAX MIN TYP 24 UNIT MAX 48 MHz 41.7 20.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com Table 5-86. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode (see Figure 5-93) NO. PARAMETER 12 td(CLKL-CMD) Delay time, MMC_CLK rising clock edge to MMC_CMD transition 13 td(CLKL-DAT) Delay time, MMC_CLK rising clock edge to MMC_DATx transition MIN TYP MAX UNIT 2.5 14 ns 2.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 5.11 Universal Asynchronous Receiver Transmitter (UART) For more information, see the Universal Asynchronous Receiver Transmitter (UART) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.11.1 UART Electrical Data and Timing Table 5-87. Timing Requirements for UARTx Receive (see Figure 5-94) NO.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 5.11.2 UART IrDA Interface The IrDA module operates in three different modes: • Slow infrared (SIR) (≤ 115.2 Kbps) • Medium infrared (MIR) (0.576 Mbps and 1.152 Mbps) • Fast infrared (FIR) (4 Mbps). Figure 5-95 illustrates the UART IrDA pulse parameters. Table 5-89 and Table 5-90 list the signaling rates and pulse durations for UART IrDA receive and transmit modes.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 Table 5-90. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MIN MAX 2.4 Kbps 78.1 78.1 µs 9.6 Kbps 19.5 19.5 µs 19.2 Kbps 9.75 9.75 µs 38.4 Kbps 4.87 4.87 µs 57.6 Kbps 3.25 3.25 µs 115.2 Kbps 1.62 1.62 µs 0.576 Mbps 414 419 ns 1.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com 6 Device and Documentation Support 6.1 6.1.1 Device Support Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCE), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, 27 is 275 MHz). Figure 6-1 provides a legend for reading the complete device name for any AM335x device.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 www.ti.com developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 6.2.3 Related Documentation from Other Sources The following documents are related to the AM335x MPU. Copies of these documents can be obtained directly from the internet or from your Texas Instruments representative.
AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717E – OCTOBER 2011 – REVISED JANUARY 2013 7 Mechanical Packaging and Orderable Information 7.1 Thermal Data for ZCE and ZCZ Packages Table 7-1 provides thermal characteristics for the packages used on this device. NOTE Table 7-1 provides simulation data and may not represent actual use-case values. NAME DESCRIPTION ΘJC ΘJB ΘJA ZCZ (°C/W) (2) Junction-to-case (1S0P) (3) N/A 10.3 10.2 Junction-to-board (2S2P) (3) N/A 11.6 12.1 0.
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