ADS61xx and ADS61B23EVM User's Guide Literature Number: SLAU206B September 2007 – Revised April 2008
SLAU206B – September 2007 – Revised April 2008 Submit Documentation Feedback
Contents 1 Overview ............................................................................................................................. 5 1.1 2 3 4 5 6 ADS61xx/ADS61B23 EVM Quick-Start Procedure ................................................................... 5 Circuit Description ............................................................................................................... 6 2.1 Schematic Diagram ........................................................................
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 TI ADC SPC Interface Screen ........................................................................................... Top Silkscreen .............................................................................................................. Component Side ............................................................................................................ Ground Plane 1 .......................................................................
User's Guide SLAU206B – September 2007 – Revised April 2008 1 Overview This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, ADS6145, and ADS61B23, which collectively are referred to as ADS61xx and ADS61B23.
Circuit Description 2 Circuit Description 2.1 Schematic Diagram www.ti.com The schematic diagram for the EVM is in Section 6.3. 2.2 ADC Circuit Function The following sections describe the function of individual circuits. See the relevant data sheet for device operating characteristics. 2.2.1 ADC Operational Mode By default, the ADC is configured to operate in parallel-mode operation, because jumper (J3) asserts a 3.3-V state to the ADC reset pin.
www.ti.com Circuit Description Note that the THS4509 used on this EVM is pinout compatible with the THS4508, THS4511, THS4513, and THS4520. Users can easily interchange the amplifier on this EVM and pick the appropriate amplifier based on common-mode range, power supplies, and frequency of operation. Contact your local Texas Instruments (TI) sales representative for assistance in selection of these amplifiers. 2.2.4 ADC Clock Input Connect a filtered, low-phase-noise clock input to J9.
Circuit Description www.ti.com Table 1. Breakout Board Pin Assignments ADS6122/23/B23/24/25 DESCRIPTION J4 PIN 2.2.
Circuit Description www.ti.com Table 2.
TI ADC SPI Control Interface 3 www.ti.com TI ADC SPI Control Interface This section describes the software features accompanying the EVM kit. The TI ADC SPI control software provides full control of the SPI interface, allowing users to write to any of the ADC registers found in the ADC data sheet. For most ADS61xx/ADS61B23 performance evaluations, users do not need to use the TI SPI control software to get evaluation results.
TI ADC SPI Control Interface www.ti.com 3.2 Setting Up the EVM for ADC SPI Control Users who wish to use the ADC SPI interface must supply 5 VDC to J20, which provides power to the USB circuit. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPI interface to control the ADC modes of operation, users must move several jumpers. • Move jumper J3 to short positions 1–2, which places the ADC into serial operation mode.
TI ADC SPI Control Interface www.ti.com Table 4. ADS61xx Frequently Used Registers Default Value Alternate Value ADS61xx Reset 12 2s Complement Straight Binary CMOS DDR LVDS Powerdown: OFF Powerdown On No Course Gain 3.
Connecting to FPGA Platforms www.ti.com 4 Connecting to FPGA Platforms The ADS61xx/ADS61B23 EVM provides several connection options to mate the EVM to various FPGA development platforms and FPGA-based capture boards. 4.1 TSW1100 Using the accompanying CMOS breakout board, users can easily mate TI's TSW1100 capture board to the ADS61xx/ADS61B23 EVM. Simply connect the breakout board to the J2 (Channel 2) connector on the TSW1100.
ADC Evaluation 5 www.ti.com ADC Evaluation This section describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for data-sheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal tone analysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). 5.
ADC Evaluation www.ti.com 5.2 Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is impractical when looking at a finite set of ADC samples, usually collected from a logic analyzer.
Physical Description 6 www.ti.com Physical Description This section describes the physical characteristics and PCB layout of the EVM. 6.1 PCB Layout The EVM is constructed on a four-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 2 through Figure 6. The layout features a split ground plane; however, similar performance can be obtained with careful layout using a common ground plane. Figure 2.
Physical Description www.ti.com Figure 3.
Physical Description www.ti.com Figure 4.
Physical Description www.ti.com Figure 5.
Physical Description www.ti.com Figure 6.
Physical Description www.ti.com 6.2 Bill of Materials Table 5. Bill of Materials Qty (1) Reference Not Installed Part Foot Print Part Number Manufacturer 5 C1, C5, C8, C52, C54 33 µF TANT_B B45196H2336M209 Kemet 5 C2, C9, C30, C56, C57 10 µF 805 ECJ-2FB0J106K Panasonic 3 C3, C6, C31 1 µF 603 ECJ-1VB1A105K Panasonic 43 C4, C7, C11–C29,C32–C35, C53, C55, C66, C67, C70, C72,C74, C75, C77–C79,C81, C83, C85, C87–C89, C92 0.
Physical Description www.ti.com Table 5. Bill of Materials (continued) Qty 22 Reference Not Installed Part Foot Print Part Number Manufacturer 0 R33 Not installed 200 Ω 402 ERJ-2RKF2000X Panasonic 2 R36, R48 348 Ω 603 ERJ-3EKF3480V Panasonic 0 R37, R45 499 Ω 603 ERJ-3EKF4990V Panasonic 2 R39, R43 69.8 Ω 603 ERJ-3EKF69R8V Panasonic 0 R41, R42 200 Ω 603 ERJ-3EKF2000V Panasonic 1 R49 10 kΩ 603 ERJ-3GEYJ103V Panasonic 1 R50 2.
J15 AMP EN D S MA SH2 4 3 2 5 1 VREF J8 AIN C78 .1uF 16V 1 2 .1uF R45 499 Do Not Install 1 2 11 4 17 C80 .22uF R47 49.9 348 R36 C70 .1uF 16V C81 .1uF 16V 12 3 10 9 C82 10uF 10V 348 R48 3 C84 10uF 10V PD C73 10uF 10V JP7 2 6 5 4 3 1 VREF R35 10K 1/10W 1% +5V_AMP SH2 49.9 R46 49.9 R38 C76 18pF R24 39 1/10W 1% R23 39 1/10W 1% .1uF C77 .1uF C75 0 OHM R66 Remove R66 for ADS61B23 Default: Short 2-3 -VSS_AMP TC4-1W T2 +5V_AMP C72 .1uF 16V 1 2 2 C83 .
1 SW1 100 R8 3 2 1 +3.3VD 2 SDATA R64 R19 1 0 OHM Do Not Install 2 100 Default: Shunt 1-2 J6 SERIAL INTERFACE SH5 ADCRESET +3.3VD SH4 FPGA_SDATA SH5 J3 R13 100 R10 10K R18 10K SH3 SH3 ICLKP ICLKM SH1 ICLKP ICLKM RESET SCLOCK SDA SEN VREF SH1 SH1 +3.3VD .1uF C11 DRVDD RESET SCLK SDATA SEN AGND CLKP CLKM TP4 U1 ADS614X DRVSS(GND PAD) IN_P IN_M 1 2 3 4 5 6 7 8 33 1 2 1 2 Default: Shunt 2-3 1 2 3 2 1 R6 10K TP6 R16 10 .1uF C13 .1uF C12 +3.
C22 .1uF Default: Short 1-2 1 2 3 D NE A MS J9 CLK JP8 1 2 3 C23 .1uF 1 C24 .1uF 2 C25 .1uF .1uF C20 C21 .1uF 49.9 R31 Default: Short 2-3 1 R29 49.9 1/10W 1% 2 C26 .1uF 1 JP2 2 1 2 1 4 3 2 5 2 1 2 1 2 1 2 1 C27 .1uF C29 .1uF +3.3V_AUX +3.3V_AUX C28 .1uF 60.4K R30 3 4 C19 .1uF 16V 2 5 TC1-1T 1 T3 6 2 1 2 1 1 2 3 4 5 6 JP1 Do Not Install 1 2 C17 .
Physical Description www.ti.
BLK J14 GND RED J13 +3.3VA_IN BLK J12 GND RED J11 +3.3VD_IN RED +3.3VA_IN R65 0 OHM +3.3VD_IN 5V_IN 1 68 1 1 L3 68 L2 68 L1 2 2 2 + C1 33uF C8 33uF + C30 10uF 6.3V + C5 33uF 1 2 C2 10uF 6.3V C9 10uF 6.3V C31 10V 1uF 5V 1 2 C6 1uF C3 1uF +3.3VD 1 +3.3VA C7 .1uF C4 .1uF 68 L8 2 + C57 10uF 6.3V -VSS_AMP J16 RED C52 33UF 10V +5V_AMP 1 2 1 2 1 2 J20 +5V_IN 1 2 1 1 2 2 1 1 2 1 2 1 2 1 2 -5V_IN C53 .1uF 16V 1 68 L9 5V C67 .
Physical Description www.ti.
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