ADS5525/27/45/46/47 EVM User Guide User's Guide November 2006 SLWU028B
SLWU028B – January 2006 – Revised November 2006 Submit Documentation Feedback
Contents 1 Overview .................................................................................................................... 5 1.1 2 3 EVM Basic Functions ............................................................................................ 5 EVM Quick Start Guide ................................................................................................ 6 2.1 EVM LVDS Output Mode Quick Start (Default) .............................................................. 6 2.
List of Figures 1 2 3 4 5 6 7 8 9 ADS5547 SNR Performance vs Decoupling ............................................................................. 8 THS4509 + ADS5545 EVM Performance ................................................................................ 9 Eye Diagram of Data on Header J4. ..................................................................................... 11 Top Layer..............................................................................................................
User's Guide SLWU028B – January 2006 – Revised November 2006 1 Overview This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device der many conditions. 1.1 EVM Basic Functions Analog input to the ADC is provided via external SMA connectors.
www.ti.com EVM Quick Start Guide 2 EVM Quick Start Guide The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode. Note: 2.1 EVM LVDS Output Mode Quick Start (Default) 1. 2. 3. 4. 5. 6. 7. 8. 2.2 Ensure a jumper is installed between pins 1 and 2 on JP2. Ensure DIP switch SW1, switch 2 is set to LVDS.
www.ti.com Circuit Description 3 Circuit Description 3.1 Schematic Diagram The schematic diagram for the EVM is in Section 5.3 of this document. 3.2 Circuit Function The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics. 3.2.1 Configuration Options The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is configured for parallel-mode operation.
www.ti.com Circuit Description Table 2. EVM Power Options BANANA JACK NAME VOLTAGE DESCRIPTION J9 Device AGND GND J10 AGND GND J11 Device AVDD 3.3 Device analog supply J12 Amplifier negative rail –5 THS4509 Vs– supply J13 Amplifier positive rail 5 THS4509 Vs+ supply J14 Auxiliary power 5 Supplies power to all peripheral circuitry including the FPGA and PROM. Voltages rails are created by using TI's TPS75003 voltage regulator. J15 Device DVDD 3.
www.ti.com Circuit Description The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using the THS4509 path.
www.ti.com Circuit Description Table 3.
www.ti.com Circuit Description C001 Figure 3. Eye Diagram of Data on Header J4. 3.2.6 Test Points For added EVM visibility and control, several test points are provided. Table 4 summarizes the test points available.
www.ti.com Circuit Description Table 4. Test Points TP 3.2.7 DESCRIPTION TP1 ADC common mode, input or output depending on the setting of SW1, switch 4 TP3 THS4509 power down TP4 ADC output enable TP5 AGND TP6 AGND TP7 AGND TP8 DGND TP9 FPGA M0 pin; determines which FPGA logic file to load TP10 ADC SCLK TP11 TPS75003 1.2 enable TP12 TPS75003 2.5 enable TP13 TPS75003 3.3 enable LED Operation To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4.
www.ti.com Expansion Options 4 Expansion Options The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to develop a custom prototype board. 4.1 Custom FPGA Code Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA, rapidly speeding up digital development time.
www.ti.com Physical Description 5 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM. 5.1 PCB Layout The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 4 through Figure 9. The layout features split analog and digital ground planes; however, similar performance can be had with careful layout using a single ground plane.
www.ti.com Physical Description K002 Figure 5.
www.ti.com Physical Description K003 Figure 6.
www.ti.com Physical Description K004 Figure 7.
www.ti.com Physical Description K005 Figure 8.
www.ti.com Physical Description K006 Figure 9.
www.ti.com Physical Description 5.
www.ti.com Physical Description Table 5. Bill of Materials VALUE FOOTPRINT QTY PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR NOT INSTALLED CAPACITORS 47-µF, tantalum, 20%, 10-V 7343 4 ECS-T1AD476R Panasonic PCS2476CT-ND C65, C66, C68, C69 10-µF, 10-V, 20% 3528 5 ECS-T1AX106R Panasonic PCS2106CT-ND C70, C71, C72, C73, C74 10-µF, 10-V, 20% 3216 2 ECS-T1AY106R Panasonic P11309CT-ND C8, C9 100-µF, 6.3-V, 10% 6032 2 TPSC107K006R0150 AVX 478-1764-2-ND C35, C60 0.
www.ti.com Physical Description Table 5. Bill of Materials (continued) VALUE FOOTPRINT QTY PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR ERJ-3GEY0R00V Panasonic P0.0GCT-ND R5, R6, R10, R18, R48, R58, R82 R11, C45, C47 NOT INSTALLED RESISTORS 0-Ω, 1/10-W, 5% 603 7 0-Ω, 1/10-W, 5% 402 3 ERJ-GE0R00X Panasonic P0.0JCT-ND 4.02-Ω, 1/10-W 1% 603 2 9C06031A4R02FGHFT Yageo 311-4.02HCT-ND 20-Ω, 1/16-W, 1% 603 1 ERJ-3EKF20R0V Panasonic P20.0HCT-ND R79 24.
www.ti.com Physical Description Table 5. Bill of Materials (continued) VALUE FOOTPRINT QTY PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR NOT INSTALLED FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, ETC. Ferrite bead 1206 5 Inductor, SMT, 15-µH, 2.6-A COIL-CDRH8D43 Inductor, SMT, 5-µH, 2.9-A COIL-CDRH6D38 0.
www.ti.com Physical Description Table 5.
www.ti.com Physical Description 5.3 PCB Schematics The schematics for the EVM are on the following pages.
U2A XILINX XC3S500E_FT256 DRVDD D C3 C1 .1uF .1uF + C8 10uF CLKOUTM CLKOUTP AVDD + C9 C4 C5 C6 C7 C10 C19 10uF .1uF .1uF .1uF .1uF .1uF .1uF D12_D13P D12_D13M A9 A10 D10_D11P D10_D11M D8_D9P D8_D9M D6_D7P D6_D7M D4_D5P D4_D5M B8 A8 D8 C8 D7 E7 D6 C6 E6 D5 A4 A5 C4 C5 B3 C3 A3 C13 C12 D12 C9 C10 D2_D3P D2_D3M U1-H6 (Sh 4) U1-H5 U1-H6 U1-H5 3.3V R3 R27 R30 10K 4.
1 2 3 4 5 6 +VCC AMPLIFIER PATH: C11 C12 .1uF .1uF C13 C40 10uF AC Couple (default) 10uF C45 C47 = 0.1uF R26 R27 = 200 Ohms R5 = 0 Ohms VCC= 5 V, VEE = GND R24 348 D D TP3 DC Couple .1uF VCM 7 8 R44 L3 49.9 R85 0 ohm Vs+ Vs+ 0 ohm C2 4.7 200 20pF C47 Vin+ Vout- R43 10 CM C119 CM L4 49.9 C118 0 ohm 0 ohm CM C49 20pF R86 R47 20pF 200 AMP_M 4.7 16 499 15 R21 14 R84 .1uF 9 .
1 2 3 4 5 6 D D 1 (Note 1) J7 CLK_INP R54 2 0 C25 6 T3 1 5 4 3 2 R59 2 49.9 (Note 1) 4 100 .1uF SJP2 3 2 CLKP CLKP (Sh 1) 0 C26 .1uF 3 (1-2) R56 1 (Note 1) 1 R58 5 4 3 2 R31 100 TC4-1W J8 CLK_INM (Note 1) R60 1 1 0 2 SJP1 CLKM CLKM (Sh 1) 3 (1-2) C C B B ti A A 12500 TI Boulevard. Dallas, Texas 75243 Title: Note 1. Part not installed Engineer: J. VENABLE Drawn By: Y.
1 2 3 4 5 U2B XILINX XC3S500E_FT256 5V J5 J4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 D R79 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 CLKOUT 20 RP1 20 Ohm 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D11 ADC_D12 ADC_D13 ADC_D14 ADC_D15 RP2 20 Ohm 40PIN_IDC 1 3 5 7 9 11 13 15 17 19 21 23 25 27
1 2 3 4 R88 2.5V 5 6 3.3V 330 D4 LED_1206 R49 4.75K VCCINT VCCINT VCCINT 3.
1 2 3 4 L1 1 D 2 S 2 VCCO_0 CDRH8D43-150 15uH .01uF 1.5nF 1.5nF 2.2uF SS32 R61 .033 TP11 5V C42 C48 .22uF .22uF C97 C99 100uF Q1 FET-SI2323DS C31 C85 .022uF .022uF D 2 D C58 BANK 0 DECOUPLING C60 + D1 C57 6 1.2V 1 1 G 3 5 5V R8 SW1 SS3 .1uF 12 13 14 16 15 17 19 18 IS1 IN1 SW1 DGND SS1 EN1 1uF 20 IN3 2.2uF C43 C50 .22uF .22uF C98 .022uF C100 .022uF 11 FB1 J20 U6 IS2 IN2 SW2 FB2 10 FB2 DGND SS2 EN2 R63 BANK 2 DECOUPLING 3.
1 2 3 4 5 6 Diff Amp Positive Supply (+5.0V) RED D +VCC FB3 J13 ADC Analog Supply (+3.3V) C66 C34 C71 + D + .1uF +3.3VA-PS 47uF AVDD 10uF J10 FB2 J11 BLACK C65 C32 + C70 C33 + .1uF .1uF 47uF Diff Amp Negative Supply (-5.0V) 10uF J9 -VCC FB4 J12 BLACK C68 C37 + RED .1uF C73 + RED 47uF 10uF C C TP5 ADC DIGITAL SUPPLY(3.3V) TP6 TP7 FPGA POWER SUPPLY(5V) OUTPUT_BUFFER DRVDD FB7 5V FB6 J15 J14 RED C38 C69 + C74 C39 + .
www.ti.com Physical Description EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
www.ti.com Physical Description FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
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