July 13, 2011 Revision 1.
-2- Table of Contents 1.0 Overview 1.1 Features 1.2 Packing List 1.3 References 2.0 Quick Start 2.1 Installing the WaveVision 5 Software 2.2 Installing the ADC12D1X00RFRB Hardware 2.3 Launching the WaveVision 5 Software 2.4 WaveVision 5 – User Interface Overview 2.5 System / Device Configuration 2.6 Data Capturing 3.0 Secondary Panel Description 4.0 Reference Board Functional Description 4.1 System Block Diagram 4.2 System Description 5.
-3- 1.0 Overview The ADC12D1X00RFRB demonstrates a high-performance signal acquisition sub-system that achieves 12-bit resolution and corresponding SNR and dynamic range on two channels at signal frequencies in excess of 1.0 GHz and sampling rates of at least 1.6/1.8 GS/s or one channel at a sampling rate of 3.2/3.6 GHz.
-4- 1.1 Features Demonstrates the ADC12D1X00RF's typical dynamic performance – see the datasheet for full details. Dual channel sample rates of up to 1.6/1.8 GS/s (limited by the ADC specifications and the FPGA capture limitations) Single channel (Interleaved) sample rates of up to 3.2/3.
-5- 1.4 Board Orientation Ext. Trigger Input LMX2531 Int Clock Q-ch. Sig. Input DCLK_RST Ext Clock Input I-ch. Sig. Input ADC Control Jumpers LEDs ADC12D1X00RF * Power section Power Jack +7.
-6- Figure 2: Jumpers and LEDs Copyright 2011 National Semiconductor Corporation
-7- 2.0 Quick Start This section will aid in bringing up the board for the first time as well as a brief tutorial on the WaveVision 5 (WV5) software. Further description of the Reference Board is in subsequent sections of this document. The software is further described in the WaveVision 5 Users' Guide or the HELP function within the software. The ADC12D1X00RF and LMX2531 datasheets should be consulted for detailed understanding of device functionality.
-8- 2.1 Installing the WaveVision 5 Software (Note: The WaveVision 5 software requires Windows XP 32-bit operating system) 1. Insert the included WaveVision 5 CD-ROM into the computer CD drive. 2. Locate, unzip and run the install.bat program on the CD-ROM. 3. Follow the on-screen instructions to complete the installation. 2.2 Installing the ADC12D1X00RFRB Hardware 1. Place the ADC12D1X00RFRB Reference Board on a clean, static-free surface. 2.
-9- 2.3 Launch the WaveVision 5 Software. Start the WaveVision 5 software on your computer by selecting the desktop icon “WaveVision 5” or by clicking on the Start button, and selecting Programs -> WaveVision 5 -> WaveVision 5 The software will automatically detect the board and load the appropriate software profile and will proceed to download the controller firmware and FPGA code onto the reference board. As an alternative, the icon on the desktop can be used to launch WaveVision 5.
- 10 - 2.4 WaveVision 5 - User Interface Overview Figure 4: WaveVision 5 Example Window Figure 4 above shows the WV5 user interface panel (GUI). This is the top level interface panel. It is arranged in such a way that the plot is always in the middle. There are tabs arranged on each side of the window to give the user additional information or control of features.
- 11 - 2.5 System / Device Configuration Prior to capturing data, confirm that the board is in the "ECE (Extended Control Enable)" mode, The ECE jumper is located in the ADC pin control jumper area as shown in Figure 2. The board should be sent with this jumper in place. This means that the ADC will be controlled through the SPI interface and not with jumpers driving the control pins. This allows the user to control the ADC's behavior through the WaveVision 5 Registers panel.
- 12 - 2.5.1 Main Panel The main menu bar of the WaveVision 5 software has several control buttons as shown in Figures 5 and 6, which may be used to perform most tasks with a button click. 1 - Load Plot A new plot window is created and the Plot Load dialog is displayed. The selected plot file is loaded into the new window. 2 - Import Data Clicking this button creates a new time-domain plot and opens the Import Data dialog.
- 13 - 2.5.2 Plot Window Controls Figure 7: WaveVision 5 plot window controls 1 - Load Plot The Plot Load dialog is displayed, and the selected plot file is loaded into the new window. 2 - Save Plot Displays the Plot Save dialog (this button is only active when the plot contains one or more channels with data). 3 - Reset Zoom Reset X and Y axis zoom to 100%. 4 - Clear Clear data from all channels. 5 - Print Print the plot. 6 - Time Domain Display the plot as time domain data.
- 14 - 2.5.3 Right Panels – Signal Source Figure 8a: WaveVision 5 main window command buttons Open the Signal Source panel on the right side of the window and confirm that the ADC12D1X00RFRB is available and confirm that it is selected.
- 15 - Note – When using “I and Q” mode, it is also necessary to select the Channels tab and deselect the “Automatically hide inactive channels” option box in order to allow both channels to appear on the plot.
- 16 - Figure 9: WaveVision 5 main window command buttons • • • • • Sampling Rate - When the signal source panel is selected, the clock frequency is displayed. This is initially the internal clock. In this example, 1800 MHz is generated by the LMX2531 on the reference board. The sampling rate is determined by the FPGA when the board is powered up. The calculation is accurate to better than 1%. If an external source is in use, confirm that this number corresponds to the clock reference that is applied.
- 17 - 2.5.4 Right Panels - Registers Next, configure the hardware (including the ADC) using the Registers control panel on the right side. This is the most important of all the panels for controlling the ADC12D1X00RFRB. This panel has twelve sub-tabs that control the settings of the board and registers inside the ADC12D1X00RF. The twelve sub-tabs are shown below and include; Settings, Config, Cal Adjust, I-channel, Q-channel, DES Adjust, tAD Adjust, AutoSync, and Temperature.
- 18 - Config: This tab configures various features and modes of the ADC12D1X00RF and is shown below. It accesses or changes the following functions, all of which are controlled through Configuration Register 1. Figure 11: Config Panel • • • • • • • • DPS – DDR Phase Select – o In DDR, this determines the DDR Data-to-DCLK phase relationship. When unchecked, the 0° Mode is selected. When checked the 90° Mode is selected.
- 19 - Cal Adjust: This tab controls the various adjustments which may be made to the Calibration feature. Figure 11a: Cal Adjust Panel • • CSS – Skip or include Rtrim calibration. When the Rtrim has been completed once, it is not necessary to do it again until the device is power cycled. SSC – Calibration control via the SPI, i.e. not the pin-controlled option for calibration. Note: No changes will take effect until the Write Config Reg button is clicked.
- 20 - I-channel: This tab changes the sign and the magnitude of the offset and the full scale range settings. Figure 12: I-Channel Panel • • • I-channel Offset Sign – This pull-down selects a positive or negative offset. I-ch Offset – This slider selects the magnitude of I-ch Offset applied. Adjustment can be done using the computer mouse/pointer, or using left/right arrow keys once the slider has been selected.
- 21 - DES Adjust: This tab controls the DES Mode time skew function. Figure 12a: DES Adjust Panel Set DES Mode time skew – This slider adjusts the time skew between the falling edge sampling clock relative to the rising edge sampling clock in DES mode. Adjustment can be done using the computer mouse/pointer, or using left/right arrow keys once the slider has been selected. Although the time skew is entered in 8 bit (0 to 127) relative form, it is also displayed in approximate fs.
- 22 - tAD Adjust: This tab controls the Aperture Delay function. Figure 13: tAD Adjust Panel • • • • • DCC – Duty Cycle Correction – When checked (default), the automatic Duty Cycle Correction circuit is enabled. STA - Select tAD Adjust – When checked, enables the Aperture Delay Time coarse adjust feature. Coarse Phase Adjust – Sets the approximate amount of coarse Aperture Delay applied. Fine Phase Adjust – Sets the approximate amount of fine Aperture Delay applied.
- 23 - AutoSync: This tab enables and controls the settings of the AutoSync feature. Figure 15: AutoSync Panel • • • • • DR – Disable DCLK Reset – When checked (default) disables the DCLK Reset feature DOC – Disable Output reference Clocks – When checked (default) disables the AutoSync reference output clocks. When un-checked a CLK/4 signal is sent on the RCOut1 and RCOut2 outputs. ES – Enable Slave mode – When checked configures this ADC as an AutoSync slave device.
- 24 - Temperature: This panel provides a read-out of three different temperatures in the ADC12D1X00RFRB. Figure 16: Temperature Panel • • • Ambient Temperature – Provides the local/board temperature of the LM95233 IC. ADC Temperature – Provides the approximate die temperature of the ADC12D1X00RF. FPGA Temperature – Provides the approximate die temperature of the Xilinx Virtex-4 FPGA. Note: No changes will appear until the Update Temperatures button is clicked.
- 25 - Debug Tabs: These panels provide the actual register settings which are conveniently formatted in the other tabs above. They may also be read to and written from and these changes will be reflected in the corresponding tabs. Figure 16: Debug Panel Note: No changes will appear until the Read/Write button is clicked. Special Note: Register 6h must be programmed to 1C0Eh before calibrating for the ADC12D1800RF to function properly.
- 26 - 2.6 Data Capturing The board is now ready for a data capture. Before proceeding, perform a manual calibration of the ADC. Even though the ADC performs a self-calibration at the time of power-up, it is recommended that the user perform another calibration after sufficient time has passed for the system (primarily temperature) to stabilize. Manual calibration is performed by clicking the Calibrate ADC feature in the Register control panel, Settings sub-tab. 2.6.
- 27 - 2.6.4 External Clock Source It is also possible to apply a high-quality external signal source to the clock input rather than using the on-board LMX2531 clock synthesizer. This will help quantify the LMX2531's performance in an ultra-high-speed signal-path such as this one. When connecting an external clock source, the generator amplitude should be set to 0dBm. Experiment with the clock signal strength to determine what effect this has on the channel performance.
- 28 - 3.0 Secondary Panel Description Please refer to the WaveVision 5 Users Guide for detailed descriptions of the remaining Left and Right panels, and additional Main Panel features.
- 29 - 4.0 Reference Board Functional Description 4.1 System Block Diagram 7.5V Power Management Analog_3.3/5.0V (for off-board use) Analog_3.3V Analog_1.9V Power Sequencing Control Digital_3.3V Digital_2.5V Digital_1.8V Digital_1.2V EEPROM Temp Sensor (LM95233) Analog Front-End Boards Plug-in Here (LMH6518, Balun, RF) I2C Vreg 2 VinI+/- ORI/Q ADR/DATA 12x2 VinQ+/ - ADC12D1X00RF Vcmo 12x2 2 DCLKI/Q Xilinx Virtex-4 FPGA USB Ctrlr. FIFO I/F SPI(1.
- 30 - 4.2 System Description 4.2.1 The ADC12D1X00RF ADC12D1X00RF forms the heart of this reference board. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 12-bit resolution at guaranteed minimum sampling rates of 1.6/1.8 Gs/s in dual channel configuration and 3.2/3.6 Gs/s in single channel configuration.
- 31 - 4.2.3 FPGA The design employs a Xilinx Virtex-4 FPGA for capturing the digital data. While the board is powered up and configured, the FPGA is continually receiving data from the ADC. In response to a user command through the WV-5 software, the ADC captures the desired amount of data in its on-chip buffer (up to a maximum of 32K samples per-channel). The user can then command the FPGA to upload the captured data to the PC through the USB interface for further processing.
- 32 - Auxiliary Port: FMC connector forms an auxiliary data port. With it, the FPGA captures the ADC’s high-speed continuous streaming data and retransmits the data out of the FMC port. See photo below of the FMC port on the bottom of the board. • • Install J155 to force FPGA to output data on FMC port (without a power good signal from Carrier to Mezzanine).
- 33 - AutoSync SMA connectors: Needs resistor jumper modification to evaluate AutoSync on the reference board. See schematic to find the resistor locations. • Remove DCLKQ+/-, RCOUT1+/- to FPGA (Remove R162, R163, R158, R159) • Route DCLKQ+/-, RCOUT1+/-, RCLK+/- to SMA connectors (Stuff 0ohm resistors to R161, R164, R157, R160, R145, R147) Enable AutoSync output by going to Wavevision 5 Software GUI -> Registers tab -> AutoSync panel -> Uncheck DOC and click ‘Write AutoSync Reg’.
- 34 - 5.0 Electrical Specification Power Supply: Nominal = 7.5V Minimum = 7.0V, Maximum = 8.0V (Voltages outside these levels will cause damage!!) Power Consumption: Nominal = 10 Watts Maximum = 20 Watts ADC Input Signals: Maximum Operating Voltage = see datasheet Recommended/initial (full scale) generator setting = 0 dBm (The maximum level at the signal generator is dependent upon the insertion loss from other hardware before the ADC inputs.
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