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ADC12C105

www.ti.com

SNAS417B –MAY 2007–REVISED AUGUST 2007

ADC12C105 12-Bit, 95/105 MSPS A/D Converter

Check for Samples: ADC12C105

FEATURES

DESCRIPTION

The ADC12C105 is a high-performance CMOS

• 1 GHz Full Power Bandwidth

analog-to-digital converter capable of converting

• Internal Reference and Sample-and-Hold

analog input signals into 12-bit digital words at rates

Circuit

up to 105 Mega Samples Per Second (MSPS). This

• Low Power Consumption

converter uses a differential, pipelined architecture

with digital error correction and an on-chip sample-

• Data Ready Output Clock

and-hold circuit to minimize power consumption and

• Clock Duty Cycle Stabilizer

the external component count, while providing

• Single +3.0V or +3.3V Supply Operation

excellent dynamic performance. A unique sample-

and-hold stage yields a full-power bandwidth of 1

• Power-Down Mode

GHz. The ADC12C105 may be operated from a

• 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm

single +3.0V or +3.3V power supply and consumes

Pin-Pitch)

low power.

A separate +2.5V supply may be used for the digital

APPLICATIONS

output interface which allows lower power operation

• High IF Sampling Receivers

with reduced noise. A power-down feature reduces

the power consumption to very low levels while still

• Wireless Base Station Receivers

allowing fast wake-up time to full operation. The

• Test and Measurement Equipment

differential inputs accept a 2V full scale differential

• Communications Instrumentation

input swing. A stable 1.2V internal voltage reference

• Portable Instrumentation

is provided, or the ADC12C105 can be operated with

an external 1.2V reference. Output data format (offset

binary versus 2's complement) and duty cycle

KEY SPECIFICATIONS

stabilizer are pin-selectable. The duty cycle stabilizer

• Resolution 12 Bits

maintains performance over a wide range of clock

• Conversion Rate 105 MSPS

duty cycles.

• SNR (f

= 240 MHz) 69 dBFS (typ)

The ADC12C105 is available in a 32-lead WQFN

• SFDR (f

= 240 MHz) 82 dBFS (typ)

package and operates over the industrial temperature

range of −40°C to +85°C.

• Full Power Bandwidth 1 GHz (typ)

• Power Consumption

– 350 mW (typ), V

=3.0 V

– 400 mW (typ), V

=3.3 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 ADC12C105 12-Bit, 95/105 MSPS A/D Converter Check for Samples: ADC12C105 FEATURES DESCRIPTION • • The ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS).
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 5 VIN+ VA 6 Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. VIN- AGND 2 VRP 32 VCMO VA VA VA 1 VRN VA These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Pin Descriptions and Equivalent Circuits (continued) Pin No. Symbol Equivalent Circuit Description DIGITAL I/O 11 CLK VA 30 The clock input pin. The analog input is sampled on the rising edge of the clock input. This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Absolute Maximum Ratings (1) (2) (3) −0.3V to 4.2V Supply Voltage (VA, VDR) −0.3V to (VA +0.3V) Voltage on Any Pin (Not to exceed 4.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Dynamic Converter Electrical Characteristics at 95MSPS Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 95 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Transfer Characteristic Figure 2.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. 14 DNL INL Figure 3. Figure 4. DNL vs. fCLK INL vs. fCLK Figure 5. Figure 6. DNL vs. Temperature INL vs. Temperature Figure 7. Figure 8.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Typical Performance Characteristics DNL, INL (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. DNL vs. VA INL vs. VA Figure 9. Figure 10.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Typical Performance Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. 16 SNR, SINAD, SFDR vs. VA Distortion vs. VA Figure 11. Figure 12. SNR, SINAD, SFDR vs. VDR Distortion vs. VDR Figure 13. Figure 14.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. SNR, SINAD, SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle Figure 17. Figure 18. SNR, SINAD, SFDR vs.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. 18 SNR, SINAD, SFDR vs. Temperature Distortion vs. Temperature Figure 23. Figure 24.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Typical Performance Characteristics (continued) Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 10 MHz, CL = 5 pF/pin. Typical values are for TA = 25°C. Power vs. fCLK Figure 29.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com FUNCTIONAL DESCRIPTION Operating on a single +3.3V supply, the ADC12C105 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 EFS = 4096 ( 1 - sin (90° + dev)) (5) Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see Figure 31). For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. Figure 31.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs for low frequency applications.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 DIGITAL INPUTS Digital CMOS compatible inputs consist of CLK, and PD. Clock Input The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input signal should also have a short transition region.
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ADC12C105 SNAS417B – MAY 2007 – REVISED AUGUST 2007 www.ti.com 2.4 to VA Volts +3.3V CHOKE 2 x 0.1 PF + 10 PF 31 1 PF 0.1 PF 32 0.1 PF 2 50 1 PF 20 10 PF V DR VA 3 VA 8 10 VA 0.1 PF VREF (MSB) D11 D10 D9 D8 VCMO V RP 0.1 PF 0.1 PF 1 0.1 PF 0.1 PF 5 T1 18 pF 2 0.1 PF 0.
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ADC12C105 www.ti.com SNAS417B – MAY 2007 – REVISED AUGUST 2007 Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC12C105CISQ/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 ADC12C105CISQE/NOPB WQFN RTV 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC12C105CISQ/NOPB WQFN RTV 32 1000 203.0 190.0 41.0 ADC12C105CISQE/NOPB WQFN RTV 32 250 203.0 190.0 41.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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