Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply SOT 23 6

3 4

GND

SDATA

SCLK

ADC081S101

www.ti.com

SNAS310C –JANUARY 2006–REVISED MARCH 2013

ADC081S101 Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter

Check for Samples: ADC081S101

FEATURES

DESCRIPTION

The ADC081S101 is a low-power, single channel

• Specified Over a Range of Sample Rates.

CMOS 8-bit analog-to-digital converter with a high-

• 6-Lead WSON and SOT-23 Packages

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC081S101 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 500 ksps to 1 Msps. The

• SPI™/QSPI™/MICROWIRE/DSP Compatible

converter is based upon a successive-approximation

APPLICATIONS

circuit.

• Portable Systems

The output serial data is straight binary, and is

• Remote Data Aquisitions

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

• Instrumentation and Control Systems

serial interfaces.

KEY SPECIFICATIONS

The ADC081S101 operates with a single supply that

can range from +2.7V to +5.25V. Normal power

• DNL ± 0.07 LSB (typ)

consumption using a +3V or +5V supply is 2.0 mW

• INL ± 0.05 LSB (typ)

and 10.0 mW, respectively. The power-down feature

• SNR 49.7 dB (typ)

reduces the power consumption to just 2.5 µW using

a +5V supply.

• Power Consumption

The ADC081S101 is packaged in an 6-lead WSON

– 3V Supply 2.0 mW (typ)

and SOT-23 packages. Operation over the industrial

– 5V Supply 10.0 mW (typ)

temperature range of −40°C to +85°C is ensured.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC101S101

8-bit ADC081S021 ADC081S051 ADC081S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Figure 1. 6-Lead SOT-23 or WSON

See DBV or NGF Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 ADC081S101 Single Channel, 0.5 to 1 Msps, 8-Bit A/D Converter Check for Samples: ADC081S101 FEATURES DESCRIPTION • • • • • The ADC081S101 is a low-power, single channel CMOS 8-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC081S101 is fully specified over a sample rate range of 500 ksps to 1 Msps.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Block Diagram VIN T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA 6 CS Chip select. On the falling edge of CS, a conversion process begins.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA Voltage on Any Pin to GND −0.3V to (VA +0.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com ADC081S101 Converter Electrical Characteristics (1) (2) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 ADC081S101 Converter Electrical Characteristics (1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com ADC081S101 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10.0 MHz to 20.0 MHz, CL = 25 pF, fSAMPLE = 500 ksps to 1 Msps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Track Hold | CS tCS tSU tACQ tCL 1 2 3 | SCLK 4 5 14 15 16 Z1 Z0 DB7 3 leading zero bits 17 18 19 20 tQUIET tCH | Z2 13 tACC tEN SDATA 12 tH tDIS TRI-STATE Zero Zero 8 data bits Zero Zero 4 trailing zeroes Figure 3. ADC081S101 Serial Timing Diagram Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC081S101 is ensured not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 1 LSB).
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. DNL fSCLK = 10 MHz INL fSCLK = 10 MHz Figure 4. Figure 5. DNL fSCLK = 20 MHz INL fSCLK = 20 MHz Figure 6. Figure 7. DNL vs Clock Frequency INL vs Clock Frequency Figure 8. Figure 9.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. 10 Total Unadjusted Error vs Clock Frequency SNR vs Clock Frequency Figure 10. Figure 11. SINAD vs. Clock Frequency THD vs. Clock Frequency Figure 12. Figure 13. SFDR vs. Clock Frequency Spectral Response, VA = 5V fSCLK = 10 MHz Figure 14. Figure 15.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated. Spectral Response, VA = 5V fSCLK = 20 MHz Power Consumption vs. Throughput, fSCLK = 20 MHz Figure 16. Figure 17.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC081S101 Operation The ADC081S101 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC081S101 in both track and hold operation are shown in Figure 18 and Figure 19, respectively.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by eight data bits, most significant first. After the data bits, the ADC will clock out four trailing zeros.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com Typical Application Circuit A typical application of the ADC is shown in Figure 21. Power is provided in this example by the TI LP2950 lowdropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply will degrade device noise performance.
PAGE 15
ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 Modes of Operation The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought low again.
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ADC081S101 SNAS310C – JANUARY 2006 – REVISED MARCH 2013 www.ti.com If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully powered-up after 16 SCLK cycles.
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ADC081S101 www.ti.com SNAS310C – JANUARY 2006 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC081S101CIMF/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADC081S101CISD/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 NGF 6 4500 330.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC081S101CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 WSON NGF 6 1000 210.0 185.0 35.0 WSON NGF 6 4500 367.0 367.0 35.
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MECHANICAL DATA NGF0006A www.ti.
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